1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas R0P7757LC0012RL Support.
4 *
5 * Copyright (C) 2009 - 2010 Renesas Solutions Corp.
6 */
7
8 #include <linux/init.h>
9 #include <linux/platform_device.h>
10 #include <linux/gpio.h>
11 #include <linux/irq.h>
12 #include <linux/regulator/fixed.h>
13 #include <linux/regulator/machine.h>
14 #include <linux/spi/spi.h>
15 #include <linux/spi/flash.h>
16 #include <linux/io.h>
17 #include <linux/mmc/host.h>
18 #include <linux/platform_data/sh_mmcif.h>
19 #include <linux/platform_data/tmio.h>
20 #include <linux/sh_eth.h>
21 #include <linux/sh_intc.h>
22 #include <linux/usb/renesas_usbhs.h>
23 #include <cpu/sh7757.h>
24 #include <asm/heartbeat.h>
25
26 static struct resource heartbeat_resource = {
27 .start = 0xffec005c, /* PUDR */
28 .end = 0xffec005c,
29 .flags = IORESOURCE_MEM | IORESOURCE_MEM_8BIT,
30 };
31
32 static unsigned char heartbeat_bit_pos[] = { 0, 1, 2, 3 };
33
34 static struct heartbeat_data heartbeat_data = {
35 .bit_pos = heartbeat_bit_pos,
36 .nr_bits = ARRAY_SIZE(heartbeat_bit_pos),
37 .flags = HEARTBEAT_INVERTED,
38 };
39
40 static struct platform_device heartbeat_device = {
41 .name = "heartbeat",
42 .id = -1,
43 .dev = {
44 .platform_data = &heartbeat_data,
45 },
46 .num_resources = 1,
47 .resource = &heartbeat_resource,
48 };
49
50 /* Fast Ethernet */
51 #define GBECONT 0xffc10100
52 #define GBECONT_RMII1 BIT(17)
53 #define GBECONT_RMII0 BIT(16)
54 static void sh7757_eth_set_mdio_gate(void *addr)
55 {
56 if (((unsigned long)addr & 0x00000fff) < 0x0800)
57 writel(readl(GBECONT) | GBECONT_RMII0, GBECONT);
58 else
59 writel(readl(GBECONT) | GBECONT_RMII1, GBECONT);
60 }
61
62 static struct resource sh_eth0_resources[] = {
63 {
64 .start = 0xfef00000,
65 .end = 0xfef001ff,
66 .flags = IORESOURCE_MEM,
67 }, {
68 .start = evt2irq(0xc80),
69 .end = evt2irq(0xc80),
70 .flags = IORESOURCE_IRQ,
71 },
72 };
73
74 static struct sh_eth_plat_data sh7757_eth0_pdata = {
75 .phy = 1,
76 .set_mdio_gate = sh7757_eth_set_mdio_gate,
77 };
78
79 static struct platform_device sh7757_eth0_device = {
80 .name = "sh7757-ether",
81 .resource = sh_eth0_resources,
82 .id = 0,
83 .num_resources = ARRAY_SIZE(sh_eth0_resources),
84 .dev = {
85 .platform_data = &sh7757_eth0_pdata,
86 },
87 };
88
89 static struct resource sh_eth1_resources[] = {
90 {
91 .start = 0xfef00800,
92 .end = 0xfef009ff,
93 .flags = IORESOURCE_MEM,
94 }, {
95 .start = evt2irq(0xc80),
96 .end = evt2irq(0xc80),
97 .flags = IORESOURCE_IRQ,
98 },
99 };
100
101 static struct sh_eth_plat_data sh7757_eth1_pdata = {
102 .phy = 1,
103 .set_mdio_gate = sh7757_eth_set_mdio_gate,
104 };
105
106 static struct platform_device sh7757_eth1_device = {
107 .name = "sh7757-ether",
108 .resource = sh_eth1_resources,
109 .id = 1,
110 .num_resources = ARRAY_SIZE(sh_eth1_resources),
111 .dev = {
112 .platform_data = &sh7757_eth1_pdata,
113 },
114 };
115
116 static void sh7757_eth_giga_set_mdio_gate(void *addr)
117 {
118 if (((unsigned long)addr & 0x00000fff) < 0x0800) {
119 gpio_set_value(GPIO_PTT4, 1);
120 writel(readl(GBECONT) & ~GBECONT_RMII0, GBECONT);
121 } else {
122 gpio_set_value(GPIO_PTT4, 0);
123 writel(readl(GBECONT) & ~GBECONT_RMII1, GBECONT);
124 }
125 }
126
127 static struct resource sh_eth_giga0_resources[] = {
128 {
129 .start = 0xfee00000,
130 .end = 0xfee007ff,
131 .flags = IORESOURCE_MEM,
132 }, {
133 /* TSU */
134 .start = 0xfee01800,
135 .end = 0xfee01fff,
136 .flags = IORESOURCE_MEM,
137 }, {
138 .start = evt2irq(0x2960),
139 .end = evt2irq(0x2960),
140 .flags = IORESOURCE_IRQ,
141 },
142 };
143
144 static struct sh_eth_plat_data sh7757_eth_giga0_pdata = {
145 .phy = 18,
146 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
147 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
148 };
149
150 static struct platform_device sh7757_eth_giga0_device = {
151 .name = "sh7757-gether",
152 .resource = sh_eth_giga0_resources,
153 .id = 2,
154 .num_resources = ARRAY_SIZE(sh_eth_giga0_resources),
155 .dev = {
156 .platform_data = &sh7757_eth_giga0_pdata,
157 },
158 };
159
160 static struct resource sh_eth_giga1_resources[] = {
161 {
162 .start = 0xfee00800,
163 .end = 0xfee00fff,
164 .flags = IORESOURCE_MEM,
165 }, {
166 /* TSU */
167 .start = 0xfee01800,
168 .end = 0xfee01fff,
169 .flags = IORESOURCE_MEM,
170 }, {
171 .start = evt2irq(0x2980),
172 .end = evt2irq(0x2980),
173 .flags = IORESOURCE_IRQ,
174 },
175 };
176
177 static struct sh_eth_plat_data sh7757_eth_giga1_pdata = {
178 .phy = 19,
179 .set_mdio_gate = sh7757_eth_giga_set_mdio_gate,
180 .phy_interface = PHY_INTERFACE_MODE_RGMII_ID,
181 };
182
183 static struct platform_device sh7757_eth_giga1_device = {
184 .name = "sh7757-gether",
185 .resource = sh_eth_giga1_resources,
186 .id = 3,
187 .num_resources = ARRAY_SIZE(sh_eth_giga1_resources),
188 .dev = {
189 .platform_data = &sh7757_eth_giga1_pdata,
190 },
191 };
192
193 /* Fixed 3.3V regulator to be used by SDHI0, MMCIF */
194 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
195 {
196 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
197 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
198 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
199 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
200 };
201
202 /* SH_MMCIF */
203 static struct resource sh_mmcif_resources[] = {
204 [0] = {
205 .start = 0xffcb0000,
206 .end = 0xffcb00ff,
207 .flags = IORESOURCE_MEM,
208 },
209 [1] = {
210 .start = evt2irq(0x1c60),
211 .flags = IORESOURCE_IRQ,
212 },
213 [2] = {
214 .start = evt2irq(0x1c80),
215 .flags = IORESOURCE_IRQ,
216 },
217 };
218
219 static struct sh_mmcif_plat_data sh_mmcif_plat = {
220 .sup_pclk = 0x0f,
221 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA |
222 MMC_CAP_NONREMOVABLE,
223 .ocr = MMC_VDD_32_33 | MMC_VDD_33_34,
224 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
225 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
226 };
227
228 static struct platform_device sh_mmcif_device = {
229 .name = "sh_mmcif",
230 .id = 0,
231 .dev = {
232 .platform_data = &sh_mmcif_plat,
233 },
234 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
235 .resource = sh_mmcif_resources,
236 };
237
238 /* SDHI0 */
239 static struct tmio_mmc_data sdhi_info = {
240 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI_TX,
241 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI_RX,
242 .capabilities = MMC_CAP_SD_HIGHSPEED,
243 };
244
245 static struct resource sdhi_resources[] = {
246 [0] = {
247 .start = 0xffe50000,
248 .end = 0xffe500ff,
249 .flags = IORESOURCE_MEM,
250 },
251 [1] = {
252 .start = evt2irq(0x480),
253 .flags = IORESOURCE_IRQ,
254 },
255 };
256
257 static struct platform_device sdhi_device = {
258 .name = "sh_mobile_sdhi",
259 .num_resources = ARRAY_SIZE(sdhi_resources),
260 .resource = sdhi_resources,
261 .id = 0,
262 .dev = {
263 .platform_data = &sdhi_info,
264 },
265 };
266
267 static int usbhs0_get_id(struct platform_device *pdev)
268 {
269 return USBHS_GADGET;
270 }
271
272 static struct renesas_usbhs_platform_info usb0_data = {
273 .platform_callback = {
274 .get_id = usbhs0_get_id,
275 },
276 .driver_param = {
277 .buswait_bwait = 5,
278 }
279 };
280
281 static struct resource usb0_resources[] = {
282 [0] = {
283 .start = 0xfe450000,
284 .end = 0xfe4501ff,
285 .flags = IORESOURCE_MEM,
286 },
287 [1] = {
288 .start = evt2irq(0x840),
289 .end = evt2irq(0x840),
290 .flags = IORESOURCE_IRQ,
291 },
292 };
293
294 static struct platform_device usb0_device = {
295 .name = "renesas_usbhs",
296 .id = 0,
297 .dev = {
298 .platform_data = &usb0_data,
299 },
300 .num_resources = ARRAY_SIZE(usb0_resources),
301 .resource = usb0_resources,
302 };
303
304 static struct platform_device *sh7757lcr_devices[] __initdata = {
305 &heartbeat_device,
306 &sh7757_eth0_device,
307 &sh7757_eth1_device,
308 &sh7757_eth_giga0_device,
309 &sh7757_eth_giga1_device,
310 &sh_mmcif_device,
311 &sdhi_device,
312 &usb0_device,
313 };
314
315 static struct flash_platform_data spi_flash_data = {
316 .name = "m25p80",
317 .type = "m25px64",
318 };
319
320 static struct spi_board_info spi_board_info[] = {
321 {
322 .modalias = "m25p80",
323 .max_speed_hz = 25000000,
324 .bus_num = 0,
325 .chip_select = 1,
326 .platform_data = &spi_flash_data,
327 },
328 };
329
330 static int __init sh7757lcr_devices_setup(void)
331 {
332 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
333 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
334
335 /* RGMII (PTA) */
336 gpio_request(GPIO_FN_ET0_MDC, NULL);
337 gpio_request(GPIO_FN_ET0_MDIO, NULL);
338 gpio_request(GPIO_FN_ET1_MDC, NULL);
339 gpio_request(GPIO_FN_ET1_MDIO, NULL);
340
341 /* ONFI (PTB, PTZ) */
342 gpio_request(GPIO_FN_ON_NRE, NULL);
343 gpio_request(GPIO_FN_ON_NWE, NULL);
344 gpio_request(GPIO_FN_ON_NWP, NULL);
345 gpio_request(GPIO_FN_ON_NCE0, NULL);
346 gpio_request(GPIO_FN_ON_R_B0, NULL);
347 gpio_request(GPIO_FN_ON_ALE, NULL);
348 gpio_request(GPIO_FN_ON_CLE, NULL);
349
350 gpio_request(GPIO_FN_ON_DQ7, NULL);
351 gpio_request(GPIO_FN_ON_DQ6, NULL);
352 gpio_request(GPIO_FN_ON_DQ5, NULL);
353 gpio_request(GPIO_FN_ON_DQ4, NULL);
354 gpio_request(GPIO_FN_ON_DQ3, NULL);
355 gpio_request(GPIO_FN_ON_DQ2, NULL);
356 gpio_request(GPIO_FN_ON_DQ1, NULL);
357 gpio_request(GPIO_FN_ON_DQ0, NULL);
358
359 /* IRQ8 to 0 (PTB, PTC) */
360 gpio_request(GPIO_FN_IRQ8, NULL);
361 gpio_request(GPIO_FN_IRQ7, NULL);
362 gpio_request(GPIO_FN_IRQ6, NULL);
363 gpio_request(GPIO_FN_IRQ5, NULL);
364 gpio_request(GPIO_FN_IRQ4, NULL);
365 gpio_request(GPIO_FN_IRQ3, NULL);
366 gpio_request(GPIO_FN_IRQ2, NULL);
367 gpio_request(GPIO_FN_IRQ1, NULL);
368 gpio_request(GPIO_FN_IRQ0, NULL);
369
370 /* SPI0 (PTD) */
371 gpio_request(GPIO_FN_SP0_MOSI, NULL);
372 gpio_request(GPIO_FN_SP0_MISO, NULL);
373 gpio_request(GPIO_FN_SP0_SCK, NULL);
374 gpio_request(GPIO_FN_SP0_SCK_FB, NULL);
375 gpio_request(GPIO_FN_SP0_SS0, NULL);
376 gpio_request(GPIO_FN_SP0_SS1, NULL);
377 gpio_request(GPIO_FN_SP0_SS2, NULL);
378 gpio_request(GPIO_FN_SP0_SS3, NULL);
379
380 /* RMII 0/1 (PTE, PTF) */
381 gpio_request(GPIO_FN_RMII0_CRS_DV, NULL);
382 gpio_request(GPIO_FN_RMII0_TXD1, NULL);
383 gpio_request(GPIO_FN_RMII0_TXD0, NULL);
384 gpio_request(GPIO_FN_RMII0_TXEN, NULL);
385 gpio_request(GPIO_FN_RMII0_REFCLK, NULL);
386 gpio_request(GPIO_FN_RMII0_RXD1, NULL);
387 gpio_request(GPIO_FN_RMII0_RXD0, NULL);
388 gpio_request(GPIO_FN_RMII0_RX_ER, NULL);
389 gpio_request(GPIO_FN_RMII1_CRS_DV, NULL);
390 gpio_request(GPIO_FN_RMII1_TXD1, NULL);
391 gpio_request(GPIO_FN_RMII1_TXD0, NULL);
392 gpio_request(GPIO_FN_RMII1_TXEN, NULL);
393 gpio_request(GPIO_FN_RMII1_REFCLK, NULL);
394 gpio_request(GPIO_FN_RMII1_RXD1, NULL);
395 gpio_request(GPIO_FN_RMII1_RXD0, NULL);
396 gpio_request(GPIO_FN_RMII1_RX_ER, NULL);
397
398 /* eMMC (PTG) */
399 gpio_request(GPIO_FN_MMCCLK, NULL);
400 gpio_request(GPIO_FN_MMCCMD, NULL);
401 gpio_request(GPIO_FN_MMCDAT7, NULL);
402 gpio_request(GPIO_FN_MMCDAT6, NULL);
403 gpio_request(GPIO_FN_MMCDAT5, NULL);
404 gpio_request(GPIO_FN_MMCDAT4, NULL);
405 gpio_request(GPIO_FN_MMCDAT3, NULL);
406 gpio_request(GPIO_FN_MMCDAT2, NULL);
407 gpio_request(GPIO_FN_MMCDAT1, NULL);
408 gpio_request(GPIO_FN_MMCDAT0, NULL);
409
410 /* LPC (PTG, PTH, PTQ, PTU) */
411 gpio_request(GPIO_FN_SERIRQ, NULL);
412 gpio_request(GPIO_FN_LPCPD, NULL);
413 gpio_request(GPIO_FN_LDRQ, NULL);
414 gpio_request(GPIO_FN_WP, NULL);
415 gpio_request(GPIO_FN_FMS0, NULL);
416 gpio_request(GPIO_FN_LAD3, NULL);
417 gpio_request(GPIO_FN_LAD2, NULL);
418 gpio_request(GPIO_FN_LAD1, NULL);
419 gpio_request(GPIO_FN_LAD0, NULL);
420 gpio_request(GPIO_FN_LFRAME, NULL);
421 gpio_request(GPIO_FN_LRESET, NULL);
422 gpio_request(GPIO_FN_LCLK, NULL);
423 gpio_request(GPIO_FN_LGPIO7, NULL);
424 gpio_request(GPIO_FN_LGPIO6, NULL);
425 gpio_request(GPIO_FN_LGPIO5, NULL);
426 gpio_request(GPIO_FN_LGPIO4, NULL);
427
428 /* SPI1 (PTH) */
429 gpio_request(GPIO_FN_SP1_MOSI, NULL);
430 gpio_request(GPIO_FN_SP1_MISO, NULL);
431 gpio_request(GPIO_FN_SP1_SCK, NULL);
432 gpio_request(GPIO_FN_SP1_SCK_FB, NULL);
433 gpio_request(GPIO_FN_SP1_SS0, NULL);
434 gpio_request(GPIO_FN_SP1_SS1, NULL);
435
436 /* SDHI (PTI) */
437 gpio_request(GPIO_FN_SD_WP, NULL);
438 gpio_request(GPIO_FN_SD_CD, NULL);
439 gpio_request(GPIO_FN_SD_CLK, NULL);
440 gpio_request(GPIO_FN_SD_CMD, NULL);
441 gpio_request(GPIO_FN_SD_D3, NULL);
442 gpio_request(GPIO_FN_SD_D2, NULL);
443 gpio_request(GPIO_FN_SD_D1, NULL);
444 gpio_request(GPIO_FN_SD_D0, NULL);
445
446 /* SCIF3/4 (PTJ, PTW) */
447 gpio_request(GPIO_FN_RTS3, NULL);
448 gpio_request(GPIO_FN_CTS3, NULL);
449 gpio_request(GPIO_FN_TXD3, NULL);
450 gpio_request(GPIO_FN_RXD3, NULL);
451 gpio_request(GPIO_FN_RTS4, NULL);
452 gpio_request(GPIO_FN_RXD4, NULL);
453 gpio_request(GPIO_FN_TXD4, NULL);
454 gpio_request(GPIO_FN_CTS4, NULL);
455
456 /* SERMUX (PTK, PTL, PTO, PTV) */
457 gpio_request(GPIO_FN_COM2_TXD, NULL);
458 gpio_request(GPIO_FN_COM2_RXD, NULL);
459 gpio_request(GPIO_FN_COM2_RTS, NULL);
460 gpio_request(GPIO_FN_COM2_CTS, NULL);
461 gpio_request(GPIO_FN_COM2_DTR, NULL);
462 gpio_request(GPIO_FN_COM2_DSR, NULL);
463 gpio_request(GPIO_FN_COM2_DCD, NULL);
464 gpio_request(GPIO_FN_COM2_RI, NULL);
465 gpio_request(GPIO_FN_RAC_RXD, NULL);
466 gpio_request(GPIO_FN_RAC_RTS, NULL);
467 gpio_request(GPIO_FN_RAC_CTS, NULL);
468 gpio_request(GPIO_FN_RAC_DTR, NULL);
469 gpio_request(GPIO_FN_RAC_DSR, NULL);
470 gpio_request(GPIO_FN_RAC_DCD, NULL);
471 gpio_request(GPIO_FN_RAC_TXD, NULL);
472 gpio_request(GPIO_FN_COM1_TXD, NULL);
473 gpio_request(GPIO_FN_COM1_RXD, NULL);
474 gpio_request(GPIO_FN_COM1_RTS, NULL);
475 gpio_request(GPIO_FN_COM1_CTS, NULL);
476
477 writeb(0x10, 0xfe470000); /* SMR0: SerMux mode 0 */
478
479 /* IIC (PTM, PTR, PTS) */
480 gpio_request(GPIO_FN_SDA7, NULL);
481 gpio_request(GPIO_FN_SCL7, NULL);
482 gpio_request(GPIO_FN_SDA6, NULL);
483 gpio_request(GPIO_FN_SCL6, NULL);
484 gpio_request(GPIO_FN_SDA5, NULL);
485 gpio_request(GPIO_FN_SCL5, NULL);
486 gpio_request(GPIO_FN_SDA4, NULL);
487 gpio_request(GPIO_FN_SCL4, NULL);
488 gpio_request(GPIO_FN_SDA3, NULL);
489 gpio_request(GPIO_FN_SCL3, NULL);
490 gpio_request(GPIO_FN_SDA2, NULL);
491 gpio_request(GPIO_FN_SCL2, NULL);
492 gpio_request(GPIO_FN_SDA1, NULL);
493 gpio_request(GPIO_FN_SCL1, NULL);
494 gpio_request(GPIO_FN_SDA0, NULL);
495 gpio_request(GPIO_FN_SCL0, NULL);
496
497 /* USB (PTN) */
498 gpio_request(GPIO_FN_VBUS_EN, NULL);
499 gpio_request(GPIO_FN_VBUS_OC, NULL);
500
501 /* SGPIO1/0 (PTN, PTO) */
502 gpio_request(GPIO_FN_SGPIO1_CLK, NULL);
503 gpio_request(GPIO_FN_SGPIO1_LOAD, NULL);
504 gpio_request(GPIO_FN_SGPIO1_DI, NULL);
505 gpio_request(GPIO_FN_SGPIO1_DO, NULL);
506 gpio_request(GPIO_FN_SGPIO0_CLK, NULL);
507 gpio_request(GPIO_FN_SGPIO0_LOAD, NULL);
508 gpio_request(GPIO_FN_SGPIO0_DI, NULL);
509 gpio_request(GPIO_FN_SGPIO0_DO, NULL);
510
511 /* WDT (PTN) */
512 gpio_request(GPIO_FN_SUB_CLKIN, NULL);
513
514 /* System (PTT) */
515 gpio_request(GPIO_FN_STATUS1, NULL);
516 gpio_request(GPIO_FN_STATUS0, NULL);
517
518 /* PWMX (PTT) */
519 gpio_request(GPIO_FN_PWMX1, NULL);
520 gpio_request(GPIO_FN_PWMX0, NULL);
521
522 /* R-SPI (PTV) */
523 gpio_request(GPIO_FN_R_SPI_MOSI, NULL);
524 gpio_request(GPIO_FN_R_SPI_MISO, NULL);
525 gpio_request(GPIO_FN_R_SPI_RSPCK, NULL);
526 gpio_request(GPIO_FN_R_SPI_SSL0, NULL);
527 gpio_request(GPIO_FN_R_SPI_SSL1, NULL);
528
529 /* EVC (PTV, PTW) */
530 gpio_request(GPIO_FN_EVENT7, NULL);
531 gpio_request(GPIO_FN_EVENT6, NULL);
532 gpio_request(GPIO_FN_EVENT5, NULL);
533 gpio_request(GPIO_FN_EVENT4, NULL);
534 gpio_request(GPIO_FN_EVENT3, NULL);
535 gpio_request(GPIO_FN_EVENT2, NULL);
536 gpio_request(GPIO_FN_EVENT1, NULL);
537 gpio_request(GPIO_FN_EVENT0, NULL);
538
539 /* LED for heartbeat */
540 gpio_request(GPIO_PTU3, NULL);
541 gpio_direction_output(GPIO_PTU3, 1);
542 gpio_request(GPIO_PTU2, NULL);
543 gpio_direction_output(GPIO_PTU2, 1);
544 gpio_request(GPIO_PTU1, NULL);
545 gpio_direction_output(GPIO_PTU1, 1);
546 gpio_request(GPIO_PTU0, NULL);
547 gpio_direction_output(GPIO_PTU0, 1);
548
549 /* control for MDIO of Gigabit Ethernet */
550 gpio_request(GPIO_PTT4, NULL);
551 gpio_direction_output(GPIO_PTT4, 1);
552
553 /* control for eMMC */
554 gpio_request(GPIO_PTT7, NULL); /* eMMC_RST# */
555 gpio_direction_output(GPIO_PTT7, 0);
556 gpio_request(GPIO_PTT6, NULL); /* eMMC_INDEX# */
557 gpio_direction_output(GPIO_PTT6, 0);
558 gpio_request(GPIO_PTT5, NULL); /* eMMC_PRST# */
559 gpio_direction_output(GPIO_PTT5, 1);
560
561 /* register SPI device information */
562 spi_register_board_info(spi_board_info,
563 ARRAY_SIZE(spi_board_info));
564
565 /* General platform */
566 return platform_add_devices(sh7757lcr_devices,
567 ARRAY_SIZE(sh7757lcr_devices));
568 }
569 arch_initcall(sh7757lcr_devices_setup);
570
571 /* Initialize IRQ setting */
572 static void __init init_sh7757lcr_IRQ(void)
573 {
574 plat_irq_setup_pins(IRQ_MODE_IRQ7654);
575 plat_irq_setup_pins(IRQ_MODE_IRQ3210);
576 }
577
578 /* Initialize the board */
579 static void __init sh7757lcr_setup(char **cmdline_p)
580 {
581 printk(KERN_INFO "Renesas R0P7757LC0012RL support.\n");
582 }
583
584 static int sh7757lcr_mode_pins(void)
585 {
586 int value = 0;
587
588 /* These are the factory default settings of S3 (Low active).
589 * If you change these dip switches then you will need to
590 * adjust the values below as well.
591 */
592 value |= MODE_PIN0; /* Clock Mode: 1 */
593
594 return value;
595 }
596
597 /* The Machine Vector */
598 static struct sh_machine_vector mv_sh7757lcr __initmv = {
599 .mv_name = "SH7757LCR",
600 .mv_setup = sh7757lcr_setup,
601 .mv_init_irq = init_sh7757lcr_IRQ,
602 .mv_mode_pins = sh7757lcr_mode_pins,
603 };
604
605
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