1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas System Solutions Asia Pte. Ltd - Migo-R
4 *
5 * Copyright (C) 2008 Magnus Damm
6 */
7 #include <linux/clkdev.h>
8 #include <linux/dma-map-ops.h>
9 #include <linux/init.h>
10 #include <linux/platform_data/tmio.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/input.h>
14 #include <linux/input/sh_keysc.h>
15 #include <linux/memblock.h>
16 #include <linux/mmc/host.h>
17 #include <linux/mtd/physmap.h>
18 #include <linux/mtd/platnand.h>
19 #include <linux/i2c.h>
20 #include <linux/regulator/fixed.h>
21 #include <linux/regulator/machine.h>
22 #include <linux/smc91x.h>
23 #include <linux/delay.h>
24 #include <linux/clk.h>
25 #include <linux/gpio.h>
26 #include <linux/gpio/machine.h>
27 #include <linux/videodev2.h>
28 #include <linux/sh_intc.h>
29 #include <video/sh_mobile_lcdc.h>
30 #include <media/drv-intf/renesas-ceu.h>
31 #include <media/i2c/ov772x.h>
32 #include <media/i2c/tw9910.h>
33 #include <asm/clock.h>
34 #include <asm/machvec.h>
35 #include <asm/io.h>
36 #include <asm/suspend.h>
37 #include <mach/migor.h>
38 #include <cpu/sh7722.h>
39
40 /* Address IRQ Size Bus Description
41 * 0x00000000 64MB 16 NOR Flash (SP29PL256N)
42 * 0x0c000000 64MB 64 SDRAM (2xK4M563233G)
43 * 0x10000000 IRQ0 16 Ethernet (SMC91C111)
44 * 0x14000000 IRQ4 16 USB 2.0 Host Controller (M66596)
45 * 0x18000000 8GB 8 NAND Flash (K9K8G08U0A)
46 */
47
48 #define CEU_BUFFER_MEMORY_SIZE (4 << 20)
49 static phys_addr_t ceu_dma_membase;
50
51 static struct smc91x_platdata smc91x_info = {
52 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT,
53 };
54
55 static struct resource smc91x_eth_resources[] = {
56 [0] = {
57 .name = "SMC91C111" ,
58 .start = 0x10000300,
59 .end = 0x1000030f,
60 .flags = IORESOURCE_MEM,
61 },
62 [1] = {
63 .start = evt2irq(0x600), /* IRQ0 */
64 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
65 },
66 };
67
68 static struct platform_device smc91x_eth_device = {
69 .name = "smc91x",
70 .num_resources = ARRAY_SIZE(smc91x_eth_resources),
71 .resource = smc91x_eth_resources,
72 .dev = {
73 .platform_data = &smc91x_info,
74 },
75 };
76
77 static struct sh_keysc_info sh_keysc_info = {
78 .mode = SH_KEYSC_MODE_2, /* KEYOUT0->4, KEYIN1->5 */
79 .scan_timing = 3,
80 .delay = 5,
81 .keycodes = {
82 0, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, KEY_ENTER,
83 0, KEY_F, KEY_C, KEY_D, KEY_H, KEY_1,
84 0, KEY_2, KEY_3, KEY_4, KEY_5, KEY_6,
85 0, KEY_7, KEY_8, KEY_9, KEY_S, KEY_0,
86 0, KEY_P, KEY_STOP, KEY_REWIND, KEY_PLAY, KEY_FASTFORWARD,
87 },
88 };
89
90 static struct resource sh_keysc_resources[] = {
91 [0] = {
92 .start = 0x044b0000,
93 .end = 0x044b000f,
94 .flags = IORESOURCE_MEM,
95 },
96 [1] = {
97 .start = evt2irq(0xbe0),
98 .flags = IORESOURCE_IRQ,
99 },
100 };
101
102 static struct platform_device sh_keysc_device = {
103 .name = "sh_keysc",
104 .id = 0, /* "keysc0" clock */
105 .num_resources = ARRAY_SIZE(sh_keysc_resources),
106 .resource = sh_keysc_resources,
107 .dev = {
108 .platform_data = &sh_keysc_info,
109 },
110 };
111
112 static struct mtd_partition migor_nor_flash_partitions[] =
113 {
114 {
115 .name = "uboot",
116 .offset = 0,
117 .size = (1 * 1024 * 1024),
118 .mask_flags = MTD_WRITEABLE, /* Read-only */
119 },
120 {
121 .name = "rootfs",
122 .offset = MTDPART_OFS_APPEND,
123 .size = (15 * 1024 * 1024),
124 },
125 {
126 .name = "other",
127 .offset = MTDPART_OFS_APPEND,
128 .size = MTDPART_SIZ_FULL,
129 },
130 };
131
132 static struct physmap_flash_data migor_nor_flash_data = {
133 .width = 2,
134 .parts = migor_nor_flash_partitions,
135 .nr_parts = ARRAY_SIZE(migor_nor_flash_partitions),
136 };
137
138 static struct resource migor_nor_flash_resources[] = {
139 [0] = {
140 .name = "NOR Flash",
141 .start = 0x00000000,
142 .end = 0x03ffffff,
143 .flags = IORESOURCE_MEM,
144 }
145 };
146
147 static struct platform_device migor_nor_flash_device = {
148 .name = "physmap-flash",
149 .resource = migor_nor_flash_resources,
150 .num_resources = ARRAY_SIZE(migor_nor_flash_resources),
151 .dev = {
152 .platform_data = &migor_nor_flash_data,
153 },
154 };
155
156 static struct mtd_partition migor_nand_flash_partitions[] = {
157 {
158 .name = "nanddata1",
159 .offset = 0x0,
160 .size = 512 * 1024 * 1024,
161 },
162 {
163 .name = "nanddata2",
164 .offset = MTDPART_OFS_APPEND,
165 .size = 512 * 1024 * 1024,
166 },
167 };
168
169 static void migor_nand_flash_cmd_ctl(struct nand_chip *chip, int cmd,
170 unsigned int ctrl)
171 {
172 if (cmd == NAND_CMD_NONE)
173 return;
174
175 if (ctrl & NAND_CLE)
176 writeb(cmd, chip->legacy.IO_ADDR_W + 0x00400000);
177 else if (ctrl & NAND_ALE)
178 writeb(cmd, chip->legacy.IO_ADDR_W + 0x00800000);
179 else
180 writeb(cmd, chip->legacy.IO_ADDR_W);
181 }
182
183 static int migor_nand_flash_ready(struct nand_chip *chip)
184 {
185 return gpio_get_value(GPIO_PTA1); /* NAND_RBn */
186 }
187
188 static struct platform_nand_data migor_nand_flash_data = {
189 .chip = {
190 .nr_chips = 1,
191 .partitions = migor_nand_flash_partitions,
192 .nr_partitions = ARRAY_SIZE(migor_nand_flash_partitions),
193 .chip_delay = 20,
194 },
195 .ctrl = {
196 .dev_ready = migor_nand_flash_ready,
197 .cmd_ctrl = migor_nand_flash_cmd_ctl,
198 },
199 };
200
201 static struct resource migor_nand_flash_resources[] = {
202 [0] = {
203 .name = "NAND Flash",
204 .start = 0x18000000,
205 .end = 0x18ffffff,
206 .flags = IORESOURCE_MEM,
207 },
208 };
209
210 static struct platform_device migor_nand_flash_device = {
211 .name = "gen_nand",
212 .resource = migor_nand_flash_resources,
213 .num_resources = ARRAY_SIZE(migor_nand_flash_resources),
214 .dev = {
215 .platform_data = &migor_nand_flash_data,
216 }
217 };
218
219 static const struct fb_videomode migor_lcd_modes[] = {
220 {
221 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
222 .name = "LB070WV1",
223 .xres = 800,
224 .yres = 480,
225 .left_margin = 64,
226 .right_margin = 16,
227 .hsync_len = 120,
228 .sync = 0,
229 #elif defined(CONFIG_SH_MIGOR_QVGA)
230 .name = "PH240320T",
231 .xres = 320,
232 .yres = 240,
233 .left_margin = 0,
234 .right_margin = 16,
235 .hsync_len = 8,
236 .sync = FB_SYNC_HOR_HIGH_ACT,
237 #endif
238 .upper_margin = 1,
239 .lower_margin = 17,
240 .vsync_len = 2,
241 },
242 };
243
244 static struct sh_mobile_lcdc_info sh_mobile_lcdc_info = {
245 #if defined(CONFIG_SH_MIGOR_RTA_WVGA)
246 .clock_source = LCDC_CLK_BUS,
247 .ch[0] = {
248 .chan = LCDC_CHAN_MAINLCD,
249 .fourcc = V4L2_PIX_FMT_RGB565,
250 .interface_type = RGB16,
251 .clock_divider = 2,
252 .lcd_modes = migor_lcd_modes,
253 .num_modes = ARRAY_SIZE(migor_lcd_modes),
254 .panel_cfg = { /* 7.0 inch */
255 .width = 152,
256 .height = 91,
257 },
258 }
259 #elif defined(CONFIG_SH_MIGOR_QVGA)
260 .clock_source = LCDC_CLK_PERIPHERAL,
261 .ch[0] = {
262 .chan = LCDC_CHAN_MAINLCD,
263 .fourcc = V4L2_PIX_FMT_RGB565,
264 .interface_type = SYS16A,
265 .clock_divider = 10,
266 .lcd_modes = migor_lcd_modes,
267 .num_modes = ARRAY_SIZE(migor_lcd_modes),
268 .panel_cfg = {
269 .width = 49, /* 2.4 inch */
270 .height = 37,
271 .setup_sys = migor_lcd_qvga_setup,
272 },
273 .sys_bus_cfg = {
274 .ldmt2r = 0x06000a09,
275 .ldmt3r = 0x180e3418,
276 /* set 1s delay to encourage fsync() */
277 .deferred_io_msec = 1000,
278 },
279 }
280 #endif
281 };
282
283 static struct resource migor_lcdc_resources[] = {
284 [0] = {
285 .name = "LCDC",
286 .start = 0xfe940000, /* P4-only space */
287 .end = 0xfe942fff,
288 .flags = IORESOURCE_MEM,
289 },
290 [1] = {
291 .start = evt2irq(0x580),
292 .flags = IORESOURCE_IRQ,
293 },
294 };
295
296 static struct platform_device migor_lcdc_device = {
297 .name = "sh_mobile_lcdc_fb",
298 .num_resources = ARRAY_SIZE(migor_lcdc_resources),
299 .resource = migor_lcdc_resources,
300 .dev = {
301 .platform_data = &sh_mobile_lcdc_info,
302 },
303 };
304
305 static struct ceu_platform_data ceu_pdata = {
306 .num_subdevs = 2,
307 .subdevs = {
308 { /* [0] = ov772x */
309 .flags = 0,
310 .bus_width = 8,
311 .bus_shift = 0,
312 .i2c_adapter_id = 0,
313 .i2c_address = 0x21,
314 },
315 { /* [1] = tw9910 */
316 .flags = 0,
317 .bus_width = 8,
318 .bus_shift = 0,
319 .i2c_adapter_id = 0,
320 .i2c_address = 0x45,
321 },
322 },
323 };
324
325 static struct resource migor_ceu_resources[] = {
326 [0] = {
327 .name = "CEU",
328 .start = 0xfe910000,
329 .end = 0xfe91009f,
330 .flags = IORESOURCE_MEM,
331 },
332 [1] = {
333 .start = evt2irq(0x880),
334 .flags = IORESOURCE_IRQ,
335 },
336 };
337
338 static struct platform_device migor_ceu_device = {
339 .name = "renesas-ceu",
340 .id = 0, /* ceu.0 */
341 .num_resources = ARRAY_SIZE(migor_ceu_resources),
342 .resource = migor_ceu_resources,
343 .dev = {
344 .platform_data = &ceu_pdata,
345 },
346 };
347
348 /* Powerdown/reset gpios for CEU image sensors */
349 static struct gpiod_lookup_table ov7725_gpios = {
350 .dev_id = "0-0021",
351 .table = {
352 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT0, "powerdown",
353 GPIO_ACTIVE_HIGH),
354 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "reset", GPIO_ACTIVE_LOW),
355 },
356 };
357
358 static struct gpiod_lookup_table tw9910_gpios = {
359 .dev_id = "0-0045",
360 .table = {
361 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT2, "pdn", GPIO_ACTIVE_LOW),
362 GPIO_LOOKUP("sh7722_pfc", GPIO_PTT3, "rstb", GPIO_ACTIVE_LOW),
363 },
364 };
365
366 /* Fixed 3.3V regulator to be used by SDHI0 */
367 static struct regulator_consumer_supply fixed3v3_power_consumers[] =
368 {
369 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
370 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
371 };
372
373 static struct resource sdhi_cn9_resources[] = {
374 [0] = {
375 .name = "SDHI",
376 .start = 0x04ce0000,
377 .end = 0x04ce00ff,
378 .flags = IORESOURCE_MEM,
379 },
380 [1] = {
381 .start = evt2irq(0xe80),
382 .flags = IORESOURCE_IRQ,
383 },
384 };
385
386 static struct tmio_mmc_data sh7724_sdhi_data = {
387 .chan_priv_tx = (void *)SHDMA_SLAVE_SDHI0_TX,
388 .chan_priv_rx = (void *)SHDMA_SLAVE_SDHI0_RX,
389 .capabilities = MMC_CAP_SDIO_IRQ,
390 };
391
392 static struct platform_device sdhi_cn9_device = {
393 .name = "sh_mobile_sdhi",
394 .num_resources = ARRAY_SIZE(sdhi_cn9_resources),
395 .resource = sdhi_cn9_resources,
396 .dev = {
397 .platform_data = &sh7724_sdhi_data,
398 },
399 };
400
401 static struct ov772x_camera_info ov7725_info = {
402 .flags = 0,
403 };
404
405 static struct tw9910_video_info tw9910_info = {
406 .buswidth = 8,
407 .mpout = TW9910_MPO_FIELD,
408 };
409
410 static struct i2c_board_info migor_i2c_devices[] = {
411 {
412 I2C_BOARD_INFO("rs5c372b", 0x32),
413 },
414 {
415 I2C_BOARD_INFO("migor_ts", 0x51),
416 .irq = evt2irq(0x6c0), /* IRQ6 */
417 },
418 {
419 I2C_BOARD_INFO("wm8978", 0x1a),
420 },
421 {
422 I2C_BOARD_INFO("ov772x", 0x21),
423 .platform_data = &ov7725_info,
424 },
425 {
426 I2C_BOARD_INFO("tw9910", 0x45),
427 .platform_data = &tw9910_info,
428 },
429 };
430
431 static struct platform_device *migor_devices[] __initdata = {
432 &smc91x_eth_device,
433 &sh_keysc_device,
434 &migor_lcdc_device,
435 &migor_nor_flash_device,
436 &migor_nand_flash_device,
437 &sdhi_cn9_device,
438 };
439
440 extern char migor_sdram_enter_start;
441 extern char migor_sdram_enter_end;
442 extern char migor_sdram_leave_start;
443 extern char migor_sdram_leave_end;
444
445 static int __init migor_devices_setup(void)
446 {
447 struct clk *video_clk;
448
449 /* register board specific self-refresh code */
450 sh_mobile_register_self_refresh(SUSP_SH_STANDBY | SUSP_SH_SF,
451 &migor_sdram_enter_start,
452 &migor_sdram_enter_end,
453 &migor_sdram_leave_start,
454 &migor_sdram_leave_end);
455
456 regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
457 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
458
459 /* Let D11 LED show STATUS0 */
460 gpio_request(GPIO_FN_STATUS0, NULL);
461
462 /* Lit D12 LED show PDSTATUS */
463 gpio_request(GPIO_FN_PDSTATUS, NULL);
464
465 /* SMC91C111 - Enable IRQ0, Setup CS4 for 16-bit fast access */
466 gpio_request(GPIO_FN_IRQ0, NULL);
467 __raw_writel(0x00003400, BSC_CS4BCR);
468 __raw_writel(0x00110080, BSC_CS4WCR);
469
470 /* KEYSC */
471 gpio_request(GPIO_FN_KEYOUT0, NULL);
472 gpio_request(GPIO_FN_KEYOUT1, NULL);
473 gpio_request(GPIO_FN_KEYOUT2, NULL);
474 gpio_request(GPIO_FN_KEYOUT3, NULL);
475 gpio_request(GPIO_FN_KEYOUT4_IN6, NULL);
476 gpio_request(GPIO_FN_KEYIN1, NULL);
477 gpio_request(GPIO_FN_KEYIN2, NULL);
478 gpio_request(GPIO_FN_KEYIN3, NULL);
479 gpio_request(GPIO_FN_KEYIN4, NULL);
480 gpio_request(GPIO_FN_KEYOUT5_IN5, NULL);
481
482 /* NAND Flash */
483 gpio_request(GPIO_FN_CS6A_CE2B, NULL);
484 __raw_writel((__raw_readl(BSC_CS6ABCR) & ~0x0600) | 0x0200, BSC_CS6ABCR);
485 gpio_request(GPIO_PTA1, NULL);
486 gpio_direction_input(GPIO_PTA1);
487
488 /* SDHI */
489 gpio_request(GPIO_FN_SDHICD, NULL);
490 gpio_request(GPIO_FN_SDHIWP, NULL);
491 gpio_request(GPIO_FN_SDHID3, NULL);
492 gpio_request(GPIO_FN_SDHID2, NULL);
493 gpio_request(GPIO_FN_SDHID1, NULL);
494 gpio_request(GPIO_FN_SDHID0, NULL);
495 gpio_request(GPIO_FN_SDHICMD, NULL);
496 gpio_request(GPIO_FN_SDHICLK, NULL);
497
498 /* Touch Panel */
499 gpio_request(GPIO_FN_IRQ6, NULL);
500
501 /* LCD Panel */
502 #ifdef CONFIG_SH_MIGOR_QVGA /* LCDC - QVGA - Enable SYS Interface signals */
503 gpio_request(GPIO_FN_LCDD17, NULL);
504 gpio_request(GPIO_FN_LCDD16, NULL);
505 gpio_request(GPIO_FN_LCDD15, NULL);
506 gpio_request(GPIO_FN_LCDD14, NULL);
507 gpio_request(GPIO_FN_LCDD13, NULL);
508 gpio_request(GPIO_FN_LCDD12, NULL);
509 gpio_request(GPIO_FN_LCDD11, NULL);
510 gpio_request(GPIO_FN_LCDD10, NULL);
511 gpio_request(GPIO_FN_LCDD8, NULL);
512 gpio_request(GPIO_FN_LCDD7, NULL);
513 gpio_request(GPIO_FN_LCDD6, NULL);
514 gpio_request(GPIO_FN_LCDD5, NULL);
515 gpio_request(GPIO_FN_LCDD4, NULL);
516 gpio_request(GPIO_FN_LCDD3, NULL);
517 gpio_request(GPIO_FN_LCDD2, NULL);
518 gpio_request(GPIO_FN_LCDD1, NULL);
519 gpio_request(GPIO_FN_LCDRS, NULL);
520 gpio_request(GPIO_FN_LCDCS, NULL);
521 gpio_request(GPIO_FN_LCDRD, NULL);
522 gpio_request(GPIO_FN_LCDWR, NULL);
523 gpio_request(GPIO_PTH2, NULL); /* LCD_DON */
524 gpio_direction_output(GPIO_PTH2, 1);
525 #endif
526 #ifdef CONFIG_SH_MIGOR_RTA_WVGA /* LCDC - WVGA - Enable RGB Interface signals */
527 gpio_request(GPIO_FN_LCDD15, NULL);
528 gpio_request(GPIO_FN_LCDD14, NULL);
529 gpio_request(GPIO_FN_LCDD13, NULL);
530 gpio_request(GPIO_FN_LCDD12, NULL);
531 gpio_request(GPIO_FN_LCDD11, NULL);
532 gpio_request(GPIO_FN_LCDD10, NULL);
533 gpio_request(GPIO_FN_LCDD9, NULL);
534 gpio_request(GPIO_FN_LCDD8, NULL);
535 gpio_request(GPIO_FN_LCDD7, NULL);
536 gpio_request(GPIO_FN_LCDD6, NULL);
537 gpio_request(GPIO_FN_LCDD5, NULL);
538 gpio_request(GPIO_FN_LCDD4, NULL);
539 gpio_request(GPIO_FN_LCDD3, NULL);
540 gpio_request(GPIO_FN_LCDD2, NULL);
541 gpio_request(GPIO_FN_LCDD1, NULL);
542 gpio_request(GPIO_FN_LCDD0, NULL);
543 gpio_request(GPIO_FN_LCDLCLK, NULL);
544 gpio_request(GPIO_FN_LCDDCK, NULL);
545 gpio_request(GPIO_FN_LCDVEPWC, NULL);
546 gpio_request(GPIO_FN_LCDVCPWC, NULL);
547 gpio_request(GPIO_FN_LCDVSYN, NULL);
548 gpio_request(GPIO_FN_LCDHSYN, NULL);
549 gpio_request(GPIO_FN_LCDDISP, NULL);
550 gpio_request(GPIO_FN_LCDDON, NULL);
551 #endif
552
553 /* CEU */
554 gpio_request(GPIO_FN_VIO_CLK2, NULL);
555 gpio_request(GPIO_FN_VIO_VD2, NULL);
556 gpio_request(GPIO_FN_VIO_HD2, NULL);
557 gpio_request(GPIO_FN_VIO_FLD, NULL);
558 gpio_request(GPIO_FN_VIO_CKO, NULL);
559 gpio_request(GPIO_FN_VIO_D15, NULL);
560 gpio_request(GPIO_FN_VIO_D14, NULL);
561 gpio_request(GPIO_FN_VIO_D13, NULL);
562 gpio_request(GPIO_FN_VIO_D12, NULL);
563 gpio_request(GPIO_FN_VIO_D11, NULL);
564 gpio_request(GPIO_FN_VIO_D10, NULL);
565 gpio_request(GPIO_FN_VIO_D9, NULL);
566 gpio_request(GPIO_FN_VIO_D8, NULL);
567
568 __raw_writew(__raw_readw(PORT_MSELCRB) | 0x2000, PORT_MSELCRB); /* D15->D8 */
569
570 /* SIU: Port B */
571 gpio_request(GPIO_FN_SIUBOLR, NULL);
572 gpio_request(GPIO_FN_SIUBOBT, NULL);
573 gpio_request(GPIO_FN_SIUBISLD, NULL);
574 gpio_request(GPIO_FN_SIUBOSLD, NULL);
575 gpio_request(GPIO_FN_SIUMCKB, NULL);
576
577 /*
578 * The original driver sets SIUB OLR/OBT, ILR/IBT, and SIUA OLR/OBT to
579 * output. Need only SIUB, set to output for master mode (table 34.2)
580 */
581 __raw_writew(__raw_readw(PORT_MSELCRA) | 1, PORT_MSELCRA);
582
583 /*
584 * Use 10 MHz VIO_CKO instead of 24 MHz to work around signal quality
585 * issues on Panel Board V2.1.
586 */
587 video_clk = clk_get(NULL, "video_clk");
588 if (!IS_ERR(video_clk)) {
589 clk_set_rate(video_clk, clk_round_rate(video_clk, 10000000));
590 clk_put(video_clk);
591 }
592
593 /* Add a clock alias for ov7725 xclk source. */
594 clk_add_alias(NULL, "0-0021", "video_clk", NULL);
595
596 /* Register GPIOs for video sources. */
597 gpiod_add_lookup_table(&ov7725_gpios);
598 gpiod_add_lookup_table(&tw9910_gpios);
599
600 i2c_register_board_info(0, migor_i2c_devices,
601 ARRAY_SIZE(migor_i2c_devices));
602
603 /* Initialize CEU platform device separately to map memory first */
604 device_initialize(&migor_ceu_device.dev);
605 dma_declare_coherent_memory(&migor_ceu_device.dev,
606 ceu_dma_membase, ceu_dma_membase,
607 CEU_BUFFER_MEMORY_SIZE);
608
609 platform_device_add(&migor_ceu_device);
610
611 return platform_add_devices(migor_devices, ARRAY_SIZE(migor_devices));
612 }
613 arch_initcall(migor_devices_setup);
614
615 /* Return the board specific boot mode pin configuration */
616 static int migor_mode_pins(void)
617 {
618 /* MD0=1, MD1=1, MD2=0: Clock Mode 3
619 * MD3=0: 16-bit Area0 Bus Width
620 * MD5=1: Little Endian
621 * TSTMD=1, MD8=0: Test Mode Disabled
622 */
623 return MODE_PIN0 | MODE_PIN1 | MODE_PIN5;
624 }
625
626 /* Reserve a portion of memory for CEU buffers */
627 static void __init migor_mv_mem_reserve(void)
628 {
629 phys_addr_t phys;
630 phys_addr_t size = CEU_BUFFER_MEMORY_SIZE;
631
632 phys = memblock_phys_alloc(size, PAGE_SIZE);
633 if (!phys)
634 panic("Failed to allocate CEU memory\n");
635
636 memblock_phys_free(phys, size);
637 memblock_remove(phys, size);
638
639 ceu_dma_membase = phys;
640 }
641
642 /*
643 * The Machine Vector
644 */
645 static struct sh_machine_vector mv_migor __initmv = {
646 .mv_name = "Migo-R",
647 .mv_mode_pins = migor_mode_pins,
648 .mv_mem_reserve = migor_mv_mem_reserve,
649 };
650
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