1 /* SPDX-License-Identifier: GPL-2.0
2 *
3 * Copyright (C) 1999 by Kaz Kojima
4 *
5 * Defitions for the address spaces of the SH CPUs.
6 */
7 #ifndef __ASM_SH_ADDRSPACE_H
8 #define __ASM_SH_ADDRSPACE_H
9
10 #include <cpu/addrspace.h>
11
12 /* If this CPU supports segmentation, hook up the helpers */
13 #ifdef P1SEG
14
15 /*
16 [ P0/U0 (virtual) ] 0x00000000 <------ User space
17 [ P1 (fixed) cached ] 0x80000000 <------ Kernel space
18 [ P2 (fixed) non-cachable] 0xA0000000 <------ Physical access
19 [ P3 (virtual) cached] 0xC0000000 <------ vmalloced area
20 [ P4 control ] 0xE0000000
21 */
22
23 /* Returns the privileged segment base of a given address */
24 #define PXSEG(a) (((unsigned long)(a)) & 0xe0000000)
25
26 #ifdef CONFIG_29BIT
27 /*
28 * Map an address to a certain privileged segment
29 */
30 #define P1SEGADDR(a) \
31 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P1SEG))
32 #define P2SEGADDR(a) \
33 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P2SEG))
34 #define P3SEGADDR(a) \
35 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P3SEG))
36 #define P4SEGADDR(a) \
37 ((__typeof__(a))(((unsigned long)(a) & 0x1fffffff) | P4SEG))
38 #else
39 /*
40 * These will never work in 32-bit, don't even bother.
41 */
42 #define P1SEGADDR(a) ({ (void)(a); BUG(); NULL; })
43 #define P2SEGADDR(a) ({ (void)(a); BUG(); NULL; })
44 #define P3SEGADDR(a) ({ (void)(a); BUG(); NULL; })
45 #define P4SEGADDR(a) ({ (void)(a); BUG(); NULL; })
46 #endif
47 #endif /* P1SEG */
48
49 /* Check if an address can be reached in 29 bits */
50 #define IS_29BIT(a) (((unsigned long)(a)) < 0x20000000)
51
52 #ifdef CONFIG_SH_STORE_QUEUES
53 /*
54 * This is a special case for the SH-4 store queues, as pages for this
55 * space still need to be faulted in before it's possible to flush the
56 * store queue cache for writeout to the remapped region.
57 */
58 #define P3_ADDR_MAX (P4SEG_STORE_QUE + 0x04000000)
59 #else
60 #define P3_ADDR_MAX P4SEG
61 #endif
62
63 #endif /* __ASM_SH_ADDRSPACE_H */
64
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