1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * include/asm-sh/cpu-sh3/mmu_context.h 4 * 5 * Copyright (C) 1999 Niibe Yutaka 6 */ 7 #ifndef __ASM_CPU_SH3_MMU_CONTEXT_H 8 #define __ASM_CPU_SH3_MMU_CONTEXT_H 9 10 #define MMU_PTEH 0xFFFFFFF0 /* Page table entry register HIGH */ 11 #define MMU_PTEL 0xFFFFFFF4 /* Page table entry register LOW */ 12 #define MMU_TTB 0xFFFFFFF8 /* Translation table base register */ 13 #define MMU_TEA 0xFFFFFFFC /* TLB Exception Address */ 14 15 #define MMUCR 0xFFFFFFE0 /* MMU Control Register */ 16 #define MMUCR_TI (1 << 2) /* TLB flush bit */ 17 18 #define MMU_TLB_ADDRESS_ARRAY 0xF2000000 19 #define MMU_PAGE_ASSOC_BIT 0x80 20 21 #define MMU_NTLB_ENTRIES 128 /* for 7708 */ 22 #define MMU_NTLB_WAYS 4 23 #define MMU_CONTROL_INIT 0x007 /* SV=0, TF=1, IX=1, AT=1 */ 24 25 #define TRA 0xffffffd0 26 #define EXPEVT 0xffffffd4 27 28 #if defined(CONFIG_CPU_SUBTYPE_SH7705) || \ 29 defined(CONFIG_CPU_SUBTYPE_SH7706) || \ 30 defined(CONFIG_CPU_SUBTYPE_SH7707) || \ 31 defined(CONFIG_CPU_SUBTYPE_SH7709) || \ 32 defined(CONFIG_CPU_SUBTYPE_SH7710) || \ 33 defined(CONFIG_CPU_SUBTYPE_SH7712) || \ 34 defined(CONFIG_CPU_SUBTYPE_SH7720) || \ 35 defined(CONFIG_CPU_SUBTYPE_SH7721) 36 #define INTEVT 0xa4000000 /* INTEVTE2(0xa4000000) */ 37 #else 38 #define INTEVT 0xffffffd8 39 #endif 40 41 #endif /* __ASM_CPU_SH3_MMU_CONTEXT_H */ 42 43
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