1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * include/asm-sh/cpu-sh4/mmu_context.h 4 * 5 * Copyright (C) 1999 Niibe Yutaka 6 */ 7 #ifndef __ASM_CPU_SH4_MMU_CONTEXT_H 8 #define __ASM_CPU_SH4_MMU_CONTEXT_H 9 10 #define MMU_PTEH 0xFF000000 /* Page table entry register HIGH */ 11 #define MMU_PTEL 0xFF000004 /* Page table entry register LOW */ 12 #define MMU_TTB 0xFF000008 /* Translation table base register */ 13 #define MMU_TEA 0xFF00000C /* TLB Exception Address */ 14 #define MMU_PTEA 0xFF000034 /* PTE assistance register */ 15 #define MMU_PTEAEX 0xFF00007C /* PTE ASID extension register */ 16 17 #define MMUCR 0xFF000010 /* MMU Control Register */ 18 19 #define MMU_TLB_ENTRY_SHIFT 8 20 21 #define MMU_ITLB_ADDRESS_ARRAY 0xF2000000 22 #define MMU_ITLB_ADDRESS_ARRAY2 0xF2800000 23 #define MMU_ITLB_DATA_ARRAY 0xF3000000 24 #define MMU_ITLB_DATA_ARRAY2 0xF3800000 25 26 #define MMU_UTLB_ADDRESS_ARRAY 0xF6000000 27 #define MMU_UTLB_ADDRESS_ARRAY2 0xF6800000 28 #define MMU_UTLB_DATA_ARRAY 0xF7000000 29 #define MMU_UTLB_DATA_ARRAY2 0xF7800000 30 #define MMU_PAGE_ASSOC_BIT 0x80 31 32 #ifdef CONFIG_MMU 33 #define MMUCR_AT (1 << 0) 34 #else 35 #define MMUCR_AT (0) 36 #endif 37 38 #define MMUCR_TI (1 << 2) 39 40 #define MMUCR_URB 0x00FC0000 41 #define MMUCR_URB_SHIFT 18 42 #define MMUCR_URB_NENTRIES 64 43 #define MMUCR_URC 0x0000FC00 44 #define MMUCR_URC_SHIFT 10 45 46 #if defined(CONFIG_32BIT) && defined(CONFIG_CPU_SUBTYPE_ST40) 47 #define MMUCR_SE (1 << 4) 48 #else 49 #define MMUCR_SE (0) 50 #endif 51 52 #ifdef CONFIG_CPU_HAS_PTEAEX 53 #define MMUCR_AEX (1 << 6) 54 #else 55 #define MMUCR_AEX (0) 56 #endif 57 58 #ifdef CONFIG_X2TLB 59 #define MMUCR_ME (1 << 7) 60 #else 61 #define MMUCR_ME (0) 62 #endif 63 64 #ifdef CONFIG_SH_STORE_QUEUES 65 #define MMUCR_SQMD (1 << 9) 66 #else 67 #define MMUCR_SQMD (0) 68 #endif 69 70 #define MMU_NTLB_ENTRIES 64 71 #define MMU_CONTROL_INIT (MMUCR_AT | MMUCR_TI | MMUCR_SQMD | \ 72 MMUCR_ME | MMUCR_SE | MMUCR_AEX) 73 74 #define TRA 0xff000020 75 #define EXPEVT 0xff000024 76 #define INTEVT 0xff000028 77 78 #endif /* __ASM_CPU_SH4_MMU_CONTEXT_H */ 79 80
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