1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/sh/kernel/cpu/sh2a/opcode_helper.c
4 *
5 * Helper for the SH-2A 32-bit opcodes.
6 *
7 * Copyright (C) 2007 Paul Mundt
8 */
9 #include <linux/kernel.h>
10
11 #include <asm/processor.h>
12
13 /*
14 * Instructions on SH are generally fixed at 16-bits, however, SH-2A
15 * introduces some 32-bit instructions. Since there are no real
16 * constraints on their use (and they can be mixed and matched), we need
17 * to check the instruction encoding to work out if it's a true 32-bit
18 * instruction or not.
19 *
20 * Presently, 32-bit opcodes have only slight variations in what the
21 * actual encoding looks like in the first-half of the instruction, which
22 * makes it fairly straightforward to differentiate from the 16-bit ones.
23 *
24 * First 16-bits of encoding Used by
25 *
26 * 0011nnnnmmmm0001 mov.b, mov.w, mov.l, fmov.d,
27 * fmov.s, movu.b, movu.w
28 *
29 * 0011nnnn0iii1001 bclr.b, bld.b, bset.b, bst.b, band.b,
30 * bandnot.b, bldnot.b, bor.b, bornot.b,
31 * bxor.b
32 *
33 * 0000nnnniiii0000 movi20
34 * 0000nnnniiii0001 movi20s
35 */
36 unsigned int instruction_size(unsigned int insn)
37 {
38 /* Look for the common cases */
39 switch ((insn & 0xf00f)) {
40 case 0x0000: /* movi20 */
41 case 0x0001: /* movi20s */
42 case 0x3001: /* 32-bit mov/fmov/movu variants */
43 return 4;
44 }
45
46 /* And the special cases.. */
47 switch ((insn & 0xf08f)) {
48 case 0x3009: /* 32-bit b*.b bit operations */
49 return 4;
50 }
51
52 return 2;
53 }
54
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