1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * SH7203 and SH7263 Setup
4 *
5 * Copyright (C) 2007 - 2009 Paul Mundt
6 */
7 #include <linux/platform_device.h>
8 #include <linux/init.h>
9 #include <linux/serial.h>
10 #include <linux/serial_sci.h>
11 #include <linux/sh_timer.h>
12 #include <linux/io.h>
13 #include <asm/platform_early.h>
14
15 enum {
16 UNUSED = 0,
17
18 /* interrupt sources */
19 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
20 PINT0, PINT1, PINT2, PINT3, PINT4, PINT5, PINT6, PINT7,
21 DMAC0, DMAC1, DMAC2, DMAC3, DMAC4, DMAC5, DMAC6, DMAC7,
22 USB, LCDC, CMT0, CMT1, BSC, WDT,
23
24 MTU0_ABCD, MTU0_VEF, MTU1_AB, MTU1_VU, MTU2_AB, MTU2_VU,
25 MTU3_ABCD, MTU4_ABCD, MTU2_TCI3V, MTU2_TCI4V,
26
27 ADC_ADI,
28
29 IIC30, IIC31, IIC32, IIC33,
30 SCIF0, SCIF1, SCIF2, SCIF3,
31
32 SSU0, SSU1,
33
34 SSI0_SSII, SSI1_SSII, SSI2_SSII, SSI3_SSII,
35
36 /* ROM-DEC, SDHI, SRC, and IEB are SH7263 specific */
37 ROMDEC, FLCTL, SDHI, RTC, RCAN0, RCAN1,
38 SRC, IEBI,
39
40 /* interrupt groups */
41 PINT,
42 };
43
44 static struct intc_vect vectors[] __initdata = {
45 INTC_IRQ(IRQ0, 64), INTC_IRQ(IRQ1, 65),
46 INTC_IRQ(IRQ2, 66), INTC_IRQ(IRQ3, 67),
47 INTC_IRQ(IRQ4, 68), INTC_IRQ(IRQ5, 69),
48 INTC_IRQ(IRQ6, 70), INTC_IRQ(IRQ7, 71),
49 INTC_IRQ(PINT0, 80), INTC_IRQ(PINT1, 81),
50 INTC_IRQ(PINT2, 82), INTC_IRQ(PINT3, 83),
51 INTC_IRQ(PINT4, 84), INTC_IRQ(PINT5, 85),
52 INTC_IRQ(PINT6, 86), INTC_IRQ(PINT7, 87),
53 INTC_IRQ(DMAC0, 108), INTC_IRQ(DMAC0, 109),
54 INTC_IRQ(DMAC1, 112), INTC_IRQ(DMAC1, 113),
55 INTC_IRQ(DMAC2, 116), INTC_IRQ(DMAC2, 117),
56 INTC_IRQ(DMAC3, 120), INTC_IRQ(DMAC3, 121),
57 INTC_IRQ(DMAC4, 124), INTC_IRQ(DMAC4, 125),
58 INTC_IRQ(DMAC5, 128), INTC_IRQ(DMAC5, 129),
59 INTC_IRQ(DMAC6, 132), INTC_IRQ(DMAC6, 133),
60 INTC_IRQ(DMAC7, 136), INTC_IRQ(DMAC7, 137),
61 INTC_IRQ(USB, 140), INTC_IRQ(LCDC, 141),
62 INTC_IRQ(CMT0, 142), INTC_IRQ(CMT1, 143),
63 INTC_IRQ(BSC, 144), INTC_IRQ(WDT, 145),
64 INTC_IRQ(MTU0_ABCD, 146), INTC_IRQ(MTU0_ABCD, 147),
65 INTC_IRQ(MTU0_ABCD, 148), INTC_IRQ(MTU0_ABCD, 149),
66 INTC_IRQ(MTU0_VEF, 150),
67 INTC_IRQ(MTU0_VEF, 151), INTC_IRQ(MTU0_VEF, 152),
68 INTC_IRQ(MTU1_AB, 153), INTC_IRQ(MTU1_AB, 154),
69 INTC_IRQ(MTU1_VU, 155), INTC_IRQ(MTU1_VU, 156),
70 INTC_IRQ(MTU2_AB, 157), INTC_IRQ(MTU2_AB, 158),
71 INTC_IRQ(MTU2_VU, 159), INTC_IRQ(MTU2_VU, 160),
72 INTC_IRQ(MTU3_ABCD, 161), INTC_IRQ(MTU3_ABCD, 162),
73 INTC_IRQ(MTU3_ABCD, 163), INTC_IRQ(MTU3_ABCD, 164),
74 INTC_IRQ(MTU2_TCI3V, 165),
75 INTC_IRQ(MTU4_ABCD, 166), INTC_IRQ(MTU4_ABCD, 167),
76 INTC_IRQ(MTU4_ABCD, 168), INTC_IRQ(MTU4_ABCD, 169),
77 INTC_IRQ(MTU2_TCI4V, 170),
78 INTC_IRQ(ADC_ADI, 171),
79 INTC_IRQ(IIC30, 172), INTC_IRQ(IIC30, 173),
80 INTC_IRQ(IIC30, 174), INTC_IRQ(IIC30, 175),
81 INTC_IRQ(IIC30, 176),
82 INTC_IRQ(IIC31, 177), INTC_IRQ(IIC31, 178),
83 INTC_IRQ(IIC31, 179), INTC_IRQ(IIC31, 180),
84 INTC_IRQ(IIC31, 181),
85 INTC_IRQ(IIC32, 182), INTC_IRQ(IIC32, 183),
86 INTC_IRQ(IIC32, 184), INTC_IRQ(IIC32, 185),
87 INTC_IRQ(IIC32, 186),
88 INTC_IRQ(IIC33, 187), INTC_IRQ(IIC33, 188),
89 INTC_IRQ(IIC33, 189), INTC_IRQ(IIC33, 190),
90 INTC_IRQ(IIC33, 191),
91 INTC_IRQ(SCIF0, 192), INTC_IRQ(SCIF0, 193),
92 INTC_IRQ(SCIF0, 194), INTC_IRQ(SCIF0, 195),
93 INTC_IRQ(SCIF1, 196), INTC_IRQ(SCIF1, 197),
94 INTC_IRQ(SCIF1, 198), INTC_IRQ(SCIF1, 199),
95 INTC_IRQ(SCIF2, 200), INTC_IRQ(SCIF2, 201),
96 INTC_IRQ(SCIF2, 202), INTC_IRQ(SCIF2, 203),
97 INTC_IRQ(SCIF3, 204), INTC_IRQ(SCIF3, 205),
98 INTC_IRQ(SCIF3, 206), INTC_IRQ(SCIF3, 207),
99 INTC_IRQ(SSU0, 208), INTC_IRQ(SSU0, 209),
100 INTC_IRQ(SSU0, 210),
101 INTC_IRQ(SSU1, 211), INTC_IRQ(SSU1, 212),
102 INTC_IRQ(SSU1, 213),
103 INTC_IRQ(SSI0_SSII, 214), INTC_IRQ(SSI1_SSII, 215),
104 INTC_IRQ(SSI2_SSII, 216), INTC_IRQ(SSI3_SSII, 217),
105 INTC_IRQ(FLCTL, 224), INTC_IRQ(FLCTL, 225),
106 INTC_IRQ(FLCTL, 226), INTC_IRQ(FLCTL, 227),
107 INTC_IRQ(RTC, 231), INTC_IRQ(RTC, 232),
108 INTC_IRQ(RTC, 233),
109 INTC_IRQ(RCAN0, 234), INTC_IRQ(RCAN0, 235),
110 INTC_IRQ(RCAN0, 236), INTC_IRQ(RCAN0, 237),
111 INTC_IRQ(RCAN0, 238),
112 INTC_IRQ(RCAN1, 239), INTC_IRQ(RCAN1, 240),
113 INTC_IRQ(RCAN1, 241), INTC_IRQ(RCAN1, 242),
114 INTC_IRQ(RCAN1, 243),
115
116 /* SH7263-specific trash */
117 #ifdef CONFIG_CPU_SUBTYPE_SH7263
118 INTC_IRQ(ROMDEC, 218), INTC_IRQ(ROMDEC, 219),
119 INTC_IRQ(ROMDEC, 220), INTC_IRQ(ROMDEC, 221),
120 INTC_IRQ(ROMDEC, 222), INTC_IRQ(ROMDEC, 223),
121
122 INTC_IRQ(SDHI, 228), INTC_IRQ(SDHI, 229),
123 INTC_IRQ(SDHI, 230),
124
125 INTC_IRQ(SRC, 244), INTC_IRQ(SRC, 245),
126 INTC_IRQ(SRC, 246),
127
128 INTC_IRQ(IEBI, 247),
129 #endif
130 };
131
132 static struct intc_group groups[] __initdata = {
133 INTC_GROUP(PINT, PINT0, PINT1, PINT2, PINT3,
134 PINT4, PINT5, PINT6, PINT7),
135 };
136
137 static struct intc_prio_reg prio_registers[] __initdata = {
138 { 0xfffe0818, 0, 16, 4, /* IPR01 */ { IRQ0, IRQ1, IRQ2, IRQ3 } },
139 { 0xfffe081a, 0, 16, 4, /* IPR02 */ { IRQ4, IRQ5, IRQ6, IRQ7 } },
140 { 0xfffe0820, 0, 16, 4, /* IPR05 */ { PINT, 0, 0, 0 } },
141 { 0xfffe0c00, 0, 16, 4, /* IPR06 */ { DMAC0, DMAC1, DMAC2, DMAC3 } },
142 { 0xfffe0c02, 0, 16, 4, /* IPR07 */ { DMAC4, DMAC5, DMAC6, DMAC7 } },
143 { 0xfffe0c04, 0, 16, 4, /* IPR08 */ { USB, LCDC, CMT0, CMT1 } },
144 { 0xfffe0c06, 0, 16, 4, /* IPR09 */ { BSC, WDT, MTU0_ABCD, MTU0_VEF } },
145 { 0xfffe0c08, 0, 16, 4, /* IPR10 */ { MTU1_AB, MTU1_VU, MTU2_AB,
146 MTU2_VU } },
147 { 0xfffe0c0a, 0, 16, 4, /* IPR11 */ { MTU3_ABCD, MTU2_TCI3V, MTU4_ABCD,
148 MTU2_TCI4V } },
149 { 0xfffe0c0c, 0, 16, 4, /* IPR12 */ { ADC_ADI, IIC30, IIC31, IIC32 } },
150 { 0xfffe0c0e, 0, 16, 4, /* IPR13 */ { IIC33, SCIF0, SCIF1, SCIF2 } },
151 { 0xfffe0c10, 0, 16, 4, /* IPR14 */ { SCIF3, SSU0, SSU1, SSI0_SSII } },
152 #ifdef CONFIG_CPU_SUBTYPE_SH7203
153 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
154 SSI3_SSII, 0 } },
155 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, 0, RTC, RCAN0 } },
156 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, 0, 0, 0 } },
157 #else
158 { 0xfffe0c12, 0, 16, 4, /* IPR15 */ { SSI1_SSII, SSI2_SSII,
159 SSI3_SSII, ROMDEC } },
160 { 0xfffe0c14, 0, 16, 4, /* IPR16 */ { FLCTL, SDHI, RTC, RCAN0 } },
161 { 0xfffe0c16, 0, 16, 4, /* IPR17 */ { RCAN1, SRC, IEBI, 0 } },
162 #endif
163 };
164
165 static struct intc_mask_reg mask_registers[] __initdata = {
166 { 0xfffe0808, 0, 16, /* PINTER */
167 { 0, 0, 0, 0, 0, 0, 0, 0,
168 PINT7, PINT6, PINT5, PINT4, PINT3, PINT2, PINT1, PINT0 } },
169 };
170
171 static DECLARE_INTC_DESC(intc_desc, "sh7203", vectors, groups,
172 mask_registers, prio_registers, NULL);
173
174 static struct plat_sci_port scif0_platform_data = {
175 .scscr = SCSCR_REIE,
176 .type = PORT_SCIF,
177 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
178 };
179
180 static struct resource scif0_resources[] = {
181 DEFINE_RES_MEM(0xfffe8000, 0x100),
182 DEFINE_RES_IRQ(192),
183 };
184
185 static struct platform_device scif0_device = {
186 .name = "sh-sci",
187 .id = 0,
188 .resource = scif0_resources,
189 .num_resources = ARRAY_SIZE(scif0_resources),
190 .dev = {
191 .platform_data = &scif0_platform_data,
192 },
193 };
194
195 static struct plat_sci_port scif1_platform_data = {
196 .scscr = SCSCR_REIE,
197 .type = PORT_SCIF,
198 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
199 };
200
201 static struct resource scif1_resources[] = {
202 DEFINE_RES_MEM(0xfffe8800, 0x100),
203 DEFINE_RES_IRQ(196),
204 };
205
206 static struct platform_device scif1_device = {
207 .name = "sh-sci",
208 .id = 1,
209 .resource = scif1_resources,
210 .num_resources = ARRAY_SIZE(scif1_resources),
211 .dev = {
212 .platform_data = &scif1_platform_data,
213 },
214 };
215
216 static struct plat_sci_port scif2_platform_data = {
217 .scscr = SCSCR_REIE,
218 .type = PORT_SCIF,
219 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
220 };
221
222 static struct resource scif2_resources[] = {
223 DEFINE_RES_MEM(0xfffe9000, 0x100),
224 DEFINE_RES_IRQ(200),
225 };
226
227 static struct platform_device scif2_device = {
228 .name = "sh-sci",
229 .id = 2,
230 .resource = scif2_resources,
231 .num_resources = ARRAY_SIZE(scif2_resources),
232 .dev = {
233 .platform_data = &scif2_platform_data,
234 },
235 };
236
237 static struct plat_sci_port scif3_platform_data = {
238 .scscr = SCSCR_REIE,
239 .type = PORT_SCIF,
240 .regtype = SCIx_SH2_SCIF_FIFODATA_REGTYPE,
241 };
242
243 static struct resource scif3_resources[] = {
244 DEFINE_RES_MEM(0xfffe9800, 0x100),
245 DEFINE_RES_IRQ(204),
246 };
247
248 static struct platform_device scif3_device = {
249 .name = "sh-sci",
250 .id = 3,
251 .resource = scif3_resources,
252 .num_resources = ARRAY_SIZE(scif3_resources),
253 .dev = {
254 .platform_data = &scif3_platform_data,
255 },
256 };
257
258 static struct sh_timer_config cmt_platform_data = {
259 .channels_mask = 3,
260 };
261
262 static struct resource cmt_resources[] = {
263 DEFINE_RES_MEM(0xfffec000, 0x10),
264 DEFINE_RES_IRQ(142),
265 DEFINE_RES_IRQ(143),
266 };
267
268 static struct platform_device cmt_device = {
269 .name = "sh-cmt-16",
270 .id = 0,
271 .dev = {
272 .platform_data = &cmt_platform_data,
273 },
274 .resource = cmt_resources,
275 .num_resources = ARRAY_SIZE(cmt_resources),
276 };
277
278 static struct resource mtu2_resources[] = {
279 DEFINE_RES_MEM(0xfffe4000, 0x400),
280 DEFINE_RES_IRQ_NAMED(146, "tgi0a"),
281 DEFINE_RES_IRQ_NAMED(153, "tgi1a"),
282 };
283
284 static struct platform_device mtu2_device = {
285 .name = "sh-mtu2",
286 .id = -1,
287 .resource = mtu2_resources,
288 .num_resources = ARRAY_SIZE(mtu2_resources),
289 };
290
291 static struct resource rtc_resources[] = {
292 [0] = {
293 .start = 0xffff2000,
294 .end = 0xffff2000 + 0x58 - 1,
295 .flags = IORESOURCE_IO,
296 },
297 [1] = {
298 /* Shared Period/Carry/Alarm IRQ */
299 .start = 231,
300 .flags = IORESOURCE_IRQ,
301 },
302 };
303
304 static struct platform_device rtc_device = {
305 .name = "sh-rtc",
306 .id = -1,
307 .num_resources = ARRAY_SIZE(rtc_resources),
308 .resource = rtc_resources,
309 };
310
311 static struct platform_device *sh7203_devices[] __initdata = {
312 &scif0_device,
313 &scif1_device,
314 &scif2_device,
315 &scif3_device,
316 &cmt_device,
317 &mtu2_device,
318 &rtc_device,
319 };
320
321 static int __init sh7203_devices_setup(void)
322 {
323 return platform_add_devices(sh7203_devices,
324 ARRAY_SIZE(sh7203_devices));
325 }
326 arch_initcall(sh7203_devices_setup);
327
328 void __init plat_irq_setup(void)
329 {
330 register_intc_controller(&intc_desc);
331 }
332
333 static struct platform_device *sh7203_early_devices[] __initdata = {
334 &scif0_device,
335 &scif1_device,
336 &scif2_device,
337 &scif3_device,
338 &cmt_device,
339 &mtu2_device,
340 };
341
342 #define STBCR3 0xfffe0408
343 #define STBCR4 0xfffe040c
344
345 void __init plat_early_device_setup(void)
346 {
347 /* enable CMT clock */
348 __raw_writeb(__raw_readb(STBCR4) & ~0x04, STBCR4);
349
350 /* enable MTU2 clock */
351 __raw_writeb(__raw_readb(STBCR3) & ~0x20, STBCR3);
352
353 sh_early_platform_add_devices(sh7203_early_devices,
354 ARRAY_SIZE(sh7203_early_devices));
355 }
356
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