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Linux/arch/sh/kernel/cpu/sh3/setup-sh3.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * Shared SH3 Setup code
  4  *
  5  *  Copyright (C) 2008  Magnus Damm
  6  */
  7 
  8 #include <linux/init.h>
  9 #include <linux/irq.h>
 10 #include <linux/io.h>
 11 #include <asm/platform_early.h>
 12 
 13 /* All SH3 devices are equipped with IRQ0->5 (except sh7708) */
 14 
 15 enum {
 16         UNUSED = 0,
 17 
 18         /* interrupt sources */
 19         IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5,
 20 };
 21 
 22 static struct intc_vect vectors_irq0123[] __initdata = {
 23         INTC_VECT(IRQ0, 0x600), INTC_VECT(IRQ1, 0x620),
 24         INTC_VECT(IRQ2, 0x640), INTC_VECT(IRQ3, 0x660),
 25 };
 26 
 27 static struct intc_vect vectors_irq45[] __initdata = {
 28         INTC_VECT(IRQ4, 0x680), INTC_VECT(IRQ5, 0x6a0),
 29 };
 30 
 31 static struct intc_prio_reg prio_registers[] __initdata = {
 32         { 0xa4000016, 0, 16, 4, /* IPRC */ { IRQ3, IRQ2, IRQ1, IRQ0 } },
 33         { 0xa4000018, 0, 16, 4, /* IPRD */ { 0, 0, IRQ5, IRQ4 } },
 34 };
 35 
 36 static struct intc_mask_reg ack_registers[] __initdata = {
 37         { 0xa4000004, 0, 8, /* IRR0 */
 38           { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
 39 };
 40 
 41 static struct intc_sense_reg sense_registers[] __initdata = {
 42         { 0xa4000010, 16, 2, { 0, 0, IRQ5, IRQ4, IRQ3, IRQ2, IRQ1, IRQ0 } },
 43 };
 44 
 45 static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh3-irq0123",
 46                              vectors_irq0123, NULL, NULL,
 47                              prio_registers, sense_registers, ack_registers);
 48 
 49 static DECLARE_INTC_DESC_ACK(intc_desc_irq45, "sh3-irq45",
 50                              vectors_irq45, NULL, NULL,
 51                              prio_registers, sense_registers, ack_registers);
 52 
 53 #define INTC_ICR1               0xa4000010UL
 54 #define INTC_ICR1_IRQLVL        (1<<14)
 55 
 56 void __init plat_irq_setup_pins(int mode)
 57 {
 58         if (mode == IRQ_MODE_IRQ) {
 59                 __raw_writew(__raw_readw(INTC_ICR1) & ~INTC_ICR1_IRQLVL, INTC_ICR1);
 60                 register_intc_controller(&intc_desc_irq0123);
 61                 return;
 62         }
 63         BUG();
 64 }
 65 
 66 void __init plat_irq_setup_sh3(void)
 67 {
 68         register_intc_controller(&intc_desc_irq45);
 69 }
 70 

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