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Linux/arch/sh/kernel/cpu/sh4a/clock-sh7763.c

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  1 // SPDX-License-Identifier: GPL-2.0
  2 /*
  3  * arch/sh/kernel/cpu/sh4a/clock-sh7763.c
  4  *
  5  * SH7763 support for the clock framework
  6  *
  7  *  Copyright (C) 2005  Paul Mundt
  8  *  Copyright (C) 2007  Yoshihiro Shimoda
  9  */
 10 #include <linux/init.h>
 11 #include <linux/kernel.h>
 12 #include <linux/io.h>
 13 #include <linux/clkdev.h>
 14 #include <asm/clock.h>
 15 #include <asm/freq.h>
 16 #include <asm/io.h>
 17 
 18 static int bfc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
 19 static int p0fc_divisors[] = { 1, 1, 1, 8, 1, 1, 1, 1 };
 20 static int cfc_divisors[] = { 1, 1, 4, 1, 1, 1, 1, 1 };
 21 
 22 static void master_clk_init(struct clk *clk)
 23 {
 24         clk->rate *= p0fc_divisors[(__raw_readl(FRQCR) >> 4) & 0x07];
 25 }
 26 
 27 static struct sh_clk_ops sh7763_master_clk_ops = {
 28         .init           = master_clk_init,
 29 };
 30 
 31 static unsigned long module_clk_recalc(struct clk *clk)
 32 {
 33         int idx = ((__raw_readl(FRQCR) >> 4) & 0x07);
 34         return clk->parent->rate / p0fc_divisors[idx];
 35 }
 36 
 37 static struct sh_clk_ops sh7763_module_clk_ops = {
 38         .recalc         = module_clk_recalc,
 39 };
 40 
 41 static unsigned long bus_clk_recalc(struct clk *clk)
 42 {
 43         int idx = ((__raw_readl(FRQCR) >> 16) & 0x07);
 44         return clk->parent->rate / bfc_divisors[idx];
 45 }
 46 
 47 static struct sh_clk_ops sh7763_bus_clk_ops = {
 48         .recalc         = bus_clk_recalc,
 49 };
 50 
 51 static struct sh_clk_ops sh7763_cpu_clk_ops = {
 52         .recalc         = followparent_recalc,
 53 };
 54 
 55 static struct sh_clk_ops *sh7763_clk_ops[] = {
 56         &sh7763_master_clk_ops,
 57         &sh7763_module_clk_ops,
 58         &sh7763_bus_clk_ops,
 59         &sh7763_cpu_clk_ops,
 60 };
 61 
 62 void __init arch_init_clk_ops(struct sh_clk_ops **ops, int idx)
 63 {
 64         if (idx < ARRAY_SIZE(sh7763_clk_ops))
 65                 *ops = sh7763_clk_ops[idx];
 66 }
 67 
 68 static unsigned long shyway_clk_recalc(struct clk *clk)
 69 {
 70         int idx = ((__raw_readl(FRQCR) >> 20) & 0x07);
 71         return clk->parent->rate / cfc_divisors[idx];
 72 }
 73 
 74 static struct sh_clk_ops sh7763_shyway_clk_ops = {
 75         .recalc         = shyway_clk_recalc,
 76 };
 77 
 78 static struct clk sh7763_shyway_clk = {
 79         .flags          = CLK_ENABLE_ON_INIT,
 80         .ops            = &sh7763_shyway_clk_ops,
 81 };
 82 
 83 /*
 84  * Additional SH7763-specific on-chip clocks that aren't already part of the
 85  * clock framework
 86  */
 87 static struct clk *sh7763_onchip_clocks[] = {
 88         &sh7763_shyway_clk,
 89 };
 90 
 91 static struct clk_lookup lookups[] = {
 92         /* main clocks */
 93         CLKDEV_CON_ID("shyway_clk", &sh7763_shyway_clk),
 94 };
 95 
 96 int __init arch_clk_init(void)
 97 {
 98         struct clk *clk;
 99         int i, ret = 0;
100 
101         cpg_clk_init();
102 
103         clk = clk_get(NULL, "master_clk");
104         for (i = 0; i < ARRAY_SIZE(sh7763_onchip_clocks); i++) {
105                 struct clk *clkp = sh7763_onchip_clocks[i];
106 
107                 clkp->parent = clk;
108                 ret |= clk_register(clkp);
109         }
110 
111         clk_put(clk);
112 
113         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
114 
115         return ret;
116 }
117 

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