1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * tsunami.h: Module specific definitions for Tsunami V8 Sparcs
4 *
5 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
6 */
7
8 #ifndef _SPARC_TSUNAMI_H
9 #define _SPARC_TSUNAMI_H
10
11 #include <asm/asi.h>
12
13 /* The MMU control register on the Tsunami:
14 *
15 * -----------------------------------------------------------------------
16 * | implvers |SW|AV|DV|MV| RSV |PC|ITD|ALC| RSV |PE| RC |IE|DE|RSV|NF|ME|
17 * -----------------------------------------------------------------------
18 * 31 24 23 22 21 20 19-18 17 16 14 13-12 11 10-9 8 7 6-2 1 0
19 *
20 * SW: Enable Software Table Walks 0=off 1=on
21 * AV: Address View bit
22 * DV: Data View bit
23 * MV: Memory View bit
24 * PC: Parity Control
25 * ITD: ITBR disable
26 * ALC: Alternate Cacheable
27 * PE: Parity Enable 0=off 1=on
28 * RC: Refresh Control
29 * IE: Instruction cache Enable 0=off 1=on
30 * DE: Data cache Enable 0=off 1=on
31 * NF: No Fault, same as all other SRMMUs
32 * ME: MMU Enable, same as all other SRMMUs
33 */
34
35 #define TSUNAMI_SW 0x00800000
36 #define TSUNAMI_AV 0x00400000
37 #define TSUNAMI_DV 0x00200000
38 #define TSUNAMI_MV 0x00100000
39 #define TSUNAMI_PC 0x00020000
40 #define TSUNAMI_ITD 0x00010000
41 #define TSUNAMI_ALC 0x00008000
42 #define TSUNAMI_PE 0x00001000
43 #define TSUNAMI_RCMASK 0x00000C00
44 #define TSUNAMI_IENAB 0x00000200
45 #define TSUNAMI_DENAB 0x00000100
46 #define TSUNAMI_NF 0x00000002
47 #define TSUNAMI_ME 0x00000001
48
49 static inline void tsunami_flush_icache(void)
50 {
51 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
52 : /* no outputs */
53 : "i" (ASI_M_IC_FLCLEAR)
54 : "memory");
55 }
56
57 static inline void tsunami_flush_dcache(void)
58 {
59 __asm__ __volatile__("sta %%g0, [%%g0] %0\n\t"
60 : /* no outputs */
61 : "i" (ASI_M_DC_FLCLEAR)
62 : "memory");
63 }
64
65 #endif /* !(_SPARC_TSUNAMI_H) */
66
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