1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2 /*----------------------------------------
3 PERFORMANCE INSTRUMENTATION
4 Guillaume Thouvenin 08/10/98
5 David S. Miller 10/06/98
6 ---------------------------------------*/
7 #ifndef PERF_COUNTER_API
8 #define PERF_COUNTER_API
9
10 /* sys_perfctr() interface. First arg is operation code
11 * from enumeration below. The meaning of further arguments
12 * are determined by the operation code.
13 *
14 * NOTE: This system call is no longer provided, use the perf_events
15 * infrastructure.
16 *
17 * Pointers which are passed by the user are pointers to 64-bit
18 * integers.
19 *
20 * Once enabled, performance counter state is retained until the
21 * process either exits or performs an exec. That is, performance
22 * counters remain enabled for fork/clone children.
23 */
24 enum perfctr_opcode {
25 /* Enable UltraSparc performance counters, ARG0 is pointer
26 * to 64-bit accumulator for D0 counter in PIC, ARG1 is pointer
27 * to 64-bit accumulator for D1 counter. ARG2 is a pointer to
28 * the initial PCR register value to use.
29 */
30 PERFCTR_ON,
31
32 /* Disable UltraSparc performance counters. The PCR is written
33 * with zero and the user counter accumulator pointers and
34 * working PCR register value are forgotten.
35 */
36 PERFCTR_OFF,
37
38 /* Add current D0 and D1 PIC values into user pointers given
39 * in PERFCTR_ON operation. The PIC is cleared before returning.
40 */
41 PERFCTR_READ,
42
43 /* Clear the PIC register. */
44 PERFCTR_CLRPIC,
45
46 /* Begin using a new PCR value, the pointer to which is passed
47 * in ARG0. The PIC is also cleared after the new PCR value is
48 * written.
49 */
50 PERFCTR_SETPCR,
51
52 /* Store in pointer given in ARG0 the current PCR register value
53 * being used.
54 */
55 PERFCTR_GETPCR
56 };
57
58 #define PRIV 0x00000001
59 #define SYS 0x00000002
60 #define USR 0x00000004
61
62 /* Pic.S0 Selection Bit Field Encoding, Ultra-I/II */
63 #define CYCLE_CNT 0x00000000
64 #define INSTR_CNT 0x00000010
65 #define DISPATCH0_IC_MISS 0x00000020
66 #define DISPATCH0_STOREBUF 0x00000030
67 #define IC_REF 0x00000080
68 #define DC_RD 0x00000090
69 #define DC_WR 0x000000A0
70 #define LOAD_USE 0x000000B0
71 #define EC_REF 0x000000C0
72 #define EC_WRITE_HIT_RDO 0x000000D0
73 #define EC_SNOOP_INV 0x000000E0
74 #define EC_RD_HIT 0x000000F0
75
76 /* Pic.S0 Selection Bit Field Encoding, Ultra-III */
77 #define US3_CYCLE_CNT 0x00000000
78 #define US3_INSTR_CNT 0x00000010
79 #define US3_DISPATCH0_IC_MISS 0x00000020
80 #define US3_DISPATCH0_BR_TGT 0x00000030
81 #define US3_DISPATCH0_2ND_BR 0x00000040
82 #define US3_RSTALL_STOREQ 0x00000050
83 #define US3_RSTALL_IU_USE 0x00000060
84 #define US3_IC_REF 0x00000080
85 #define US3_DC_RD 0x00000090
86 #define US3_DC_WR 0x000000a0
87 #define US3_EC_REF 0x000000c0
88 #define US3_EC_WR_HIT_RTO 0x000000d0
89 #define US3_EC_SNOOP_INV 0x000000e0
90 #define US3_EC_RD_MISS 0x000000f0
91 #define US3_PC_PORT0_RD 0x00000100
92 #define US3_SI_SNOOP 0x00000110
93 #define US3_SI_CIQ_FLOW 0x00000120
94 #define US3_SI_OWNED 0x00000130
95 #define US3_SW_COUNT_0 0x00000140
96 #define US3_IU_BR_MISS_TAKEN 0x00000150
97 #define US3_IU_BR_COUNT_TAKEN 0x00000160
98 #define US3_DISP_RS_MISPRED 0x00000170
99 #define US3_FA_PIPE_COMPL 0x00000180
100 #define US3_MC_READS_0 0x00000200
101 #define US3_MC_READS_1 0x00000210
102 #define US3_MC_READS_2 0x00000220
103 #define US3_MC_READS_3 0x00000230
104 #define US3_MC_STALLS_0 0x00000240
105 #define US3_MC_STALLS_2 0x00000250
106
107 /* Pic.S1 Selection Bit Field Encoding, Ultra-I/II */
108 #define CYCLE_CNT_D1 0x00000000
109 #define INSTR_CNT_D1 0x00000800
110 #define DISPATCH0_IC_MISPRED 0x00001000
111 #define DISPATCH0_FP_USE 0x00001800
112 #define IC_HIT 0x00004000
113 #define DC_RD_HIT 0x00004800
114 #define DC_WR_HIT 0x00005000
115 #define LOAD_USE_RAW 0x00005800
116 #define EC_HIT 0x00006000
117 #define EC_WB 0x00006800
118 #define EC_SNOOP_CB 0x00007000
119 #define EC_IT_HIT 0x00007800
120
121 /* Pic.S1 Selection Bit Field Encoding, Ultra-III */
122 #define US3_CYCLE_CNT_D1 0x00000000
123 #define US3_INSTR_CNT_D1 0x00000800
124 #define US3_DISPATCH0_MISPRED 0x00001000
125 #define US3_IC_MISS_CANCELLED 0x00001800
126 #define US3_RE_ENDIAN_MISS 0x00002000
127 #define US3_RE_FPU_BYPASS 0x00002800
128 #define US3_RE_DC_MISS 0x00003000
129 #define US3_RE_EC_MISS 0x00003800
130 #define US3_IC_MISS 0x00004000
131 #define US3_DC_RD_MISS 0x00004800
132 #define US3_DC_WR_MISS 0x00005000
133 #define US3_RSTALL_FP_USE 0x00005800
134 #define US3_EC_MISSES 0x00006000
135 #define US3_EC_WB 0x00006800
136 #define US3_EC_SNOOP_CB 0x00007000
137 #define US3_EC_IC_MISS 0x00007800
138 #define US3_RE_PC_MISS 0x00008000
139 #define US3_ITLB_MISS 0x00008800
140 #define US3_DTLB_MISS 0x00009000
141 #define US3_WC_MISS 0x00009800
142 #define US3_WC_SNOOP_CB 0x0000a000
143 #define US3_WC_SCRUBBED 0x0000a800
144 #define US3_WC_WB_WO_READ 0x0000b000
145 #define US3_PC_SOFT_HIT 0x0000c000
146 #define US3_PC_SNOOP_INV 0x0000c800
147 #define US3_PC_HARD_HIT 0x0000d000
148 #define US3_PC_PORT1_RD 0x0000d800
149 #define US3_SW_COUNT_1 0x0000e000
150 #define US3_IU_STAT_BR_MIS_UNTAKEN 0x0000e800
151 #define US3_IU_STAT_BR_COUNT_UNTAKEN 0x0000f000
152 #define US3_PC_MS_MISSES 0x0000f800
153 #define US3_MC_WRITES_0 0x00010800
154 #define US3_MC_WRITES_1 0x00011000
155 #define US3_MC_WRITES_2 0x00011800
156 #define US3_MC_WRITES_3 0x00012000
157 #define US3_MC_STALLS_1 0x00012800
158 #define US3_MC_STALLS_3 0x00013000
159 #define US3_RE_RAW_MISS 0x00013800
160 #define US3_FM_PIPE_COMPLETION 0x00014000
161
162 struct vcounter_struct {
163 unsigned long long vcnt0;
164 unsigned long long vcnt1;
165 };
166
167 #endif /* !(PERF_COUNTER_API) */
168
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