1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * leon_pci_grpci1.c: GRPCI1 Host PCI driver
4 *
5 * Copyright (C) 2013 Aeroflex Gaisler AB
6 *
7 * This GRPCI1 driver does not support PCI interrupts taken from
8 * GPIO pins. Interrupt generation at PCI parity and system error
9 * detection is by default turned off since some GRPCI1 cores does
10 * not support detection. It can be turned on from the bootloader
11 * using the all_pci_errors property.
12 *
13 * Contributors: Daniel Hellstrom <daniel@gaisler.com>
14 */
15
16 #include <linux/export.h>
17 #include <linux/kernel.h>
18 #include <linux/of.h>
19 #include <linux/of_irq.h>
20 #include <linux/platform_device.h>
21 #include <linux/delay.h>
22 #include <linux/pci.h>
23
24 #include <asm/leon_pci.h>
25 #include <asm/sections.h>
26 #include <asm/vaddrs.h>
27 #include <asm/leon.h>
28 #include <asm/io.h>
29
30 #include "irq.h"
31
32 /* Enable/Disable Debugging Configuration Space Access */
33 #undef GRPCI1_DEBUG_CFGACCESS
34
35 /*
36 * GRPCI1 APB Register MAP
37 */
38 struct grpci1_regs {
39 unsigned int cfg_stat; /* 0x00 Configuration / Status */
40 unsigned int bar0; /* 0x04 BAR0 (RO) */
41 unsigned int page0; /* 0x08 PAGE0 (RO) */
42 unsigned int bar1; /* 0x0C BAR1 (RO) */
43 unsigned int page1; /* 0x10 PAGE1 */
44 unsigned int iomap; /* 0x14 IO Map */
45 unsigned int stat_cmd; /* 0x18 PCI Status & Command (RO) */
46 unsigned int irq; /* 0x1C Interrupt register */
47 };
48
49 #define REGLOAD(a) (be32_to_cpu(__raw_readl(&(a))))
50 #define REGSTORE(a, v) (__raw_writel(cpu_to_be32(v), &(a)))
51
52 #define PAGE0_BTEN_BIT 0
53 #define PAGE0_BTEN (1 << PAGE0_BTEN_BIT)
54
55 #define CFGSTAT_HOST_BIT 13
56 #define CFGSTAT_CTO_BIT 8
57 #define CFGSTAT_HOST (1 << CFGSTAT_HOST_BIT)
58 #define CFGSTAT_CTO (1 << CFGSTAT_CTO_BIT)
59
60 #define IRQ_DPE (1 << 9)
61 #define IRQ_SSE (1 << 8)
62 #define IRQ_RMA (1 << 7)
63 #define IRQ_RTA (1 << 6)
64 #define IRQ_STA (1 << 5)
65 #define IRQ_DPED (1 << 4)
66 #define IRQ_INTD (1 << 3)
67 #define IRQ_INTC (1 << 2)
68 #define IRQ_INTB (1 << 1)
69 #define IRQ_INTA (1 << 0)
70 #define IRQ_DEF_ERRORS (IRQ_RMA | IRQ_RTA | IRQ_STA)
71 #define IRQ_ALL_ERRORS (IRQ_DPED | IRQ_DEF_ERRORS | IRQ_SSE | IRQ_DPE)
72 #define IRQ_INTX (IRQ_INTA | IRQ_INTB | IRQ_INTC | IRQ_INTD)
73 #define IRQ_MASK_BIT 16
74
75 #define DEF_PCI_ERRORS (PCI_STATUS_SIG_TARGET_ABORT | \
76 PCI_STATUS_REC_TARGET_ABORT | \
77 PCI_STATUS_REC_MASTER_ABORT)
78 #define ALL_PCI_ERRORS (PCI_STATUS_PARITY | PCI_STATUS_DETECTED_PARITY | \
79 PCI_STATUS_SIG_SYSTEM_ERROR | DEF_PCI_ERRORS)
80
81 #define TGT 256
82
83 struct grpci1_priv {
84 struct leon_pci_info info; /* must be on top of this structure */
85 struct grpci1_regs __iomem *regs; /* GRPCI register map */
86 struct device *dev;
87 int pci_err_mask; /* STATUS register error mask */
88 int irq; /* LEON irqctrl GRPCI IRQ */
89 unsigned char irq_map[4]; /* GRPCI nexus PCI INTX# IRQs */
90 unsigned int irq_err; /* GRPCI nexus Virt Error IRQ */
91
92 /* AHB PCI Windows */
93 unsigned long pci_area; /* MEMORY */
94 unsigned long pci_area_end;
95 unsigned long pci_io; /* I/O */
96 unsigned long pci_conf; /* CONFIGURATION */
97 unsigned long pci_conf_end;
98 unsigned long pci_io_va;
99 };
100
101 static struct grpci1_priv *grpci1priv;
102
103 static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
104 unsigned int devfn, int where, u32 val);
105
106 static int grpci1_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
107 {
108 struct grpci1_priv *priv = dev->bus->sysdata;
109 int irq_group;
110
111 /* Use default IRQ decoding on PCI BUS0 according slot numbering */
112 irq_group = slot & 0x3;
113 pin = ((pin - 1) + irq_group) & 0x3;
114
115 return priv->irq_map[pin];
116 }
117
118 static int grpci1_cfg_r32(struct grpci1_priv *priv, unsigned int bus,
119 unsigned int devfn, int where, u32 *val)
120 {
121 u32 *pci_conf, tmp, cfg;
122
123 if (where & 0x3)
124 return -EINVAL;
125
126 if (bus == 0) {
127 devfn += (0x8 * 6); /* start at AD16=Device0 */
128 } else if (bus == TGT) {
129 bus = 0;
130 devfn = 0; /* special case: bridge controller itself */
131 }
132
133 /* Select bus */
134 cfg = REGLOAD(priv->regs->cfg_stat);
135 REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
136
137 /* do read access */
138 pci_conf = (u32 *) (priv->pci_conf | (devfn << 8) | (where & 0xfc));
139 tmp = LEON3_BYPASS_LOAD_PA(pci_conf);
140
141 /* check if master abort was received */
142 if (REGLOAD(priv->regs->cfg_stat) & CFGSTAT_CTO) {
143 *val = 0xffffffff;
144 /* Clear Master abort bit in PCI cfg space (is set) */
145 tmp = REGLOAD(priv->regs->stat_cmd);
146 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, tmp);
147 } else {
148 /* Bus always little endian (unaffected by byte-swapping) */
149 *val = swab32(tmp);
150 }
151
152 return 0;
153 }
154
155 static int grpci1_cfg_r16(struct grpci1_priv *priv, unsigned int bus,
156 unsigned int devfn, int where, u32 *val)
157 {
158 u32 v;
159 int ret;
160
161 if (where & 0x1)
162 return -EINVAL;
163 ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
164 *val = 0xffff & (v >> (8 * (where & 0x3)));
165 return ret;
166 }
167
168 static int grpci1_cfg_r8(struct grpci1_priv *priv, unsigned int bus,
169 unsigned int devfn, int where, u32 *val)
170 {
171 u32 v;
172 int ret;
173
174 ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
175 *val = 0xff & (v >> (8 * (where & 3)));
176
177 return ret;
178 }
179
180 static int grpci1_cfg_w32(struct grpci1_priv *priv, unsigned int bus,
181 unsigned int devfn, int where, u32 val)
182 {
183 unsigned int *pci_conf;
184 u32 cfg;
185
186 if (where & 0x3)
187 return -EINVAL;
188
189 if (bus == 0) {
190 devfn += (0x8 * 6); /* start at AD16=Device0 */
191 } else if (bus == TGT) {
192 bus = 0;
193 devfn = 0; /* special case: bridge controller itself */
194 }
195
196 /* Select bus */
197 cfg = REGLOAD(priv->regs->cfg_stat);
198 REGSTORE(priv->regs->cfg_stat, (cfg & ~(0xf << 23)) | (bus << 23));
199
200 pci_conf = (unsigned int *) (priv->pci_conf |
201 (devfn << 8) | (where & 0xfc));
202 LEON3_BYPASS_STORE_PA(pci_conf, swab32(val));
203
204 return 0;
205 }
206
207 static int grpci1_cfg_w16(struct grpci1_priv *priv, unsigned int bus,
208 unsigned int devfn, int where, u32 val)
209 {
210 int ret;
211 u32 v;
212
213 if (where & 0x1)
214 return -EINVAL;
215 ret = grpci1_cfg_r32(priv, bus, devfn, where&~3, &v);
216 if (ret)
217 return ret;
218 v = (v & ~(0xffff << (8 * (where & 0x3)))) |
219 ((0xffff & val) << (8 * (where & 0x3)));
220 return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
221 }
222
223 static int grpci1_cfg_w8(struct grpci1_priv *priv, unsigned int bus,
224 unsigned int devfn, int where, u32 val)
225 {
226 int ret;
227 u32 v;
228
229 ret = grpci1_cfg_r32(priv, bus, devfn, where & ~0x3, &v);
230 if (ret != 0)
231 return ret;
232 v = (v & ~(0xff << (8 * (where & 0x3)))) |
233 ((0xff & val) << (8 * (where & 0x3)));
234 return grpci1_cfg_w32(priv, bus, devfn, where & ~0x3, v);
235 }
236
237 /* Read from Configuration Space. When entering here the PCI layer has taken
238 * the pci_lock spinlock and IRQ is off.
239 */
240 static int grpci1_read_config(struct pci_bus *bus, unsigned int devfn,
241 int where, int size, u32 *val)
242 {
243 struct grpci1_priv *priv = grpci1priv;
244 unsigned int busno = bus->number;
245 int ret;
246
247 if (PCI_SLOT(devfn) > 15 || busno > 15) {
248 *val = ~0;
249 return 0;
250 }
251
252 switch (size) {
253 case 1:
254 ret = grpci1_cfg_r8(priv, busno, devfn, where, val);
255 break;
256 case 2:
257 ret = grpci1_cfg_r16(priv, busno, devfn, where, val);
258 break;
259 case 4:
260 ret = grpci1_cfg_r32(priv, busno, devfn, where, val);
261 break;
262 default:
263 ret = -EINVAL;
264 break;
265 }
266
267 #ifdef GRPCI1_DEBUG_CFGACCESS
268 printk(KERN_INFO
269 "grpci1_read_config: [%02x:%02x:%x] ofs=%d val=%x size=%d\n",
270 busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, *val, size);
271 #endif
272
273 return ret;
274 }
275
276 /* Write to Configuration Space. When entering here the PCI layer has taken
277 * the pci_lock spinlock and IRQ is off.
278 */
279 static int grpci1_write_config(struct pci_bus *bus, unsigned int devfn,
280 int where, int size, u32 val)
281 {
282 struct grpci1_priv *priv = grpci1priv;
283 unsigned int busno = bus->number;
284
285 if (PCI_SLOT(devfn) > 15 || busno > 15)
286 return 0;
287
288 #ifdef GRPCI1_DEBUG_CFGACCESS
289 printk(KERN_INFO
290 "grpci1_write_config: [%02x:%02x:%x] ofs=%d size=%d val=%x\n",
291 busno, PCI_SLOT(devfn), PCI_FUNC(devfn), where, size, val);
292 #endif
293
294 switch (size) {
295 default:
296 return -EINVAL;
297 case 1:
298 return grpci1_cfg_w8(priv, busno, devfn, where, val);
299 case 2:
300 return grpci1_cfg_w16(priv, busno, devfn, where, val);
301 case 4:
302 return grpci1_cfg_w32(priv, busno, devfn, where, val);
303 }
304 }
305
306 static struct pci_ops grpci1_ops = {
307 .read = grpci1_read_config,
308 .write = grpci1_write_config,
309 };
310
311 /* GENIRQ IRQ chip implementation for grpci1 irqmode=0..2. In configuration
312 * 3 where all PCI Interrupts has a separate IRQ on the system IRQ controller
313 * this is not needed and the standard IRQ controller can be used.
314 */
315
316 static void grpci1_mask_irq(struct irq_data *data)
317 {
318 u32 irqidx;
319 struct grpci1_priv *priv = grpci1priv;
320
321 irqidx = (u32)data->chip_data - 1;
322 if (irqidx > 3) /* only mask PCI interrupts here */
323 return;
324 irqidx += IRQ_MASK_BIT;
325
326 REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) & ~(1 << irqidx));
327 }
328
329 static void grpci1_unmask_irq(struct irq_data *data)
330 {
331 u32 irqidx;
332 struct grpci1_priv *priv = grpci1priv;
333
334 irqidx = (u32)data->chip_data - 1;
335 if (irqidx > 3) /* only unmask PCI interrupts here */
336 return;
337 irqidx += IRQ_MASK_BIT;
338
339 REGSTORE(priv->regs->irq, REGLOAD(priv->regs->irq) | (1 << irqidx));
340 }
341
342 static unsigned int grpci1_startup_irq(struct irq_data *data)
343 {
344 grpci1_unmask_irq(data);
345 return 0;
346 }
347
348 static void grpci1_shutdown_irq(struct irq_data *data)
349 {
350 grpci1_mask_irq(data);
351 }
352
353 static struct irq_chip grpci1_irq = {
354 .name = "grpci1",
355 .irq_startup = grpci1_startup_irq,
356 .irq_shutdown = grpci1_shutdown_irq,
357 .irq_mask = grpci1_mask_irq,
358 .irq_unmask = grpci1_unmask_irq,
359 };
360
361 /* Handle one or multiple IRQs from the PCI core */
362 static void grpci1_pci_flow_irq(struct irq_desc *desc)
363 {
364 struct grpci1_priv *priv = grpci1priv;
365 int i, ack = 0;
366 unsigned int irqreg;
367
368 irqreg = REGLOAD(priv->regs->irq);
369 irqreg = (irqreg >> IRQ_MASK_BIT) & irqreg;
370
371 /* Error Interrupt? */
372 if (irqreg & IRQ_ALL_ERRORS) {
373 generic_handle_irq(priv->irq_err);
374 ack = 1;
375 }
376
377 /* PCI Interrupt? */
378 if (irqreg & IRQ_INTX) {
379 /* Call respective PCI Interrupt handler */
380 for (i = 0; i < 4; i++) {
381 if (irqreg & (1 << i))
382 generic_handle_irq(priv->irq_map[i]);
383 }
384 ack = 1;
385 }
386
387 /*
388 * Call "first level" IRQ chip end-of-irq handler. It will ACK LEON IRQ
389 * Controller, this must be done after IRQ sources have been handled to
390 * avoid double IRQ generation
391 */
392 if (ack)
393 desc->irq_data.chip->irq_eoi(&desc->irq_data);
394 }
395
396 /* Create a virtual IRQ */
397 static unsigned int grpci1_build_device_irq(unsigned int irq)
398 {
399 unsigned int virq = 0, pil;
400
401 pil = 1 << 8;
402 virq = irq_alloc(irq, pil);
403 if (virq == 0)
404 goto out;
405
406 irq_set_chip_and_handler_name(virq, &grpci1_irq, handle_simple_irq,
407 "pcilvl");
408 irq_set_chip_data(virq, (void *)irq);
409
410 out:
411 return virq;
412 }
413
414 /*
415 * Initialize mappings AMBA<->PCI, clear IRQ state, setup PCI interface
416 *
417 * Target BARs:
418 * BAR0: unused in this implementation
419 * BAR1: peripheral DMA to host's memory (size at least 256MByte)
420 * BAR2..BAR5: not implemented in hardware
421 */
422 static void grpci1_hw_init(struct grpci1_priv *priv)
423 {
424 u32 ahbadr, bar_sz, data, pciadr;
425 struct grpci1_regs __iomem *regs = priv->regs;
426
427 /* set 1:1 mapping between AHB -> PCI memory space */
428 REGSTORE(regs->cfg_stat, priv->pci_area & 0xf0000000);
429
430 /* map PCI accesses to target BAR1 to Linux kernel memory 1:1 */
431 ahbadr = 0xf0000000 & (u32)__pa(PAGE_ALIGN((unsigned long) &_end));
432 REGSTORE(regs->page1, ahbadr);
433
434 /* translate I/O accesses to 0, I/O Space always @ PCI low 64Kbytes */
435 REGSTORE(regs->iomap, REGLOAD(regs->iomap) & 0x0000ffff);
436
437 /* disable and clear pending interrupts */
438 REGSTORE(regs->irq, 0);
439
440 /* Setup BAR0 outside access range so that it does not conflict with
441 * peripheral DMA. There is no need to set up the PAGE0 register.
442 */
443 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, 0xffffffff);
444 grpci1_cfg_r32(priv, TGT, 0, PCI_BASE_ADDRESS_0, &bar_sz);
445 bar_sz = ~bar_sz + 1;
446 pciadr = priv->pci_area - bar_sz;
447 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_0, pciadr);
448
449 /*
450 * Setup the Host's PCI Target BAR1 for other peripherals to access,
451 * and do DMA to the host's memory.
452 */
453 grpci1_cfg_w32(priv, TGT, 0, PCI_BASE_ADDRESS_1, ahbadr);
454
455 /*
456 * Setup Latency Timer and cache line size. Default cache line
457 * size will result in poor performance (256 word fetches), 0xff
458 * will set it according to the max size of the PCI FIFO.
459 */
460 grpci1_cfg_w8(priv, TGT, 0, PCI_CACHE_LINE_SIZE, 0xff);
461 grpci1_cfg_w8(priv, TGT, 0, PCI_LATENCY_TIMER, 0x40);
462
463 /* set as bus master, enable pci memory responses, clear status bits */
464 grpci1_cfg_r32(priv, TGT, 0, PCI_COMMAND, &data);
465 data |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
466 grpci1_cfg_w32(priv, TGT, 0, PCI_COMMAND, data);
467 }
468
469 static irqreturn_t grpci1_jump_interrupt(int irq, void *arg)
470 {
471 struct grpci1_priv *priv = arg;
472 dev_err(priv->dev, "Jump IRQ happened\n");
473 return IRQ_NONE;
474 }
475
476 /* Handle GRPCI1 Error Interrupt */
477 static irqreturn_t grpci1_err_interrupt(int irq, void *arg)
478 {
479 struct grpci1_priv *priv = arg;
480 u32 status;
481
482 grpci1_cfg_r16(priv, TGT, 0, PCI_STATUS, &status);
483 status &= priv->pci_err_mask;
484
485 if (status == 0)
486 return IRQ_NONE;
487
488 if (status & PCI_STATUS_PARITY)
489 dev_err(priv->dev, "Data Parity Error\n");
490
491 if (status & PCI_STATUS_SIG_TARGET_ABORT)
492 dev_err(priv->dev, "Signalled Target Abort\n");
493
494 if (status & PCI_STATUS_REC_TARGET_ABORT)
495 dev_err(priv->dev, "Received Target Abort\n");
496
497 if (status & PCI_STATUS_REC_MASTER_ABORT)
498 dev_err(priv->dev, "Received Master Abort\n");
499
500 if (status & PCI_STATUS_SIG_SYSTEM_ERROR)
501 dev_err(priv->dev, "Signalled System Error\n");
502
503 if (status & PCI_STATUS_DETECTED_PARITY)
504 dev_err(priv->dev, "Parity Error\n");
505
506 /* Clear handled INT TYPE IRQs */
507 grpci1_cfg_w16(priv, TGT, 0, PCI_STATUS, status);
508
509 return IRQ_HANDLED;
510 }
511
512 static int grpci1_of_probe(struct platform_device *ofdev)
513 {
514 struct grpci1_regs __iomem *regs;
515 struct grpci1_priv *priv;
516 int err, len;
517 const int *tmp;
518 u32 cfg, size, err_mask;
519 struct resource *res;
520
521 if (grpci1priv) {
522 dev_err(&ofdev->dev, "only one GRPCI1 supported\n");
523 return -ENODEV;
524 }
525
526 if (ofdev->num_resources < 3) {
527 dev_err(&ofdev->dev, "not enough APB/AHB resources\n");
528 return -EIO;
529 }
530
531 priv = devm_kzalloc(&ofdev->dev, sizeof(*priv), GFP_KERNEL);
532 if (!priv) {
533 dev_err(&ofdev->dev, "memory allocation failed\n");
534 return -ENOMEM;
535 }
536 platform_set_drvdata(ofdev, priv);
537 priv->dev = &ofdev->dev;
538
539 /* find device register base address */
540 res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
541 regs = devm_ioremap_resource(&ofdev->dev, res);
542 if (IS_ERR(regs))
543 return PTR_ERR(regs);
544
545 /*
546 * check that we're in Host Slot and that we can act as a Host Bridge
547 * and not only as target/peripheral.
548 */
549 cfg = REGLOAD(regs->cfg_stat);
550 if ((cfg & CFGSTAT_HOST) == 0) {
551 dev_err(&ofdev->dev, "not in host system slot\n");
552 return -EIO;
553 }
554
555 /* check that BAR1 support 256 MByte so that we can map kernel space */
556 REGSTORE(regs->page1, 0xffffffff);
557 size = ~REGLOAD(regs->page1) + 1;
558 if (size < 0x10000000) {
559 dev_err(&ofdev->dev, "BAR1 must be at least 256MByte\n");
560 return -EIO;
561 }
562
563 /* hardware must support little-endian PCI (byte-twisting) */
564 if ((REGLOAD(regs->page0) & PAGE0_BTEN) == 0) {
565 dev_err(&ofdev->dev, "byte-twisting is required\n");
566 return -EIO;
567 }
568
569 priv->regs = regs;
570 priv->irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
571 dev_info(&ofdev->dev, "host found at 0x%p, irq%d\n", regs, priv->irq);
572
573 /* Find PCI Memory, I/O and Configuration Space Windows */
574 priv->pci_area = ofdev->resource[1].start;
575 priv->pci_area_end = ofdev->resource[1].end+1;
576 priv->pci_io = ofdev->resource[2].start;
577 priv->pci_conf = ofdev->resource[2].start + 0x10000;
578 priv->pci_conf_end = priv->pci_conf + 0x10000;
579 priv->pci_io_va = (unsigned long)ioremap(priv->pci_io, 0x10000);
580 if (!priv->pci_io_va) {
581 dev_err(&ofdev->dev, "unable to map PCI I/O area\n");
582 return -EIO;
583 }
584
585 printk(KERN_INFO
586 "GRPCI1: MEMORY SPACE [0x%08lx - 0x%08lx]\n"
587 " I/O SPACE [0x%08lx - 0x%08lx]\n"
588 " CONFIG SPACE [0x%08lx - 0x%08lx]\n",
589 priv->pci_area, priv->pci_area_end-1,
590 priv->pci_io, priv->pci_conf-1,
591 priv->pci_conf, priv->pci_conf_end-1);
592
593 /*
594 * I/O Space resources in I/O Window mapped into Virtual Adr Space
595 * We never use low 4KB because some devices seem have problems using
596 * address 0.
597 */
598 priv->info.io_space.name = "GRPCI1 PCI I/O Space";
599 priv->info.io_space.start = priv->pci_io_va + 0x1000;
600 priv->info.io_space.end = priv->pci_io_va + 0x10000 - 1;
601 priv->info.io_space.flags = IORESOURCE_IO;
602
603 /*
604 * grpci1 has no prefetchable memory, map everything as
605 * non-prefetchable memory
606 */
607 priv->info.mem_space.name = "GRPCI1 PCI MEM Space";
608 priv->info.mem_space.start = priv->pci_area;
609 priv->info.mem_space.end = priv->pci_area_end - 1;
610 priv->info.mem_space.flags = IORESOURCE_MEM;
611
612 if (request_resource(&iomem_resource, &priv->info.mem_space) < 0) {
613 dev_err(&ofdev->dev, "unable to request PCI memory area\n");
614 err = -ENOMEM;
615 goto err1;
616 }
617
618 if (request_resource(&ioport_resource, &priv->info.io_space) < 0) {
619 dev_err(&ofdev->dev, "unable to request PCI I/O area\n");
620 err = -ENOMEM;
621 goto err2;
622 }
623
624 /* setup maximum supported PCI buses */
625 priv->info.busn.name = "GRPCI1 busn";
626 priv->info.busn.start = 0;
627 priv->info.busn.end = 15;
628
629 grpci1priv = priv;
630
631 /* Initialize hardware */
632 grpci1_hw_init(priv);
633
634 /*
635 * Get PCI Interrupt to System IRQ mapping and setup IRQ handling
636 * Error IRQ. All PCI and PCI-Error interrupts are shared using the
637 * same system IRQ.
638 */
639 leon_update_virq_handling(priv->irq, grpci1_pci_flow_irq, "pcilvl", 0);
640
641 priv->irq_map[0] = grpci1_build_device_irq(1);
642 priv->irq_map[1] = grpci1_build_device_irq(2);
643 priv->irq_map[2] = grpci1_build_device_irq(3);
644 priv->irq_map[3] = grpci1_build_device_irq(4);
645 priv->irq_err = grpci1_build_device_irq(5);
646
647 printk(KERN_INFO " PCI INTA..D#: IRQ%d, IRQ%d, IRQ%d, IRQ%d\n",
648 priv->irq_map[0], priv->irq_map[1], priv->irq_map[2],
649 priv->irq_map[3]);
650
651 /* Enable IRQs on LEON IRQ controller */
652 err = devm_request_irq(&ofdev->dev, priv->irq, grpci1_jump_interrupt, 0,
653 "GRPCI1_JUMP", priv);
654 if (err) {
655 dev_err(&ofdev->dev, "ERR IRQ request failed: %d\n", err);
656 goto err3;
657 }
658
659 /* Setup IRQ handler for access errors */
660 err = devm_request_irq(&ofdev->dev, priv->irq_err,
661 grpci1_err_interrupt, IRQF_SHARED, "GRPCI1_ERR",
662 priv);
663 if (err) {
664 dev_err(&ofdev->dev, "ERR VIRQ request failed: %d\n", err);
665 goto err3;
666 }
667
668 tmp = of_get_property(ofdev->dev.of_node, "all_pci_errors", &len);
669 if (tmp && (len == 4)) {
670 priv->pci_err_mask = ALL_PCI_ERRORS;
671 err_mask = IRQ_ALL_ERRORS << IRQ_MASK_BIT;
672 } else {
673 priv->pci_err_mask = DEF_PCI_ERRORS;
674 err_mask = IRQ_DEF_ERRORS << IRQ_MASK_BIT;
675 }
676
677 /*
678 * Enable Error Interrupts. PCI interrupts are unmasked once request_irq
679 * is called by the PCI Device drivers
680 */
681 REGSTORE(regs->irq, err_mask);
682
683 /* Init common layer and scan buses */
684 priv->info.ops = &grpci1_ops;
685 priv->info.map_irq = grpci1_map_irq;
686 leon_pci_init(ofdev, &priv->info);
687
688 return 0;
689
690 err3:
691 release_resource(&priv->info.io_space);
692 err2:
693 release_resource(&priv->info.mem_space);
694 err1:
695 iounmap((void __iomem *)priv->pci_io_va);
696 grpci1priv = NULL;
697 return err;
698 }
699
700 static const struct of_device_id grpci1_of_match[] = {
701 {
702 .name = "GAISLER_PCIFBRG",
703 },
704 {
705 .name = "01_014",
706 },
707 {},
708 };
709
710 static struct platform_driver grpci1_of_driver = {
711 .driver = {
712 .name = "grpci1",
713 .of_match_table = grpci1_of_match,
714 },
715 .probe = grpci1_of_probe,
716 };
717
718 static int __init grpci1_init(void)
719 {
720 return platform_driver_register(&grpci1_of_driver);
721 }
722
723 subsys_initcall(grpci1_init);
724
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