1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * sun4m irq support
4 *
5 * djhr: Hacked out of irq.c into a CPU dependent version.
6 *
7 * Copyright (C) 1995 David S. Miller (davem@caip.rutgers.edu)
8 * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
9 * Copyright (C) 1995 Pete A. Zaitcev (zaitcev@yahoo.com)
10 * Copyright (C) 1996 Dave Redman (djhr@tadpole.co.uk)
11 */
12
13 #include <linux/slab.h>
14 #include <linux/sched/debug.h>
15 #include <linux/pgtable.h>
16
17 #include <asm/timer.h>
18 #include <asm/traps.h>
19 #include <asm/irq.h>
20 #include <asm/io.h>
21 #include <asm/cacheflush.h>
22
23 #include "irq.h"
24 #include "kernel.h"
25
26 /* Sample sun4m IRQ layout:
27 *
28 * 0x22 - Power
29 * 0x24 - ESP SCSI
30 * 0x26 - Lance ethernet
31 * 0x2b - Floppy
32 * 0x2c - Zilog uart
33 * 0x32 - SBUS level 0
34 * 0x33 - Parallel port, SBUS level 1
35 * 0x35 - SBUS level 2
36 * 0x37 - SBUS level 3
37 * 0x39 - Audio, Graphics card, SBUS level 4
38 * 0x3b - SBUS level 5
39 * 0x3d - SBUS level 6
40 *
41 * Each interrupt source has a mask bit in the interrupt registers.
42 * When the mask bit is set, this blocks interrupt deliver. So you
43 * clear the bit to enable the interrupt.
44 *
45 * Interrupts numbered less than 0x10 are software triggered interrupts
46 * and unused by Linux.
47 *
48 * Interrupt level assignment on sun4m:
49 *
50 * level source
51 * ------------------------------------------------------------
52 * 1 softint-1
53 * 2 softint-2, VME/SBUS level 1
54 * 3 softint-3, VME/SBUS level 2
55 * 4 softint-4, onboard SCSI
56 * 5 softint-5, VME/SBUS level 3
57 * 6 softint-6, onboard ETHERNET
58 * 7 softint-7, VME/SBUS level 4
59 * 8 softint-8, onboard VIDEO
60 * 9 softint-9, VME/SBUS level 5, Module Interrupt
61 * 10 softint-10, system counter/timer
62 * 11 softint-11, VME/SBUS level 6, Floppy
63 * 12 softint-12, Keyboard/Mouse, Serial
64 * 13 softint-13, VME/SBUS level 7, ISDN Audio
65 * 14 softint-14, per-processor counter/timer
66 * 15 softint-15, Asynchronous Errors (broadcast)
67 *
68 * Each interrupt source is masked distinctly in the sun4m interrupt
69 * registers. The PIL level alone is therefore ambiguous, since multiple
70 * interrupt sources map to a single PIL.
71 *
72 * This ambiguity is resolved in the 'intr' property for device nodes
73 * in the OF device tree. Each 'intr' property entry is composed of
74 * two 32-bit words. The first word is the IRQ priority value, which
75 * is what we're intersted in. The second word is the IRQ vector, which
76 * is unused.
77 *
78 * The low 4 bits of the IRQ priority indicate the PIL, and the upper
79 * 4 bits indicate onboard vs. SBUS leveled vs. VME leveled. 0x20
80 * means onboard, 0x30 means SBUS leveled, and 0x40 means VME leveled.
81 *
82 * For example, an 'intr' IRQ priority value of 0x24 is onboard SCSI
83 * whereas a value of 0x33 is SBUS level 2. Here are some sample
84 * 'intr' property IRQ priority values from ss4, ss5, ss10, ss20, and
85 * Tadpole S3 GX systems.
86 *
87 * esp: 0x24 onboard ESP SCSI
88 * le: 0x26 onboard Lance ETHERNET
89 * p9100: 0x32 SBUS level 1 P9100 video
90 * bpp: 0x33 SBUS level 2 BPP parallel port device
91 * DBRI: 0x39 SBUS level 5 DBRI ISDN audio
92 * SUNW,leo: 0x39 SBUS level 5 LEO video
93 * pcmcia: 0x3b SBUS level 6 PCMCIA controller
94 * uctrl: 0x3b SBUS level 6 UCTRL device
95 * modem: 0x3d SBUS level 7 MODEM
96 * zs: 0x2c onboard keyboard/mouse/serial
97 * floppy: 0x2b onboard Floppy
98 * power: 0x22 onboard power device (XXX unknown mask bit XXX)
99 */
100
101
102 /* Code in entry.S needs to get at these register mappings. */
103 struct sun4m_irq_percpu __iomem *sun4m_irq_percpu[SUN4M_NCPUS];
104 struct sun4m_irq_global __iomem *sun4m_irq_global;
105
106 struct sun4m_handler_data {
107 bool percpu;
108 long mask;
109 };
110
111 /* Dave Redman (djhr@tadpole.co.uk)
112 * The sun4m interrupt registers.
113 */
114 #define SUN4M_INT_ENABLE 0x80000000
115 #define SUN4M_INT_E14 0x00000080
116 #define SUN4M_INT_E10 0x00080000
117
118 #define SUN4M_INT_MASKALL 0x80000000 /* mask all interrupts */
119 #define SUN4M_INT_MODULE_ERR 0x40000000 /* module error */
120 #define SUN4M_INT_M2S_WRITE_ERR 0x20000000 /* write buffer error */
121 #define SUN4M_INT_ECC_ERR 0x10000000 /* ecc memory error */
122 #define SUN4M_INT_VME_ERR 0x08000000 /* vme async error */
123 #define SUN4M_INT_FLOPPY 0x00400000 /* floppy disk */
124 #define SUN4M_INT_MODULE 0x00200000 /* module interrupt */
125 #define SUN4M_INT_VIDEO 0x00100000 /* onboard video */
126 #define SUN4M_INT_REALTIME 0x00080000 /* system timer */
127 #define SUN4M_INT_SCSI 0x00040000 /* onboard scsi */
128 #define SUN4M_INT_AUDIO 0x00020000 /* audio/isdn */
129 #define SUN4M_INT_ETHERNET 0x00010000 /* onboard ethernet */
130 #define SUN4M_INT_SERIAL 0x00008000 /* serial ports */
131 #define SUN4M_INT_KBDMS 0x00004000 /* keyboard/mouse */
132 #define SUN4M_INT_SBUSBITS 0x00003F80 /* sbus int bits */
133 #define SUN4M_INT_VMEBITS 0x0000007F /* vme int bits */
134
135 #define SUN4M_INT_ERROR (SUN4M_INT_MODULE_ERR | \
136 SUN4M_INT_M2S_WRITE_ERR | \
137 SUN4M_INT_ECC_ERR | \
138 SUN4M_INT_VME_ERR)
139
140 #define SUN4M_INT_SBUS(x) (1 << (x+7))
141 #define SUN4M_INT_VME(x) (1 << (x))
142
143 /* Interrupt levels used by OBP */
144 #define OBP_INT_LEVEL_SOFT 0x10
145 #define OBP_INT_LEVEL_ONBOARD 0x20
146 #define OBP_INT_LEVEL_SBUS 0x30
147 #define OBP_INT_LEVEL_VME 0x40
148
149 #define SUN4M_TIMER_IRQ (OBP_INT_LEVEL_ONBOARD | 10)
150 #define SUN4M_PROFILE_IRQ (OBP_INT_LEVEL_ONBOARD | 14)
151
152 static unsigned long sun4m_imask[0x50] = {
153 /* 0x00 - SMP */
154 0, SUN4M_SOFT_INT(1),
155 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
156 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
157 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
158 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
159 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
160 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
161 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
162 /* 0x10 - soft */
163 0, SUN4M_SOFT_INT(1),
164 SUN4M_SOFT_INT(2), SUN4M_SOFT_INT(3),
165 SUN4M_SOFT_INT(4), SUN4M_SOFT_INT(5),
166 SUN4M_SOFT_INT(6), SUN4M_SOFT_INT(7),
167 SUN4M_SOFT_INT(8), SUN4M_SOFT_INT(9),
168 SUN4M_SOFT_INT(10), SUN4M_SOFT_INT(11),
169 SUN4M_SOFT_INT(12), SUN4M_SOFT_INT(13),
170 SUN4M_SOFT_INT(14), SUN4M_SOFT_INT(15),
171 /* 0x20 - onboard */
172 0, 0, 0, 0,
173 SUN4M_INT_SCSI, 0, SUN4M_INT_ETHERNET, 0,
174 SUN4M_INT_VIDEO, SUN4M_INT_MODULE,
175 SUN4M_INT_REALTIME, SUN4M_INT_FLOPPY,
176 (SUN4M_INT_SERIAL | SUN4M_INT_KBDMS),
177 SUN4M_INT_AUDIO, SUN4M_INT_E14, SUN4M_INT_MODULE_ERR,
178 /* 0x30 - sbus */
179 0, 0, SUN4M_INT_SBUS(0), SUN4M_INT_SBUS(1),
180 0, SUN4M_INT_SBUS(2), 0, SUN4M_INT_SBUS(3),
181 0, SUN4M_INT_SBUS(4), 0, SUN4M_INT_SBUS(5),
182 0, SUN4M_INT_SBUS(6), 0, 0,
183 /* 0x40 - vme */
184 0, 0, SUN4M_INT_VME(0), SUN4M_INT_VME(1),
185 0, SUN4M_INT_VME(2), 0, SUN4M_INT_VME(3),
186 0, SUN4M_INT_VME(4), 0, SUN4M_INT_VME(5),
187 0, SUN4M_INT_VME(6), 0, 0
188 };
189
190 static void sun4m_mask_irq(struct irq_data *data)
191 {
192 struct sun4m_handler_data *handler_data;
193 int cpu = smp_processor_id();
194
195 handler_data = irq_data_get_irq_handler_data(data);
196 if (handler_data->mask) {
197 unsigned long flags;
198
199 local_irq_save(flags);
200 if (handler_data->percpu) {
201 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->set);
202 } else {
203 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_set);
204 }
205 local_irq_restore(flags);
206 }
207 }
208
209 static void sun4m_unmask_irq(struct irq_data *data)
210 {
211 struct sun4m_handler_data *handler_data;
212 int cpu = smp_processor_id();
213
214 handler_data = irq_data_get_irq_handler_data(data);
215 if (handler_data->mask) {
216 unsigned long flags;
217
218 local_irq_save(flags);
219 if (handler_data->percpu) {
220 sbus_writel(handler_data->mask, &sun4m_irq_percpu[cpu]->clear);
221 } else {
222 sbus_writel(handler_data->mask, &sun4m_irq_global->mask_clear);
223 }
224 local_irq_restore(flags);
225 }
226 }
227
228 static unsigned int sun4m_startup_irq(struct irq_data *data)
229 {
230 irq_link(data->irq);
231 sun4m_unmask_irq(data);
232 return 0;
233 }
234
235 static void sun4m_shutdown_irq(struct irq_data *data)
236 {
237 sun4m_mask_irq(data);
238 irq_unlink(data->irq);
239 }
240
241 static struct irq_chip sun4m_irq = {
242 .name = "sun4m",
243 .irq_startup = sun4m_startup_irq,
244 .irq_shutdown = sun4m_shutdown_irq,
245 .irq_mask = sun4m_mask_irq,
246 .irq_unmask = sun4m_unmask_irq,
247 };
248
249
250 static unsigned int sun4m_build_device_irq(struct platform_device *op,
251 unsigned int real_irq)
252 {
253 struct sun4m_handler_data *handler_data;
254 unsigned int irq;
255 unsigned int pil;
256
257 if (real_irq >= OBP_INT_LEVEL_VME) {
258 prom_printf("Bogus sun4m IRQ %u\n", real_irq);
259 prom_halt();
260 }
261 pil = (real_irq & 0xf);
262 irq = irq_alloc(real_irq, pil);
263
264 if (irq == 0)
265 goto out;
266
267 handler_data = irq_get_handler_data(irq);
268 if (unlikely(handler_data))
269 goto out;
270
271 handler_data = kzalloc(sizeof(struct sun4m_handler_data), GFP_ATOMIC);
272 if (unlikely(!handler_data)) {
273 prom_printf("IRQ: kzalloc(sun4m_handler_data) failed.\n");
274 prom_halt();
275 }
276
277 handler_data->mask = sun4m_imask[real_irq];
278 handler_data->percpu = real_irq < OBP_INT_LEVEL_ONBOARD;
279 irq_set_chip_and_handler_name(irq, &sun4m_irq,
280 handle_level_irq, "level");
281 irq_set_handler_data(irq, handler_data);
282
283 out:
284 return irq;
285 }
286
287 struct sun4m_timer_percpu {
288 u32 l14_limit;
289 u32 l14_count;
290 u32 l14_limit_noclear;
291 u32 user_timer_start_stop;
292 };
293
294 static struct sun4m_timer_percpu __iomem *timers_percpu[SUN4M_NCPUS];
295
296 struct sun4m_timer_global {
297 u32 l10_limit;
298 u32 l10_count;
299 u32 l10_limit_noclear;
300 u32 reserved;
301 u32 timer_config;
302 };
303
304 static struct sun4m_timer_global __iomem *timers_global;
305
306 static void sun4m_clear_clock_irq(void)
307 {
308 sbus_readl(&timers_global->l10_limit);
309 }
310
311 void sun4m_nmi(struct pt_regs *regs)
312 {
313 unsigned long afsr, afar, si;
314
315 printk(KERN_ERR "Aieee: sun4m NMI received!\n");
316 /* XXX HyperSparc hack XXX */
317 __asm__ __volatile__("mov 0x500, %%g1\n\t"
318 "lda [%%g1] 0x4, %0\n\t"
319 "mov 0x600, %%g1\n\t"
320 "lda [%%g1] 0x4, %1\n\t" :
321 "=r" (afsr), "=r" (afar));
322 printk(KERN_ERR "afsr=%08lx afar=%08lx\n", afsr, afar);
323 si = sbus_readl(&sun4m_irq_global->pending);
324 printk(KERN_ERR "si=%08lx\n", si);
325 if (si & SUN4M_INT_MODULE_ERR)
326 printk(KERN_ERR "Module async error\n");
327 if (si & SUN4M_INT_M2S_WRITE_ERR)
328 printk(KERN_ERR "MBus/SBus async error\n");
329 if (si & SUN4M_INT_ECC_ERR)
330 printk(KERN_ERR "ECC memory error\n");
331 if (si & SUN4M_INT_VME_ERR)
332 printk(KERN_ERR "VME async error\n");
333 printk(KERN_ERR "you lose buddy boy...\n");
334 show_regs(regs);
335 prom_halt();
336 }
337
338 void sun4m_unmask_profile_irq(void)
339 {
340 unsigned long flags;
341
342 local_irq_save(flags);
343 sbus_writel(sun4m_imask[SUN4M_PROFILE_IRQ], &sun4m_irq_global->mask_clear);
344 local_irq_restore(flags);
345 }
346
347 void sun4m_clear_profile_irq(int cpu)
348 {
349 sbus_readl(&timers_percpu[cpu]->l14_limit);
350 }
351
352 static void sun4m_load_profile_irq(int cpu, unsigned int limit)
353 {
354 unsigned int value = limit ? timer_value(limit) : 0;
355 sbus_writel(value, &timers_percpu[cpu]->l14_limit);
356 }
357
358 static void __init sun4m_init_timers(void)
359 {
360 struct device_node *dp = of_find_node_by_name(NULL, "counter");
361 int i, err, len, num_cpu_timers;
362 unsigned int irq;
363 const u32 *addr;
364
365 if (!dp) {
366 printk(KERN_ERR "sun4m_init_timers: No 'counter' node.\n");
367 return;
368 }
369
370 addr = of_get_property(dp, "address", &len);
371 of_node_put(dp);
372 if (!addr) {
373 printk(KERN_ERR "sun4m_init_timers: No 'address' prop.\n");
374 return;
375 }
376
377 num_cpu_timers = (len / sizeof(u32)) - 1;
378 for (i = 0; i < num_cpu_timers; i++) {
379 timers_percpu[i] = (void __iomem *)
380 (unsigned long) addr[i];
381 }
382 timers_global = (void __iomem *)
383 (unsigned long) addr[num_cpu_timers];
384
385 /* Every per-cpu timer works in timer mode */
386 sbus_writel(0x00000000, &timers_global->timer_config);
387
388 #ifdef CONFIG_SMP
389 sparc_config.cs_period = SBUS_CLOCK_RATE * 2; /* 2 seconds */
390 sparc_config.features |= FEAT_L14_ONESHOT;
391 #else
392 sparc_config.cs_period = SBUS_CLOCK_RATE / HZ; /* 1/HZ sec */
393 sparc_config.features |= FEAT_L10_CLOCKEVENT;
394 #endif
395 sparc_config.features |= FEAT_L10_CLOCKSOURCE;
396 sbus_writel(timer_value(sparc_config.cs_period),
397 &timers_global->l10_limit);
398
399 master_l10_counter = &timers_global->l10_count;
400
401 irq = sun4m_build_device_irq(NULL, SUN4M_TIMER_IRQ);
402
403 err = request_irq(irq, timer_interrupt, IRQF_TIMER, "timer", NULL);
404 if (err) {
405 printk(KERN_ERR "sun4m_init_timers: Register IRQ error %d.\n",
406 err);
407 return;
408 }
409
410 for (i = 0; i < num_cpu_timers; i++)
411 sbus_writel(0, &timers_percpu[i]->l14_limit);
412 if (num_cpu_timers == 4)
413 sbus_writel(SUN4M_INT_E14, &sun4m_irq_global->mask_set);
414
415 #ifdef CONFIG_SMP
416 {
417 unsigned long flags;
418 struct tt_entry *trap_table = &sparc_ttable[SP_TRAP_IRQ1 + (14 - 1)];
419
420 /* For SMP we use the level 14 ticker, however the bootup code
421 * has copied the firmware's level 14 vector into the boot cpu's
422 * trap table, we must fix this now or we get squashed.
423 */
424 local_irq_save(flags);
425 trap_table->inst_one = lvl14_save[0];
426 trap_table->inst_two = lvl14_save[1];
427 trap_table->inst_three = lvl14_save[2];
428 trap_table->inst_four = lvl14_save[3];
429 local_ops->cache_all();
430 local_irq_restore(flags);
431 }
432 #endif
433 }
434
435 void __init sun4m_init_IRQ(void)
436 {
437 struct device_node *dp = of_find_node_by_name(NULL, "interrupt");
438 int len, i, mid, num_cpu_iregs;
439 const u32 *addr;
440
441 if (!dp) {
442 printk(KERN_ERR "sun4m_init_IRQ: No 'interrupt' node.\n");
443 return;
444 }
445
446 addr = of_get_property(dp, "address", &len);
447 of_node_put(dp);
448 if (!addr) {
449 printk(KERN_ERR "sun4m_init_IRQ: No 'address' prop.\n");
450 return;
451 }
452
453 num_cpu_iregs = (len / sizeof(u32)) - 1;
454 for (i = 0; i < num_cpu_iregs; i++) {
455 sun4m_irq_percpu[i] = (void __iomem *)
456 (unsigned long) addr[i];
457 }
458 sun4m_irq_global = (void __iomem *)
459 (unsigned long) addr[num_cpu_iregs];
460
461 local_irq_disable();
462
463 sbus_writel(~SUN4M_INT_MASKALL, &sun4m_irq_global->mask_set);
464 for (i = 0; !cpu_find_by_instance(i, NULL, &mid); i++)
465 sbus_writel(~0x17fff, &sun4m_irq_percpu[mid]->clear);
466
467 if (num_cpu_iregs == 4)
468 sbus_writel(0, &sun4m_irq_global->interrupt_target);
469
470 sparc_config.init_timers = sun4m_init_timers;
471 sparc_config.build_device_irq = sun4m_build_device_irq;
472 sparc_config.clock_rate = SBUS_CLOCK_RATE;
473 sparc_config.clear_clock_irq = sun4m_clear_clock_irq;
474 sparc_config.load_profile_irq = sun4m_load_profile_irq;
475
476
477 /* Cannot enable interrupts until OBP ticker is disabled. */
478 }
479
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