1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * arch/sparc64/mm/init.c
4 *
5 * Copyright (C) 1996-1999 David S. Miller (davem@caip.rutgers.edu)
6 * Copyright (C) 1997-1999 Jakub Jelinek (jj@sunsite.mff.cuni.cz)
7 */
8
9 #include <linux/extable.h>
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <linux/string.h>
13 #include <linux/init.h>
14 #include <linux/memblock.h>
15 #include <linux/mm.h>
16 #include <linux/hugetlb.h>
17 #include <linux/initrd.h>
18 #include <linux/swap.h>
19 #include <linux/pagemap.h>
20 #include <linux/poison.h>
21 #include <linux/fs.h>
22 #include <linux/seq_file.h>
23 #include <linux/kprobes.h>
24 #include <linux/cache.h>
25 #include <linux/sort.h>
26 #include <linux/ioport.h>
27 #include <linux/percpu.h>
28 #include <linux/mmzone.h>
29 #include <linux/gfp.h>
30 #include <linux/bootmem_info.h>
31
32 #include <asm/head.h>
33 #include <asm/page.h>
34 #include <asm/pgalloc.h>
35 #include <asm/oplib.h>
36 #include <asm/iommu.h>
37 #include <asm/io.h>
38 #include <linux/uaccess.h>
39 #include <asm/mmu_context.h>
40 #include <asm/tlbflush.h>
41 #include <asm/dma.h>
42 #include <asm/starfire.h>
43 #include <asm/tlb.h>
44 #include <asm/spitfire.h>
45 #include <asm/sections.h>
46 #include <asm/tsb.h>
47 #include <asm/hypervisor.h>
48 #include <asm/prom.h>
49 #include <asm/mdesc.h>
50 #include <asm/cpudata.h>
51 #include <asm/setup.h>
52 #include <asm/irq.h>
53
54 #include "init_64.h"
55
56 unsigned long kern_linear_pte_xor[4] __read_mostly;
57 static unsigned long page_cache4v_flag;
58
59 /* A bitmap, two bits for every 256MB of physical memory. These two
60 * bits determine what page size we use for kernel linear
61 * translations. They form an index into kern_linear_pte_xor[]. The
62 * value in the indexed slot is XOR'd with the TLB miss virtual
63 * address to form the resulting TTE. The mapping is:
64 *
65 * 0 ==> 4MB
66 * 1 ==> 256MB
67 * 2 ==> 2GB
68 * 3 ==> 16GB
69 *
70 * All sun4v chips support 256MB pages. Only SPARC-T4 and later
71 * support 2GB pages, and hopefully future cpus will support the 16GB
72 * pages as well. For slots 2 and 3, we encode a 256MB TTE xor there
73 * if these larger page sizes are not supported by the cpu.
74 *
75 * It would be nice to determine this from the machine description
76 * 'cpu' properties, but we need to have this table setup before the
77 * MDESC is initialized.
78 */
79
80 #ifndef CONFIG_DEBUG_PAGEALLOC
81 /* A special kernel TSB for 4MB, 256MB, 2GB and 16GB linear mappings.
82 * Space is allocated for this right after the trap table in
83 * arch/sparc64/kernel/head.S
84 */
85 extern struct tsb swapper_4m_tsb[KERNEL_TSB4M_NENTRIES];
86 #endif
87 extern struct tsb swapper_tsb[KERNEL_TSB_NENTRIES];
88
89 static unsigned long cpu_pgsz_mask;
90
91 #define MAX_BANKS 1024
92
93 static struct linux_prom64_registers pavail[MAX_BANKS];
94 static int pavail_ents;
95
96 u64 numa_latency[MAX_NUMNODES][MAX_NUMNODES];
97
98 static int cmp_p64(const void *a, const void *b)
99 {
100 const struct linux_prom64_registers *x = a, *y = b;
101
102 if (x->phys_addr > y->phys_addr)
103 return 1;
104 if (x->phys_addr < y->phys_addr)
105 return -1;
106 return 0;
107 }
108
109 static void __init read_obp_memory(const char *property,
110 struct linux_prom64_registers *regs,
111 int *num_ents)
112 {
113 phandle node = prom_finddevice("/memory");
114 int prop_size = prom_getproplen(node, property);
115 int ents, ret, i;
116
117 ents = prop_size / sizeof(struct linux_prom64_registers);
118 if (ents > MAX_BANKS) {
119 prom_printf("The machine has more %s property entries than "
120 "this kernel can support (%d).\n",
121 property, MAX_BANKS);
122 prom_halt();
123 }
124
125 ret = prom_getproperty(node, property, (char *) regs, prop_size);
126 if (ret == -1) {
127 prom_printf("Couldn't get %s property from /memory.\n",
128 property);
129 prom_halt();
130 }
131
132 /* Sanitize what we got from the firmware, by page aligning
133 * everything.
134 */
135 for (i = 0; i < ents; i++) {
136 unsigned long base, size;
137
138 base = regs[i].phys_addr;
139 size = regs[i].reg_size;
140
141 size &= PAGE_MASK;
142 if (base & ~PAGE_MASK) {
143 unsigned long new_base = PAGE_ALIGN(base);
144
145 size -= new_base - base;
146 if ((long) size < 0L)
147 size = 0UL;
148 base = new_base;
149 }
150 if (size == 0UL) {
151 /* If it is empty, simply get rid of it.
152 * This simplifies the logic of the other
153 * functions that process these arrays.
154 */
155 memmove(®s[i], ®s[i + 1],
156 (ents - i - 1) * sizeof(regs[0]));
157 i--;
158 ents--;
159 continue;
160 }
161 regs[i].phys_addr = base;
162 regs[i].reg_size = size;
163 }
164
165 *num_ents = ents;
166
167 sort(regs, ents, sizeof(struct linux_prom64_registers),
168 cmp_p64, NULL);
169 }
170
171 /* Kernel physical address base and size in bytes. */
172 unsigned long kern_base __read_mostly;
173 unsigned long kern_size __read_mostly;
174
175 /* Initial ramdisk setup */
176 extern unsigned long sparc_ramdisk_image64;
177 extern unsigned int sparc_ramdisk_image;
178 extern unsigned int sparc_ramdisk_size;
179
180 struct page *mem_map_zero __read_mostly;
181 EXPORT_SYMBOL(mem_map_zero);
182
183 unsigned int sparc64_highest_unlocked_tlb_ent __read_mostly;
184
185 unsigned long sparc64_kern_pri_context __read_mostly;
186 unsigned long sparc64_kern_pri_nuc_bits __read_mostly;
187 unsigned long sparc64_kern_sec_context __read_mostly;
188
189 int num_kernel_image_mappings;
190
191 #ifdef CONFIG_DEBUG_DCFLUSH
192 atomic_t dcpage_flushes = ATOMIC_INIT(0);
193 #ifdef CONFIG_SMP
194 atomic_t dcpage_flushes_xcall = ATOMIC_INIT(0);
195 #endif
196 #endif
197
198 inline void flush_dcache_folio_impl(struct folio *folio)
199 {
200 unsigned int i, nr = folio_nr_pages(folio);
201
202 BUG_ON(tlb_type == hypervisor);
203 #ifdef CONFIG_DEBUG_DCFLUSH
204 atomic_inc(&dcpage_flushes);
205 #endif
206
207 #ifdef DCACHE_ALIASING_POSSIBLE
208 for (i = 0; i < nr; i++)
209 __flush_dcache_page(folio_address(folio) + i * PAGE_SIZE,
210 ((tlb_type == spitfire) &&
211 folio_flush_mapping(folio) != NULL));
212 #else
213 if (folio_flush_mapping(folio) != NULL &&
214 tlb_type == spitfire) {
215 for (i = 0; i < nr; i++)
216 __flush_icache_page((pfn + i) * PAGE_SIZE);
217 }
218 #endif
219 }
220
221 #define PG_dcache_dirty PG_arch_1
222 #define PG_dcache_cpu_shift 32UL
223 #define PG_dcache_cpu_mask \
224 ((1UL<<ilog2(roundup_pow_of_two(NR_CPUS)))-1UL)
225
226 #define dcache_dirty_cpu(folio) \
227 (((folio)->flags >> PG_dcache_cpu_shift) & PG_dcache_cpu_mask)
228
229 static inline void set_dcache_dirty(struct folio *folio, int this_cpu)
230 {
231 unsigned long mask = this_cpu;
232 unsigned long non_cpu_bits;
233
234 non_cpu_bits = ~(PG_dcache_cpu_mask << PG_dcache_cpu_shift);
235 mask = (mask << PG_dcache_cpu_shift) | (1UL << PG_dcache_dirty);
236
237 __asm__ __volatile__("1:\n\t"
238 "ldx [%2], %%g7\n\t"
239 "and %%g7, %1, %%g1\n\t"
240 "or %%g1, %0, %%g1\n\t"
241 "casx [%2], %%g7, %%g1\n\t"
242 "cmp %%g7, %%g1\n\t"
243 "bne,pn %%xcc, 1b\n\t"
244 " nop"
245 : /* no outputs */
246 : "r" (mask), "r" (non_cpu_bits), "r" (&folio->flags)
247 : "g1", "g7");
248 }
249
250 static inline void clear_dcache_dirty_cpu(struct folio *folio, unsigned long cpu)
251 {
252 unsigned long mask = (1UL << PG_dcache_dirty);
253
254 __asm__ __volatile__("! test_and_clear_dcache_dirty\n"
255 "1:\n\t"
256 "ldx [%2], %%g7\n\t"
257 "srlx %%g7, %4, %%g1\n\t"
258 "and %%g1, %3, %%g1\n\t"
259 "cmp %%g1, %0\n\t"
260 "bne,pn %%icc, 2f\n\t"
261 " andn %%g7, %1, %%g1\n\t"
262 "casx [%2], %%g7, %%g1\n\t"
263 "cmp %%g7, %%g1\n\t"
264 "bne,pn %%xcc, 1b\n\t"
265 " nop\n"
266 "2:"
267 : /* no outputs */
268 : "r" (cpu), "r" (mask), "r" (&folio->flags),
269 "i" (PG_dcache_cpu_mask),
270 "i" (PG_dcache_cpu_shift)
271 : "g1", "g7");
272 }
273
274 static inline void tsb_insert(struct tsb *ent, unsigned long tag, unsigned long pte)
275 {
276 unsigned long tsb_addr = (unsigned long) ent;
277
278 if (tlb_type == cheetah_plus || tlb_type == hypervisor)
279 tsb_addr = __pa(tsb_addr);
280
281 __tsb_insert(tsb_addr, tag, pte);
282 }
283
284 unsigned long _PAGE_ALL_SZ_BITS __read_mostly;
285
286 static void flush_dcache(unsigned long pfn)
287 {
288 struct page *page;
289
290 page = pfn_to_page(pfn);
291 if (page) {
292 struct folio *folio = page_folio(page);
293 unsigned long pg_flags;
294
295 pg_flags = folio->flags;
296 if (pg_flags & (1UL << PG_dcache_dirty)) {
297 int cpu = ((pg_flags >> PG_dcache_cpu_shift) &
298 PG_dcache_cpu_mask);
299 int this_cpu = get_cpu();
300
301 /* This is just to optimize away some function calls
302 * in the SMP case.
303 */
304 if (cpu == this_cpu)
305 flush_dcache_folio_impl(folio);
306 else
307 smp_flush_dcache_folio_impl(folio, cpu);
308
309 clear_dcache_dirty_cpu(folio, cpu);
310
311 put_cpu();
312 }
313 }
314 }
315
316 /* mm->context.lock must be held */
317 static void __update_mmu_tsb_insert(struct mm_struct *mm, unsigned long tsb_index,
318 unsigned long tsb_hash_shift, unsigned long address,
319 unsigned long tte)
320 {
321 struct tsb *tsb = mm->context.tsb_block[tsb_index].tsb;
322 unsigned long tag;
323
324 if (unlikely(!tsb))
325 return;
326
327 tsb += ((address >> tsb_hash_shift) &
328 (mm->context.tsb_block[tsb_index].tsb_nentries - 1UL));
329 tag = (address >> 22UL);
330 tsb_insert(tsb, tag, tte);
331 }
332
333 #ifdef CONFIG_HUGETLB_PAGE
334 static int __init hugetlbpage_init(void)
335 {
336 hugetlb_add_hstate(HPAGE_64K_SHIFT - PAGE_SHIFT);
337 hugetlb_add_hstate(HPAGE_SHIFT - PAGE_SHIFT);
338 hugetlb_add_hstate(HPAGE_256MB_SHIFT - PAGE_SHIFT);
339 hugetlb_add_hstate(HPAGE_2GB_SHIFT - PAGE_SHIFT);
340
341 return 0;
342 }
343
344 arch_initcall(hugetlbpage_init);
345
346 static void __init pud_huge_patch(void)
347 {
348 struct pud_huge_patch_entry *p;
349 unsigned long addr;
350
351 p = &__pud_huge_patch;
352 addr = p->addr;
353 *(unsigned int *)addr = p->insn;
354
355 __asm__ __volatile__("flush %0" : : "r" (addr));
356 }
357
358 bool __init arch_hugetlb_valid_size(unsigned long size)
359 {
360 unsigned int hugepage_shift = ilog2(size);
361 unsigned short hv_pgsz_idx;
362 unsigned int hv_pgsz_mask;
363
364 switch (hugepage_shift) {
365 case HPAGE_16GB_SHIFT:
366 hv_pgsz_mask = HV_PGSZ_MASK_16GB;
367 hv_pgsz_idx = HV_PGSZ_IDX_16GB;
368 pud_huge_patch();
369 break;
370 case HPAGE_2GB_SHIFT:
371 hv_pgsz_mask = HV_PGSZ_MASK_2GB;
372 hv_pgsz_idx = HV_PGSZ_IDX_2GB;
373 break;
374 case HPAGE_256MB_SHIFT:
375 hv_pgsz_mask = HV_PGSZ_MASK_256MB;
376 hv_pgsz_idx = HV_PGSZ_IDX_256MB;
377 break;
378 case HPAGE_SHIFT:
379 hv_pgsz_mask = HV_PGSZ_MASK_4MB;
380 hv_pgsz_idx = HV_PGSZ_IDX_4MB;
381 break;
382 case HPAGE_64K_SHIFT:
383 hv_pgsz_mask = HV_PGSZ_MASK_64K;
384 hv_pgsz_idx = HV_PGSZ_IDX_64K;
385 break;
386 default:
387 hv_pgsz_mask = 0;
388 }
389
390 if ((hv_pgsz_mask & cpu_pgsz_mask) == 0U)
391 return false;
392
393 return true;
394 }
395 #endif /* CONFIG_HUGETLB_PAGE */
396
397 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
398 unsigned long address, pte_t *ptep, unsigned int nr)
399 {
400 struct mm_struct *mm;
401 unsigned long flags;
402 bool is_huge_tsb;
403 pte_t pte = *ptep;
404 unsigned int i;
405
406 if (tlb_type != hypervisor) {
407 unsigned long pfn = pte_pfn(pte);
408
409 if (pfn_valid(pfn))
410 flush_dcache(pfn);
411 }
412
413 mm = vma->vm_mm;
414
415 /* Don't insert a non-valid PTE into the TSB, we'll deadlock. */
416 if (!pte_accessible(mm, pte))
417 return;
418
419 spin_lock_irqsave(&mm->context.lock, flags);
420
421 is_huge_tsb = false;
422 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
423 if (mm->context.hugetlb_pte_count || mm->context.thp_pte_count) {
424 unsigned long hugepage_size = PAGE_SIZE;
425
426 if (is_vm_hugetlb_page(vma))
427 hugepage_size = huge_page_size(hstate_vma(vma));
428
429 if (hugepage_size >= PUD_SIZE) {
430 unsigned long mask = 0x1ffc00000UL;
431
432 /* Transfer bits [32:22] from address to resolve
433 * at 4M granularity.
434 */
435 pte_val(pte) &= ~mask;
436 pte_val(pte) |= (address & mask);
437 } else if (hugepage_size >= PMD_SIZE) {
438 /* We are fabricating 8MB pages using 4MB
439 * real hw pages.
440 */
441 pte_val(pte) |= (address & (1UL << REAL_HPAGE_SHIFT));
442 }
443
444 if (hugepage_size >= PMD_SIZE) {
445 __update_mmu_tsb_insert(mm, MM_TSB_HUGE,
446 REAL_HPAGE_SHIFT, address, pte_val(pte));
447 is_huge_tsb = true;
448 }
449 }
450 #endif
451 if (!is_huge_tsb) {
452 for (i = 0; i < nr; i++) {
453 __update_mmu_tsb_insert(mm, MM_TSB_BASE, PAGE_SHIFT,
454 address, pte_val(pte));
455 address += PAGE_SIZE;
456 pte_val(pte) += PAGE_SIZE;
457 }
458 }
459
460 spin_unlock_irqrestore(&mm->context.lock, flags);
461 }
462
463 void flush_dcache_folio(struct folio *folio)
464 {
465 unsigned long pfn = folio_pfn(folio);
466 struct address_space *mapping;
467 int this_cpu;
468
469 if (tlb_type == hypervisor)
470 return;
471
472 /* Do not bother with the expensive D-cache flush if it
473 * is merely the zero page. The 'bigcore' testcase in GDB
474 * causes this case to run millions of times.
475 */
476 if (is_zero_pfn(pfn))
477 return;
478
479 this_cpu = get_cpu();
480
481 mapping = folio_flush_mapping(folio);
482 if (mapping && !mapping_mapped(mapping)) {
483 bool dirty = test_bit(PG_dcache_dirty, &folio->flags);
484 if (dirty) {
485 int dirty_cpu = dcache_dirty_cpu(folio);
486
487 if (dirty_cpu == this_cpu)
488 goto out;
489 smp_flush_dcache_folio_impl(folio, dirty_cpu);
490 }
491 set_dcache_dirty(folio, this_cpu);
492 } else {
493 /* We could delay the flush for the !folio_mapping
494 * case too. But that case is for exec env/arg
495 * pages and those are %99 certainly going to get
496 * faulted into the tlb (and thus flushed) anyways.
497 */
498 flush_dcache_folio_impl(folio);
499 }
500
501 out:
502 put_cpu();
503 }
504 EXPORT_SYMBOL(flush_dcache_folio);
505
506 void __kprobes flush_icache_range(unsigned long start, unsigned long end)
507 {
508 /* Cheetah and Hypervisor platform cpus have coherent I-cache. */
509 if (tlb_type == spitfire) {
510 unsigned long kaddr;
511
512 /* This code only runs on Spitfire cpus so this is
513 * why we can assume _PAGE_PADDR_4U.
514 */
515 for (kaddr = start; kaddr < end; kaddr += PAGE_SIZE) {
516 unsigned long paddr, mask = _PAGE_PADDR_4U;
517
518 if (kaddr >= PAGE_OFFSET)
519 paddr = kaddr & mask;
520 else {
521 pte_t *ptep = virt_to_kpte(kaddr);
522
523 paddr = pte_val(*ptep) & mask;
524 }
525 __flush_icache_page(paddr);
526 }
527 }
528 }
529 EXPORT_SYMBOL(flush_icache_range);
530
531 void mmu_info(struct seq_file *m)
532 {
533 static const char *pgsz_strings[] = {
534 "8K", "64K", "512K", "4MB", "32MB",
535 "256MB", "2GB", "16GB",
536 };
537 int i, printed;
538
539 if (tlb_type == cheetah)
540 seq_printf(m, "MMU Type\t: Cheetah\n");
541 else if (tlb_type == cheetah_plus)
542 seq_printf(m, "MMU Type\t: Cheetah+\n");
543 else if (tlb_type == spitfire)
544 seq_printf(m, "MMU Type\t: Spitfire\n");
545 else if (tlb_type == hypervisor)
546 seq_printf(m, "MMU Type\t: Hypervisor (sun4v)\n");
547 else
548 seq_printf(m, "MMU Type\t: ???\n");
549
550 seq_printf(m, "MMU PGSZs\t: ");
551 printed = 0;
552 for (i = 0; i < ARRAY_SIZE(pgsz_strings); i++) {
553 if (cpu_pgsz_mask & (1UL << i)) {
554 seq_printf(m, "%s%s",
555 printed ? "," : "", pgsz_strings[i]);
556 printed++;
557 }
558 }
559 seq_putc(m, '\n');
560
561 #ifdef CONFIG_DEBUG_DCFLUSH
562 seq_printf(m, "DCPageFlushes\t: %d\n",
563 atomic_read(&dcpage_flushes));
564 #ifdef CONFIG_SMP
565 seq_printf(m, "DCPageFlushesXC\t: %d\n",
566 atomic_read(&dcpage_flushes_xcall));
567 #endif /* CONFIG_SMP */
568 #endif /* CONFIG_DEBUG_DCFLUSH */
569 }
570
571 struct linux_prom_translation prom_trans[512] __read_mostly;
572 unsigned int prom_trans_ents __read_mostly;
573
574 unsigned long kern_locked_tte_data;
575
576 /* The obp translations are saved based on 8k pagesize, since obp can
577 * use a mixture of pagesizes. Misses to the LOW_OBP_ADDRESS ->
578 * HI_OBP_ADDRESS range are handled in ktlb.S.
579 */
580 static inline int in_obp_range(unsigned long vaddr)
581 {
582 return (vaddr >= LOW_OBP_ADDRESS &&
583 vaddr < HI_OBP_ADDRESS);
584 }
585
586 static int cmp_ptrans(const void *a, const void *b)
587 {
588 const struct linux_prom_translation *x = a, *y = b;
589
590 if (x->virt > y->virt)
591 return 1;
592 if (x->virt < y->virt)
593 return -1;
594 return 0;
595 }
596
597 /* Read OBP translations property into 'prom_trans[]'. */
598 static void __init read_obp_translations(void)
599 {
600 int n, node, ents, first, last, i;
601
602 node = prom_finddevice("/virtual-memory");
603 n = prom_getproplen(node, "translations");
604 if (unlikely(n == 0 || n == -1)) {
605 prom_printf("prom_mappings: Couldn't get size.\n");
606 prom_halt();
607 }
608 if (unlikely(n > sizeof(prom_trans))) {
609 prom_printf("prom_mappings: Size %d is too big.\n", n);
610 prom_halt();
611 }
612
613 if ((n = prom_getproperty(node, "translations",
614 (char *)&prom_trans[0],
615 sizeof(prom_trans))) == -1) {
616 prom_printf("prom_mappings: Couldn't get property.\n");
617 prom_halt();
618 }
619
620 n = n / sizeof(struct linux_prom_translation);
621
622 ents = n;
623
624 sort(prom_trans, ents, sizeof(struct linux_prom_translation),
625 cmp_ptrans, NULL);
626
627 /* Now kick out all the non-OBP entries. */
628 for (i = 0; i < ents; i++) {
629 if (in_obp_range(prom_trans[i].virt))
630 break;
631 }
632 first = i;
633 for (; i < ents; i++) {
634 if (!in_obp_range(prom_trans[i].virt))
635 break;
636 }
637 last = i;
638
639 for (i = 0; i < (last - first); i++) {
640 struct linux_prom_translation *src = &prom_trans[i + first];
641 struct linux_prom_translation *dest = &prom_trans[i];
642
643 *dest = *src;
644 }
645 for (; i < ents; i++) {
646 struct linux_prom_translation *dest = &prom_trans[i];
647 dest->virt = dest->size = dest->data = 0x0UL;
648 }
649
650 prom_trans_ents = last - first;
651
652 if (tlb_type == spitfire) {
653 /* Clear diag TTE bits. */
654 for (i = 0; i < prom_trans_ents; i++)
655 prom_trans[i].data &= ~0x0003fe0000000000UL;
656 }
657
658 /* Force execute bit on. */
659 for (i = 0; i < prom_trans_ents; i++)
660 prom_trans[i].data |= (tlb_type == hypervisor ?
661 _PAGE_EXEC_4V : _PAGE_EXEC_4U);
662 }
663
664 static void __init hypervisor_tlb_lock(unsigned long vaddr,
665 unsigned long pte,
666 unsigned long mmu)
667 {
668 unsigned long ret = sun4v_mmu_map_perm_addr(vaddr, 0, pte, mmu);
669
670 if (ret != 0) {
671 prom_printf("hypervisor_tlb_lock[%lx:%x:%lx:%lx]: "
672 "errors with %lx\n", vaddr, 0, pte, mmu, ret);
673 prom_halt();
674 }
675 }
676
677 static unsigned long kern_large_tte(unsigned long paddr);
678
679 static void __init remap_kernel(void)
680 {
681 unsigned long phys_page, tte_vaddr, tte_data;
682 int i, tlb_ent = sparc64_highest_locked_tlbent();
683
684 tte_vaddr = (unsigned long) KERNBASE;
685 phys_page = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
686 tte_data = kern_large_tte(phys_page);
687
688 kern_locked_tte_data = tte_data;
689
690 /* Now lock us into the TLBs via Hypervisor or OBP. */
691 if (tlb_type == hypervisor) {
692 for (i = 0; i < num_kernel_image_mappings; i++) {
693 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_DMMU);
694 hypervisor_tlb_lock(tte_vaddr, tte_data, HV_MMU_IMMU);
695 tte_vaddr += 0x400000;
696 tte_data += 0x400000;
697 }
698 } else {
699 for (i = 0; i < num_kernel_image_mappings; i++) {
700 prom_dtlb_load(tlb_ent - i, tte_data, tte_vaddr);
701 prom_itlb_load(tlb_ent - i, tte_data, tte_vaddr);
702 tte_vaddr += 0x400000;
703 tte_data += 0x400000;
704 }
705 sparc64_highest_unlocked_tlb_ent = tlb_ent - i;
706 }
707 if (tlb_type == cheetah_plus) {
708 sparc64_kern_pri_context = (CTX_CHEETAH_PLUS_CTX0 |
709 CTX_CHEETAH_PLUS_NUC);
710 sparc64_kern_pri_nuc_bits = CTX_CHEETAH_PLUS_NUC;
711 sparc64_kern_sec_context = CTX_CHEETAH_PLUS_CTX0;
712 }
713 }
714
715
716 static void __init inherit_prom_mappings(void)
717 {
718 /* Now fixup OBP's idea about where we really are mapped. */
719 printk("Remapping the kernel... ");
720 remap_kernel();
721 printk("done.\n");
722 }
723
724 void prom_world(int enter)
725 {
726 /*
727 * No need to change the address space any more, just flush
728 * the register windows
729 */
730 __asm__ __volatile__("flushw");
731 }
732
733 void __flush_dcache_range(unsigned long start, unsigned long end)
734 {
735 unsigned long va;
736
737 if (tlb_type == spitfire) {
738 int n = 0;
739
740 for (va = start; va < end; va += 32) {
741 spitfire_put_dcache_tag(va & 0x3fe0, 0x0);
742 if (++n >= 512)
743 break;
744 }
745 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
746 start = __pa(start);
747 end = __pa(end);
748 for (va = start; va < end; va += 32)
749 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
750 "membar #Sync"
751 : /* no outputs */
752 : "r" (va),
753 "i" (ASI_DCACHE_INVALIDATE));
754 }
755 }
756 EXPORT_SYMBOL(__flush_dcache_range);
757
758 /* get_new_mmu_context() uses "cache + 1". */
759 DEFINE_SPINLOCK(ctx_alloc_lock);
760 unsigned long tlb_context_cache = CTX_FIRST_VERSION;
761 #define MAX_CTX_NR (1UL << CTX_NR_BITS)
762 #define CTX_BMAP_SLOTS BITS_TO_LONGS(MAX_CTX_NR)
763 DECLARE_BITMAP(mmu_context_bmap, MAX_CTX_NR);
764 DEFINE_PER_CPU(struct mm_struct *, per_cpu_secondary_mm) = {0};
765
766 static void mmu_context_wrap(void)
767 {
768 unsigned long old_ver = tlb_context_cache & CTX_VERSION_MASK;
769 unsigned long new_ver, new_ctx, old_ctx;
770 struct mm_struct *mm;
771 int cpu;
772
773 bitmap_zero(mmu_context_bmap, 1 << CTX_NR_BITS);
774
775 /* Reserve kernel context */
776 set_bit(0, mmu_context_bmap);
777
778 new_ver = (tlb_context_cache & CTX_VERSION_MASK) + CTX_FIRST_VERSION;
779 if (unlikely(new_ver == 0))
780 new_ver = CTX_FIRST_VERSION;
781 tlb_context_cache = new_ver;
782
783 /*
784 * Make sure that any new mm that are added into per_cpu_secondary_mm,
785 * are going to go through get_new_mmu_context() path.
786 */
787 mb();
788
789 /*
790 * Updated versions to current on those CPUs that had valid secondary
791 * contexts
792 */
793 for_each_online_cpu(cpu) {
794 /*
795 * If a new mm is stored after we took this mm from the array,
796 * it will go into get_new_mmu_context() path, because we
797 * already bumped the version in tlb_context_cache.
798 */
799 mm = per_cpu(per_cpu_secondary_mm, cpu);
800
801 if (unlikely(!mm || mm == &init_mm))
802 continue;
803
804 old_ctx = mm->context.sparc64_ctx_val;
805 if (likely((old_ctx & CTX_VERSION_MASK) == old_ver)) {
806 new_ctx = (old_ctx & ~CTX_VERSION_MASK) | new_ver;
807 set_bit(new_ctx & CTX_NR_MASK, mmu_context_bmap);
808 mm->context.sparc64_ctx_val = new_ctx;
809 }
810 }
811 }
812
813 /* Caller does TLB context flushing on local CPU if necessary.
814 * The caller also ensures that CTX_VALID(mm->context) is false.
815 *
816 * We must be careful about boundary cases so that we never
817 * let the user have CTX 0 (nucleus) or we ever use a CTX
818 * version of zero (and thus NO_CONTEXT would not be caught
819 * by version mis-match tests in mmu_context.h).
820 *
821 * Always invoked with interrupts disabled.
822 */
823 void get_new_mmu_context(struct mm_struct *mm)
824 {
825 unsigned long ctx, new_ctx;
826 unsigned long orig_pgsz_bits;
827
828 spin_lock(&ctx_alloc_lock);
829 retry:
830 /* wrap might have happened, test again if our context became valid */
831 if (unlikely(CTX_VALID(mm->context)))
832 goto out;
833 orig_pgsz_bits = (mm->context.sparc64_ctx_val & CTX_PGSZ_MASK);
834 ctx = (tlb_context_cache + 1) & CTX_NR_MASK;
835 new_ctx = find_next_zero_bit(mmu_context_bmap, 1 << CTX_NR_BITS, ctx);
836 if (new_ctx >= (1 << CTX_NR_BITS)) {
837 new_ctx = find_next_zero_bit(mmu_context_bmap, ctx, 1);
838 if (new_ctx >= ctx) {
839 mmu_context_wrap();
840 goto retry;
841 }
842 }
843 if (mm->context.sparc64_ctx_val)
844 cpumask_clear(mm_cpumask(mm));
845 mmu_context_bmap[new_ctx>>6] |= (1UL << (new_ctx & 63));
846 new_ctx |= (tlb_context_cache & CTX_VERSION_MASK);
847 tlb_context_cache = new_ctx;
848 mm->context.sparc64_ctx_val = new_ctx | orig_pgsz_bits;
849 out:
850 spin_unlock(&ctx_alloc_lock);
851 }
852
853 static int numa_enabled = 1;
854 static int numa_debug;
855
856 static int __init early_numa(char *p)
857 {
858 if (!p)
859 return 0;
860
861 if (strstr(p, "off"))
862 numa_enabled = 0;
863
864 if (strstr(p, "debug"))
865 numa_debug = 1;
866
867 return 0;
868 }
869 early_param("numa", early_numa);
870
871 #define numadbg(f, a...) \
872 do { if (numa_debug) \
873 printk(KERN_INFO f, ## a); \
874 } while (0)
875
876 static void __init find_ramdisk(unsigned long phys_base)
877 {
878 #ifdef CONFIG_BLK_DEV_INITRD
879 if (sparc_ramdisk_image || sparc_ramdisk_image64) {
880 unsigned long ramdisk_image;
881
882 /* Older versions of the bootloader only supported a
883 * 32-bit physical address for the ramdisk image
884 * location, stored at sparc_ramdisk_image. Newer
885 * SILO versions set sparc_ramdisk_image to zero and
886 * provide a full 64-bit physical address at
887 * sparc_ramdisk_image64.
888 */
889 ramdisk_image = sparc_ramdisk_image;
890 if (!ramdisk_image)
891 ramdisk_image = sparc_ramdisk_image64;
892
893 /* Another bootloader quirk. The bootloader normalizes
894 * the physical address to KERNBASE, so we have to
895 * factor that back out and add in the lowest valid
896 * physical page address to get the true physical address.
897 */
898 ramdisk_image -= KERNBASE;
899 ramdisk_image += phys_base;
900
901 numadbg("Found ramdisk at physical address 0x%lx, size %u\n",
902 ramdisk_image, sparc_ramdisk_size);
903
904 initrd_start = ramdisk_image;
905 initrd_end = ramdisk_image + sparc_ramdisk_size;
906
907 memblock_reserve(initrd_start, sparc_ramdisk_size);
908
909 initrd_start += PAGE_OFFSET;
910 initrd_end += PAGE_OFFSET;
911 }
912 #endif
913 }
914
915 struct node_mem_mask {
916 unsigned long mask;
917 unsigned long match;
918 };
919 static struct node_mem_mask node_masks[MAX_NUMNODES];
920 static int num_node_masks;
921
922 #ifdef CONFIG_NUMA
923
924 struct mdesc_mlgroup {
925 u64 node;
926 u64 latency;
927 u64 match;
928 u64 mask;
929 };
930
931 static struct mdesc_mlgroup *mlgroups;
932 static int num_mlgroups;
933
934 int numa_cpu_lookup_table[NR_CPUS];
935 cpumask_t numa_cpumask_lookup_table[MAX_NUMNODES];
936
937 struct mdesc_mblock {
938 u64 base;
939 u64 size;
940 u64 offset; /* RA-to-PA */
941 };
942 static struct mdesc_mblock *mblocks;
943 static int num_mblocks;
944
945 static struct mdesc_mblock * __init addr_to_mblock(unsigned long addr)
946 {
947 struct mdesc_mblock *m = NULL;
948 int i;
949
950 for (i = 0; i < num_mblocks; i++) {
951 m = &mblocks[i];
952
953 if (addr >= m->base &&
954 addr < (m->base + m->size)) {
955 break;
956 }
957 }
958
959 return m;
960 }
961
962 static u64 __init memblock_nid_range_sun4u(u64 start, u64 end, int *nid)
963 {
964 int prev_nid, new_nid;
965
966 prev_nid = NUMA_NO_NODE;
967 for ( ; start < end; start += PAGE_SIZE) {
968 for (new_nid = 0; new_nid < num_node_masks; new_nid++) {
969 struct node_mem_mask *p = &node_masks[new_nid];
970
971 if ((start & p->mask) == p->match) {
972 if (prev_nid == NUMA_NO_NODE)
973 prev_nid = new_nid;
974 break;
975 }
976 }
977
978 if (new_nid == num_node_masks) {
979 prev_nid = 0;
980 WARN_ONCE(1, "addr[%Lx] doesn't match a NUMA node rule. Some memory will be owned by node 0.",
981 start);
982 break;
983 }
984
985 if (prev_nid != new_nid)
986 break;
987 }
988 *nid = prev_nid;
989
990 return start > end ? end : start;
991 }
992
993 static u64 __init memblock_nid_range(u64 start, u64 end, int *nid)
994 {
995 u64 ret_end, pa_start, m_mask, m_match, m_end;
996 struct mdesc_mblock *mblock;
997 int _nid, i;
998
999 if (tlb_type != hypervisor)
1000 return memblock_nid_range_sun4u(start, end, nid);
1001
1002 mblock = addr_to_mblock(start);
1003 if (!mblock) {
1004 WARN_ONCE(1, "memblock_nid_range: Can't find mblock addr[%Lx]",
1005 start);
1006
1007 _nid = 0;
1008 ret_end = end;
1009 goto done;
1010 }
1011
1012 pa_start = start + mblock->offset;
1013 m_match = 0;
1014 m_mask = 0;
1015
1016 for (_nid = 0; _nid < num_node_masks; _nid++) {
1017 struct node_mem_mask *const m = &node_masks[_nid];
1018
1019 if ((pa_start & m->mask) == m->match) {
1020 m_match = m->match;
1021 m_mask = m->mask;
1022 break;
1023 }
1024 }
1025
1026 if (num_node_masks == _nid) {
1027 /* We could not find NUMA group, so default to 0, but lets
1028 * search for latency group, so we could calculate the correct
1029 * end address that we return
1030 */
1031 _nid = 0;
1032
1033 for (i = 0; i < num_mlgroups; i++) {
1034 struct mdesc_mlgroup *const m = &mlgroups[i];
1035
1036 if ((pa_start & m->mask) == m->match) {
1037 m_match = m->match;
1038 m_mask = m->mask;
1039 break;
1040 }
1041 }
1042
1043 if (i == num_mlgroups) {
1044 WARN_ONCE(1, "memblock_nid_range: Can't find latency group addr[%Lx]",
1045 start);
1046
1047 ret_end = end;
1048 goto done;
1049 }
1050 }
1051
1052 /*
1053 * Each latency group has match and mask, and each memory block has an
1054 * offset. An address belongs to a latency group if its address matches
1055 * the following formula: ((addr + offset) & mask) == match
1056 * It is, however, slow to check every single page if it matches a
1057 * particular latency group. As optimization we calculate end value by
1058 * using bit arithmetics.
1059 */
1060 m_end = m_match + (1ul << __ffs(m_mask)) - mblock->offset;
1061 m_end += pa_start & ~((1ul << fls64(m_mask)) - 1);
1062 ret_end = m_end > end ? end : m_end;
1063
1064 done:
1065 *nid = _nid;
1066 return ret_end;
1067 }
1068 #endif
1069
1070 /* This must be invoked after performing all of the necessary
1071 * memblock_set_node() calls for 'nid'. We need to be able to get
1072 * correct data from get_pfn_range_for_nid().
1073 */
1074 static void __init allocate_node_data(int nid)
1075 {
1076 struct pglist_data *p;
1077 unsigned long start_pfn, end_pfn;
1078 #ifdef CONFIG_NUMA
1079
1080 NODE_DATA(nid) = memblock_alloc_node(sizeof(struct pglist_data),
1081 SMP_CACHE_BYTES, nid);
1082 if (!NODE_DATA(nid)) {
1083 prom_printf("Cannot allocate pglist_data for nid[%d]\n", nid);
1084 prom_halt();
1085 }
1086
1087 NODE_DATA(nid)->node_id = nid;
1088 #endif
1089
1090 p = NODE_DATA(nid);
1091
1092 get_pfn_range_for_nid(nid, &start_pfn, &end_pfn);
1093 p->node_start_pfn = start_pfn;
1094 p->node_spanned_pages = end_pfn - start_pfn;
1095 }
1096
1097 static void init_node_masks_nonnuma(void)
1098 {
1099 #ifdef CONFIG_NUMA
1100 int i;
1101 #endif
1102
1103 numadbg("Initializing tables for non-numa.\n");
1104
1105 node_masks[0].mask = 0;
1106 node_masks[0].match = 0;
1107 num_node_masks = 1;
1108
1109 #ifdef CONFIG_NUMA
1110 for (i = 0; i < NR_CPUS; i++)
1111 numa_cpu_lookup_table[i] = 0;
1112
1113 cpumask_setall(&numa_cpumask_lookup_table[0]);
1114 #endif
1115 }
1116
1117 #ifdef CONFIG_NUMA
1118 struct pglist_data *node_data[MAX_NUMNODES];
1119
1120 EXPORT_SYMBOL(numa_cpu_lookup_table);
1121 EXPORT_SYMBOL(numa_cpumask_lookup_table);
1122 EXPORT_SYMBOL(node_data);
1123
1124 static int scan_pio_for_cfg_handle(struct mdesc_handle *md, u64 pio,
1125 u32 cfg_handle)
1126 {
1127 u64 arc;
1128
1129 mdesc_for_each_arc(arc, md, pio, MDESC_ARC_TYPE_FWD) {
1130 u64 target = mdesc_arc_target(md, arc);
1131 const u64 *val;
1132
1133 val = mdesc_get_property(md, target,
1134 "cfg-handle", NULL);
1135 if (val && *val == cfg_handle)
1136 return 0;
1137 }
1138 return -ENODEV;
1139 }
1140
1141 static int scan_arcs_for_cfg_handle(struct mdesc_handle *md, u64 grp,
1142 u32 cfg_handle)
1143 {
1144 u64 arc, candidate, best_latency = ~(u64)0;
1145
1146 candidate = MDESC_NODE_NULL;
1147 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1148 u64 target = mdesc_arc_target(md, arc);
1149 const char *name = mdesc_node_name(md, target);
1150 const u64 *val;
1151
1152 if (strcmp(name, "pio-latency-group"))
1153 continue;
1154
1155 val = mdesc_get_property(md, target, "latency", NULL);
1156 if (!val)
1157 continue;
1158
1159 if (*val < best_latency) {
1160 candidate = target;
1161 best_latency = *val;
1162 }
1163 }
1164
1165 if (candidate == MDESC_NODE_NULL)
1166 return -ENODEV;
1167
1168 return scan_pio_for_cfg_handle(md, candidate, cfg_handle);
1169 }
1170
1171 int of_node_to_nid(struct device_node *dp)
1172 {
1173 const struct linux_prom64_registers *regs;
1174 struct mdesc_handle *md;
1175 u32 cfg_handle;
1176 int count, nid;
1177 u64 grp;
1178
1179 /* This is the right thing to do on currently supported
1180 * SUN4U NUMA platforms as well, as the PCI controller does
1181 * not sit behind any particular memory controller.
1182 */
1183 if (!mlgroups)
1184 return -1;
1185
1186 regs = of_get_property(dp, "reg", NULL);
1187 if (!regs)
1188 return -1;
1189
1190 cfg_handle = (regs->phys_addr >> 32UL) & 0x0fffffff;
1191
1192 md = mdesc_grab();
1193
1194 count = 0;
1195 nid = NUMA_NO_NODE;
1196 mdesc_for_each_node_by_name(md, grp, "group") {
1197 if (!scan_arcs_for_cfg_handle(md, grp, cfg_handle)) {
1198 nid = count;
1199 break;
1200 }
1201 count++;
1202 }
1203
1204 mdesc_release(md);
1205
1206 return nid;
1207 }
1208
1209 static void __init add_node_ranges(void)
1210 {
1211 phys_addr_t start, end;
1212 unsigned long prev_max;
1213 u64 i;
1214
1215 memblock_resized:
1216 prev_max = memblock.memory.max;
1217
1218 for_each_mem_range(i, &start, &end) {
1219 while (start < end) {
1220 unsigned long this_end;
1221 int nid;
1222
1223 this_end = memblock_nid_range(start, end, &nid);
1224
1225 numadbg("Setting memblock NUMA node nid[%d] "
1226 "start[%llx] end[%lx]\n",
1227 nid, start, this_end);
1228
1229 memblock_set_node(start, this_end - start,
1230 &memblock.memory, nid);
1231 if (memblock.memory.max != prev_max)
1232 goto memblock_resized;
1233 start = this_end;
1234 }
1235 }
1236 }
1237
1238 static int __init grab_mlgroups(struct mdesc_handle *md)
1239 {
1240 unsigned long paddr;
1241 int count = 0;
1242 u64 node;
1243
1244 mdesc_for_each_node_by_name(md, node, "memory-latency-group")
1245 count++;
1246 if (!count)
1247 return -ENOENT;
1248
1249 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mlgroup),
1250 SMP_CACHE_BYTES);
1251 if (!paddr)
1252 return -ENOMEM;
1253
1254 mlgroups = __va(paddr);
1255 num_mlgroups = count;
1256
1257 count = 0;
1258 mdesc_for_each_node_by_name(md, node, "memory-latency-group") {
1259 struct mdesc_mlgroup *m = &mlgroups[count++];
1260 const u64 *val;
1261
1262 m->node = node;
1263
1264 val = mdesc_get_property(md, node, "latency", NULL);
1265 m->latency = *val;
1266 val = mdesc_get_property(md, node, "address-match", NULL);
1267 m->match = *val;
1268 val = mdesc_get_property(md, node, "address-mask", NULL);
1269 m->mask = *val;
1270
1271 numadbg("MLGROUP[%d]: node[%llx] latency[%llx] "
1272 "match[%llx] mask[%llx]\n",
1273 count - 1, m->node, m->latency, m->match, m->mask);
1274 }
1275
1276 return 0;
1277 }
1278
1279 static int __init grab_mblocks(struct mdesc_handle *md)
1280 {
1281 unsigned long paddr;
1282 int count = 0;
1283 u64 node;
1284
1285 mdesc_for_each_node_by_name(md, node, "mblock")
1286 count++;
1287 if (!count)
1288 return -ENOENT;
1289
1290 paddr = memblock_phys_alloc(count * sizeof(struct mdesc_mblock),
1291 SMP_CACHE_BYTES);
1292 if (!paddr)
1293 return -ENOMEM;
1294
1295 mblocks = __va(paddr);
1296 num_mblocks = count;
1297
1298 count = 0;
1299 mdesc_for_each_node_by_name(md, node, "mblock") {
1300 struct mdesc_mblock *m = &mblocks[count++];
1301 const u64 *val;
1302
1303 val = mdesc_get_property(md, node, "base", NULL);
1304 m->base = *val;
1305 val = mdesc_get_property(md, node, "size", NULL);
1306 m->size = *val;
1307 val = mdesc_get_property(md, node,
1308 "address-congruence-offset", NULL);
1309
1310 /* The address-congruence-offset property is optional.
1311 * Explicity zero it be identifty this.
1312 */
1313 if (val)
1314 m->offset = *val;
1315 else
1316 m->offset = 0UL;
1317
1318 numadbg("MBLOCK[%d]: base[%llx] size[%llx] offset[%llx]\n",
1319 count - 1, m->base, m->size, m->offset);
1320 }
1321
1322 return 0;
1323 }
1324
1325 static void __init numa_parse_mdesc_group_cpus(struct mdesc_handle *md,
1326 u64 grp, cpumask_t *mask)
1327 {
1328 u64 arc;
1329
1330 cpumask_clear(mask);
1331
1332 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_BACK) {
1333 u64 target = mdesc_arc_target(md, arc);
1334 const char *name = mdesc_node_name(md, target);
1335 const u64 *id;
1336
1337 if (strcmp(name, "cpu"))
1338 continue;
1339 id = mdesc_get_property(md, target, "id", NULL);
1340 if (*id < nr_cpu_ids)
1341 cpumask_set_cpu(*id, mask);
1342 }
1343 }
1344
1345 static struct mdesc_mlgroup * __init find_mlgroup(u64 node)
1346 {
1347 int i;
1348
1349 for (i = 0; i < num_mlgroups; i++) {
1350 struct mdesc_mlgroup *m = &mlgroups[i];
1351 if (m->node == node)
1352 return m;
1353 }
1354 return NULL;
1355 }
1356
1357 int __node_distance(int from, int to)
1358 {
1359 if ((from >= MAX_NUMNODES) || (to >= MAX_NUMNODES)) {
1360 pr_warn("Returning default NUMA distance value for %d->%d\n",
1361 from, to);
1362 return (from == to) ? LOCAL_DISTANCE : REMOTE_DISTANCE;
1363 }
1364 return numa_latency[from][to];
1365 }
1366 EXPORT_SYMBOL(__node_distance);
1367
1368 static int __init find_best_numa_node_for_mlgroup(struct mdesc_mlgroup *grp)
1369 {
1370 int i;
1371
1372 for (i = 0; i < MAX_NUMNODES; i++) {
1373 struct node_mem_mask *n = &node_masks[i];
1374
1375 if ((grp->mask == n->mask) && (grp->match == n->match))
1376 break;
1377 }
1378 return i;
1379 }
1380
1381 static void __init find_numa_latencies_for_group(struct mdesc_handle *md,
1382 u64 grp, int index)
1383 {
1384 u64 arc;
1385
1386 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1387 int tnode;
1388 u64 target = mdesc_arc_target(md, arc);
1389 struct mdesc_mlgroup *m = find_mlgroup(target);
1390
1391 if (!m)
1392 continue;
1393 tnode = find_best_numa_node_for_mlgroup(m);
1394 if (tnode == MAX_NUMNODES)
1395 continue;
1396 numa_latency[index][tnode] = m->latency;
1397 }
1398 }
1399
1400 static int __init numa_attach_mlgroup(struct mdesc_handle *md, u64 grp,
1401 int index)
1402 {
1403 struct mdesc_mlgroup *candidate = NULL;
1404 u64 arc, best_latency = ~(u64)0;
1405 struct node_mem_mask *n;
1406
1407 mdesc_for_each_arc(arc, md, grp, MDESC_ARC_TYPE_FWD) {
1408 u64 target = mdesc_arc_target(md, arc);
1409 struct mdesc_mlgroup *m = find_mlgroup(target);
1410 if (!m)
1411 continue;
1412 if (m->latency < best_latency) {
1413 candidate = m;
1414 best_latency = m->latency;
1415 }
1416 }
1417 if (!candidate)
1418 return -ENOENT;
1419
1420 if (num_node_masks != index) {
1421 printk(KERN_ERR "Inconsistent NUMA state, "
1422 "index[%d] != num_node_masks[%d]\n",
1423 index, num_node_masks);
1424 return -EINVAL;
1425 }
1426
1427 n = &node_masks[num_node_masks++];
1428
1429 n->mask = candidate->mask;
1430 n->match = candidate->match;
1431
1432 numadbg("NUMA NODE[%d]: mask[%lx] match[%lx] (latency[%llx])\n",
1433 index, n->mask, n->match, candidate->latency);
1434
1435 return 0;
1436 }
1437
1438 static int __init numa_parse_mdesc_group(struct mdesc_handle *md, u64 grp,
1439 int index)
1440 {
1441 cpumask_t mask;
1442 int cpu;
1443
1444 numa_parse_mdesc_group_cpus(md, grp, &mask);
1445
1446 for_each_cpu(cpu, &mask)
1447 numa_cpu_lookup_table[cpu] = index;
1448 cpumask_copy(&numa_cpumask_lookup_table[index], &mask);
1449
1450 if (numa_debug) {
1451 printk(KERN_INFO "NUMA GROUP[%d]: cpus [ ", index);
1452 for_each_cpu(cpu, &mask)
1453 printk("%d ", cpu);
1454 printk("]\n");
1455 }
1456
1457 return numa_attach_mlgroup(md, grp, index);
1458 }
1459
1460 static int __init numa_parse_mdesc(void)
1461 {
1462 struct mdesc_handle *md = mdesc_grab();
1463 int i, j, err, count;
1464 u64 node;
1465
1466 node = mdesc_node_by_name(md, MDESC_NODE_NULL, "latency-groups");
1467 if (node == MDESC_NODE_NULL) {
1468 mdesc_release(md);
1469 return -ENOENT;
1470 }
1471
1472 err = grab_mblocks(md);
1473 if (err < 0)
1474 goto out;
1475
1476 err = grab_mlgroups(md);
1477 if (err < 0)
1478 goto out;
1479
1480 count = 0;
1481 mdesc_for_each_node_by_name(md, node, "group") {
1482 err = numa_parse_mdesc_group(md, node, count);
1483 if (err < 0)
1484 break;
1485 count++;
1486 }
1487
1488 count = 0;
1489 mdesc_for_each_node_by_name(md, node, "group") {
1490 find_numa_latencies_for_group(md, node, count);
1491 count++;
1492 }
1493
1494 /* Normalize numa latency matrix according to ACPI SLIT spec. */
1495 for (i = 0; i < MAX_NUMNODES; i++) {
1496 u64 self_latency = numa_latency[i][i];
1497
1498 for (j = 0; j < MAX_NUMNODES; j++) {
1499 numa_latency[i][j] =
1500 (numa_latency[i][j] * LOCAL_DISTANCE) /
1501 self_latency;
1502 }
1503 }
1504
1505 add_node_ranges();
1506
1507 for (i = 0; i < num_node_masks; i++) {
1508 allocate_node_data(i);
1509 node_set_online(i);
1510 }
1511
1512 err = 0;
1513 out:
1514 mdesc_release(md);
1515 return err;
1516 }
1517
1518 static int __init numa_parse_jbus(void)
1519 {
1520 unsigned long cpu, index;
1521
1522 /* NUMA node id is encoded in bits 36 and higher, and there is
1523 * a 1-to-1 mapping from CPU ID to NUMA node ID.
1524 */
1525 index = 0;
1526 for_each_present_cpu(cpu) {
1527 numa_cpu_lookup_table[cpu] = index;
1528 cpumask_copy(&numa_cpumask_lookup_table[index], cpumask_of(cpu));
1529 node_masks[index].mask = ~((1UL << 36UL) - 1UL);
1530 node_masks[index].match = cpu << 36UL;
1531
1532 index++;
1533 }
1534 num_node_masks = index;
1535
1536 add_node_ranges();
1537
1538 for (index = 0; index < num_node_masks; index++) {
1539 allocate_node_data(index);
1540 node_set_online(index);
1541 }
1542
1543 return 0;
1544 }
1545
1546 static int __init numa_parse_sun4u(void)
1547 {
1548 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1549 unsigned long ver;
1550
1551 __asm__ ("rdpr %%ver, %0" : "=r" (ver));
1552 if ((ver >> 32UL) == __JALAPENO_ID ||
1553 (ver >> 32UL) == __SERRANO_ID)
1554 return numa_parse_jbus();
1555 }
1556 return -1;
1557 }
1558
1559 static int __init bootmem_init_numa(void)
1560 {
1561 int i, j;
1562 int err = -1;
1563
1564 numadbg("bootmem_init_numa()\n");
1565
1566 /* Some sane defaults for numa latency values */
1567 for (i = 0; i < MAX_NUMNODES; i++) {
1568 for (j = 0; j < MAX_NUMNODES; j++)
1569 numa_latency[i][j] = (i == j) ?
1570 LOCAL_DISTANCE : REMOTE_DISTANCE;
1571 }
1572
1573 if (numa_enabled) {
1574 if (tlb_type == hypervisor)
1575 err = numa_parse_mdesc();
1576 else
1577 err = numa_parse_sun4u();
1578 }
1579 return err;
1580 }
1581
1582 #else
1583
1584 static int bootmem_init_numa(void)
1585 {
1586 return -1;
1587 }
1588
1589 #endif
1590
1591 static void __init bootmem_init_nonnuma(void)
1592 {
1593 unsigned long top_of_ram = memblock_end_of_DRAM();
1594 unsigned long total_ram = memblock_phys_mem_size();
1595
1596 numadbg("bootmem_init_nonnuma()\n");
1597
1598 printk(KERN_INFO "Top of RAM: 0x%lx, Total RAM: 0x%lx\n",
1599 top_of_ram, total_ram);
1600 printk(KERN_INFO "Memory hole size: %ldMB\n",
1601 (top_of_ram - total_ram) >> 20);
1602
1603 init_node_masks_nonnuma();
1604 memblock_set_node(0, PHYS_ADDR_MAX, &memblock.memory, 0);
1605 allocate_node_data(0);
1606 node_set_online(0);
1607 }
1608
1609 static unsigned long __init bootmem_init(unsigned long phys_base)
1610 {
1611 unsigned long end_pfn;
1612
1613 end_pfn = memblock_end_of_DRAM() >> PAGE_SHIFT;
1614 max_pfn = max_low_pfn = end_pfn;
1615 min_low_pfn = (phys_base >> PAGE_SHIFT);
1616
1617 if (bootmem_init_numa() < 0)
1618 bootmem_init_nonnuma();
1619
1620 /* Dump memblock with node info. */
1621 memblock_dump_all();
1622
1623 /* XXX cpu notifier XXX */
1624
1625 sparse_init();
1626
1627 return end_pfn;
1628 }
1629
1630 static struct linux_prom64_registers pall[MAX_BANKS] __initdata;
1631 static int pall_ents __initdata;
1632
1633 static unsigned long max_phys_bits = 40;
1634
1635 bool kern_addr_valid(unsigned long addr)
1636 {
1637 pgd_t *pgd;
1638 p4d_t *p4d;
1639 pud_t *pud;
1640 pmd_t *pmd;
1641 pte_t *pte;
1642
1643 if ((long)addr < 0L) {
1644 unsigned long pa = __pa(addr);
1645
1646 if ((pa >> max_phys_bits) != 0UL)
1647 return false;
1648
1649 return pfn_valid(pa >> PAGE_SHIFT);
1650 }
1651
1652 if (addr >= (unsigned long) KERNBASE &&
1653 addr < (unsigned long)&_end)
1654 return true;
1655
1656 pgd = pgd_offset_k(addr);
1657 if (pgd_none(*pgd))
1658 return false;
1659
1660 p4d = p4d_offset(pgd, addr);
1661 if (p4d_none(*p4d))
1662 return false;
1663
1664 pud = pud_offset(p4d, addr);
1665 if (pud_none(*pud))
1666 return false;
1667
1668 if (pud_leaf(*pud))
1669 return pfn_valid(pud_pfn(*pud));
1670
1671 pmd = pmd_offset(pud, addr);
1672 if (pmd_none(*pmd))
1673 return false;
1674
1675 if (pmd_leaf(*pmd))
1676 return pfn_valid(pmd_pfn(*pmd));
1677
1678 pte = pte_offset_kernel(pmd, addr);
1679 if (pte_none(*pte))
1680 return false;
1681
1682 return pfn_valid(pte_pfn(*pte));
1683 }
1684
1685 static unsigned long __ref kernel_map_hugepud(unsigned long vstart,
1686 unsigned long vend,
1687 pud_t *pud)
1688 {
1689 const unsigned long mask16gb = (1UL << 34) - 1UL;
1690 u64 pte_val = vstart;
1691
1692 /* Each PUD is 8GB */
1693 if ((vstart & mask16gb) ||
1694 (vend - vstart <= mask16gb)) {
1695 pte_val ^= kern_linear_pte_xor[2];
1696 pud_val(*pud) = pte_val | _PAGE_PUD_HUGE;
1697
1698 return vstart + PUD_SIZE;
1699 }
1700
1701 pte_val ^= kern_linear_pte_xor[3];
1702 pte_val |= _PAGE_PUD_HUGE;
1703
1704 vend = vstart + mask16gb + 1UL;
1705 while (vstart < vend) {
1706 pud_val(*pud) = pte_val;
1707
1708 pte_val += PUD_SIZE;
1709 vstart += PUD_SIZE;
1710 pud++;
1711 }
1712 return vstart;
1713 }
1714
1715 static bool kernel_can_map_hugepud(unsigned long vstart, unsigned long vend,
1716 bool guard)
1717 {
1718 if (guard && !(vstart & ~PUD_MASK) && (vend - vstart) >= PUD_SIZE)
1719 return true;
1720
1721 return false;
1722 }
1723
1724 static unsigned long __ref kernel_map_hugepmd(unsigned long vstart,
1725 unsigned long vend,
1726 pmd_t *pmd)
1727 {
1728 const unsigned long mask256mb = (1UL << 28) - 1UL;
1729 const unsigned long mask2gb = (1UL << 31) - 1UL;
1730 u64 pte_val = vstart;
1731
1732 /* Each PMD is 8MB */
1733 if ((vstart & mask256mb) ||
1734 (vend - vstart <= mask256mb)) {
1735 pte_val ^= kern_linear_pte_xor[0];
1736 pmd_val(*pmd) = pte_val | _PAGE_PMD_HUGE;
1737
1738 return vstart + PMD_SIZE;
1739 }
1740
1741 if ((vstart & mask2gb) ||
1742 (vend - vstart <= mask2gb)) {
1743 pte_val ^= kern_linear_pte_xor[1];
1744 pte_val |= _PAGE_PMD_HUGE;
1745 vend = vstart + mask256mb + 1UL;
1746 } else {
1747 pte_val ^= kern_linear_pte_xor[2];
1748 pte_val |= _PAGE_PMD_HUGE;
1749 vend = vstart + mask2gb + 1UL;
1750 }
1751
1752 while (vstart < vend) {
1753 pmd_val(*pmd) = pte_val;
1754
1755 pte_val += PMD_SIZE;
1756 vstart += PMD_SIZE;
1757 pmd++;
1758 }
1759
1760 return vstart;
1761 }
1762
1763 static bool kernel_can_map_hugepmd(unsigned long vstart, unsigned long vend,
1764 bool guard)
1765 {
1766 if (guard && !(vstart & ~PMD_MASK) && (vend - vstart) >= PMD_SIZE)
1767 return true;
1768
1769 return false;
1770 }
1771
1772 static unsigned long __ref kernel_map_range(unsigned long pstart,
1773 unsigned long pend, pgprot_t prot,
1774 bool use_huge)
1775 {
1776 unsigned long vstart = PAGE_OFFSET + pstart;
1777 unsigned long vend = PAGE_OFFSET + pend;
1778 unsigned long alloc_bytes = 0UL;
1779
1780 if ((vstart & ~PAGE_MASK) || (vend & ~PAGE_MASK)) {
1781 prom_printf("kernel_map: Unaligned physmem[%lx:%lx]\n",
1782 vstart, vend);
1783 prom_halt();
1784 }
1785
1786 while (vstart < vend) {
1787 unsigned long this_end, paddr = __pa(vstart);
1788 pgd_t *pgd = pgd_offset_k(vstart);
1789 p4d_t *p4d;
1790 pud_t *pud;
1791 pmd_t *pmd;
1792 pte_t *pte;
1793
1794 if (pgd_none(*pgd)) {
1795 pud_t *new;
1796
1797 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1798 PAGE_SIZE);
1799 if (!new)
1800 goto err_alloc;
1801 alloc_bytes += PAGE_SIZE;
1802 pgd_populate(&init_mm, pgd, new);
1803 }
1804
1805 p4d = p4d_offset(pgd, vstart);
1806 if (p4d_none(*p4d)) {
1807 pud_t *new;
1808
1809 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1810 PAGE_SIZE);
1811 if (!new)
1812 goto err_alloc;
1813 alloc_bytes += PAGE_SIZE;
1814 p4d_populate(&init_mm, p4d, new);
1815 }
1816
1817 pud = pud_offset(p4d, vstart);
1818 if (pud_none(*pud)) {
1819 pmd_t *new;
1820
1821 if (kernel_can_map_hugepud(vstart, vend, use_huge)) {
1822 vstart = kernel_map_hugepud(vstart, vend, pud);
1823 continue;
1824 }
1825 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1826 PAGE_SIZE);
1827 if (!new)
1828 goto err_alloc;
1829 alloc_bytes += PAGE_SIZE;
1830 pud_populate(&init_mm, pud, new);
1831 }
1832
1833 pmd = pmd_offset(pud, vstart);
1834 if (pmd_none(*pmd)) {
1835 pte_t *new;
1836
1837 if (kernel_can_map_hugepmd(vstart, vend, use_huge)) {
1838 vstart = kernel_map_hugepmd(vstart, vend, pmd);
1839 continue;
1840 }
1841 new = memblock_alloc_from(PAGE_SIZE, PAGE_SIZE,
1842 PAGE_SIZE);
1843 if (!new)
1844 goto err_alloc;
1845 alloc_bytes += PAGE_SIZE;
1846 pmd_populate_kernel(&init_mm, pmd, new);
1847 }
1848
1849 pte = pte_offset_kernel(pmd, vstart);
1850 this_end = (vstart + PMD_SIZE) & PMD_MASK;
1851 if (this_end > vend)
1852 this_end = vend;
1853
1854 while (vstart < this_end) {
1855 pte_val(*pte) = (paddr | pgprot_val(prot));
1856
1857 vstart += PAGE_SIZE;
1858 paddr += PAGE_SIZE;
1859 pte++;
1860 }
1861 }
1862
1863 return alloc_bytes;
1864
1865 err_alloc:
1866 panic("%s: Failed to allocate %lu bytes align=%lx from=%lx\n",
1867 __func__, PAGE_SIZE, PAGE_SIZE, PAGE_SIZE);
1868 return -ENOMEM;
1869 }
1870
1871 static void __init flush_all_kernel_tsbs(void)
1872 {
1873 int i;
1874
1875 for (i = 0; i < KERNEL_TSB_NENTRIES; i++) {
1876 struct tsb *ent = &swapper_tsb[i];
1877
1878 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1879 }
1880 #ifndef CONFIG_DEBUG_PAGEALLOC
1881 for (i = 0; i < KERNEL_TSB4M_NENTRIES; i++) {
1882 struct tsb *ent = &swapper_4m_tsb[i];
1883
1884 ent->tag = (1UL << TSB_TAG_INVALID_BIT);
1885 }
1886 #endif
1887 }
1888
1889 extern unsigned int kvmap_linear_patch[1];
1890
1891 static void __init kernel_physical_mapping_init(void)
1892 {
1893 unsigned long i, mem_alloced = 0UL;
1894 bool use_huge = true;
1895
1896 #ifdef CONFIG_DEBUG_PAGEALLOC
1897 use_huge = false;
1898 #endif
1899 for (i = 0; i < pall_ents; i++) {
1900 unsigned long phys_start, phys_end;
1901
1902 phys_start = pall[i].phys_addr;
1903 phys_end = phys_start + pall[i].reg_size;
1904
1905 mem_alloced += kernel_map_range(phys_start, phys_end,
1906 PAGE_KERNEL, use_huge);
1907 }
1908
1909 printk("Allocated %ld bytes for kernel page tables.\n",
1910 mem_alloced);
1911
1912 kvmap_linear_patch[0] = 0x01000000; /* nop */
1913 flushi(&kvmap_linear_patch[0]);
1914
1915 flush_all_kernel_tsbs();
1916
1917 __flush_tlb_all();
1918 }
1919
1920 #ifdef CONFIG_DEBUG_PAGEALLOC
1921 void __kernel_map_pages(struct page *page, int numpages, int enable)
1922 {
1923 unsigned long phys_start = page_to_pfn(page) << PAGE_SHIFT;
1924 unsigned long phys_end = phys_start + (numpages * PAGE_SIZE);
1925
1926 kernel_map_range(phys_start, phys_end,
1927 (enable ? PAGE_KERNEL : __pgprot(0)), false);
1928
1929 flush_tsb_kernel_range(PAGE_OFFSET + phys_start,
1930 PAGE_OFFSET + phys_end);
1931
1932 /* we should perform an IPI and flush all tlbs,
1933 * but that can deadlock->flush only current cpu.
1934 */
1935 __flush_tlb_kernel_range(PAGE_OFFSET + phys_start,
1936 PAGE_OFFSET + phys_end);
1937 }
1938 #endif
1939
1940 unsigned long __init find_ecache_flush_span(unsigned long size)
1941 {
1942 int i;
1943
1944 for (i = 0; i < pavail_ents; i++) {
1945 if (pavail[i].reg_size >= size)
1946 return pavail[i].phys_addr;
1947 }
1948
1949 return ~0UL;
1950 }
1951
1952 unsigned long PAGE_OFFSET;
1953 EXPORT_SYMBOL(PAGE_OFFSET);
1954
1955 unsigned long VMALLOC_END = 0x0000010000000000UL;
1956 EXPORT_SYMBOL(VMALLOC_END);
1957
1958 unsigned long sparc64_va_hole_top = 0xfffff80000000000UL;
1959 unsigned long sparc64_va_hole_bottom = 0x0000080000000000UL;
1960
1961 static void __init setup_page_offset(void)
1962 {
1963 if (tlb_type == cheetah || tlb_type == cheetah_plus) {
1964 /* Cheetah/Panther support a full 64-bit virtual
1965 * address, so we can use all that our page tables
1966 * support.
1967 */
1968 sparc64_va_hole_top = 0xfff0000000000000UL;
1969 sparc64_va_hole_bottom = 0x0010000000000000UL;
1970
1971 max_phys_bits = 42;
1972 } else if (tlb_type == hypervisor) {
1973 switch (sun4v_chip_type) {
1974 case SUN4V_CHIP_NIAGARA1:
1975 case SUN4V_CHIP_NIAGARA2:
1976 /* T1 and T2 support 48-bit virtual addresses. */
1977 sparc64_va_hole_top = 0xffff800000000000UL;
1978 sparc64_va_hole_bottom = 0x0000800000000000UL;
1979
1980 max_phys_bits = 39;
1981 break;
1982 case SUN4V_CHIP_NIAGARA3:
1983 /* T3 supports 48-bit virtual addresses. */
1984 sparc64_va_hole_top = 0xffff800000000000UL;
1985 sparc64_va_hole_bottom = 0x0000800000000000UL;
1986
1987 max_phys_bits = 43;
1988 break;
1989 case SUN4V_CHIP_NIAGARA4:
1990 case SUN4V_CHIP_NIAGARA5:
1991 case SUN4V_CHIP_SPARC64X:
1992 case SUN4V_CHIP_SPARC_M6:
1993 /* T4 and later support 52-bit virtual addresses. */
1994 sparc64_va_hole_top = 0xfff8000000000000UL;
1995 sparc64_va_hole_bottom = 0x0008000000000000UL;
1996 max_phys_bits = 47;
1997 break;
1998 case SUN4V_CHIP_SPARC_M7:
1999 case SUN4V_CHIP_SPARC_SN:
2000 /* M7 and later support 52-bit virtual addresses. */
2001 sparc64_va_hole_top = 0xfff8000000000000UL;
2002 sparc64_va_hole_bottom = 0x0008000000000000UL;
2003 max_phys_bits = 49;
2004 break;
2005 case SUN4V_CHIP_SPARC_M8:
2006 default:
2007 /* M8 and later support 54-bit virtual addresses.
2008 * However, restricting M8 and above VA bits to 53
2009 * as 4-level page table cannot support more than
2010 * 53 VA bits.
2011 */
2012 sparc64_va_hole_top = 0xfff0000000000000UL;
2013 sparc64_va_hole_bottom = 0x0010000000000000UL;
2014 max_phys_bits = 51;
2015 break;
2016 }
2017 }
2018
2019 if (max_phys_bits > MAX_PHYS_ADDRESS_BITS) {
2020 prom_printf("MAX_PHYS_ADDRESS_BITS is too small, need %lu\n",
2021 max_phys_bits);
2022 prom_halt();
2023 }
2024
2025 PAGE_OFFSET = sparc64_va_hole_top;
2026 VMALLOC_END = ((sparc64_va_hole_bottom >> 1) +
2027 (sparc64_va_hole_bottom >> 2));
2028
2029 pr_info("MM: PAGE_OFFSET is 0x%016lx (max_phys_bits == %lu)\n",
2030 PAGE_OFFSET, max_phys_bits);
2031 pr_info("MM: VMALLOC [0x%016lx --> 0x%016lx]\n",
2032 VMALLOC_START, VMALLOC_END);
2033 pr_info("MM: VMEMMAP [0x%016lx --> 0x%016lx]\n",
2034 VMEMMAP_BASE, VMEMMAP_BASE << 1);
2035 }
2036
2037 static void __init tsb_phys_patch(void)
2038 {
2039 struct tsb_ldquad_phys_patch_entry *pquad;
2040 struct tsb_phys_patch_entry *p;
2041
2042 pquad = &__tsb_ldquad_phys_patch;
2043 while (pquad < &__tsb_ldquad_phys_patch_end) {
2044 unsigned long addr = pquad->addr;
2045
2046 if (tlb_type == hypervisor)
2047 *(unsigned int *) addr = pquad->sun4v_insn;
2048 else
2049 *(unsigned int *) addr = pquad->sun4u_insn;
2050 wmb();
2051 __asm__ __volatile__("flush %0"
2052 : /* no outputs */
2053 : "r" (addr));
2054
2055 pquad++;
2056 }
2057
2058 p = &__tsb_phys_patch;
2059 while (p < &__tsb_phys_patch_end) {
2060 unsigned long addr = p->addr;
2061
2062 *(unsigned int *) addr = p->insn;
2063 wmb();
2064 __asm__ __volatile__("flush %0"
2065 : /* no outputs */
2066 : "r" (addr));
2067
2068 p++;
2069 }
2070 }
2071
2072 /* Don't mark as init, we give this to the Hypervisor. */
2073 #ifndef CONFIG_DEBUG_PAGEALLOC
2074 #define NUM_KTSB_DESCR 2
2075 #else
2076 #define NUM_KTSB_DESCR 1
2077 #endif
2078 static struct hv_tsb_descr ktsb_descr[NUM_KTSB_DESCR];
2079
2080 /* The swapper TSBs are loaded with a base sequence of:
2081 *
2082 * sethi %uhi(SYMBOL), REG1
2083 * sethi %hi(SYMBOL), REG2
2084 * or REG1, %ulo(SYMBOL), REG1
2085 * or REG2, %lo(SYMBOL), REG2
2086 * sllx REG1, 32, REG1
2087 * or REG1, REG2, REG1
2088 *
2089 * When we use physical addressing for the TSB accesses, we patch the
2090 * first four instructions in the above sequence.
2091 */
2092
2093 static void patch_one_ktsb_phys(unsigned int *start, unsigned int *end, unsigned long pa)
2094 {
2095 unsigned long high_bits, low_bits;
2096
2097 high_bits = (pa >> 32) & 0xffffffff;
2098 low_bits = (pa >> 0) & 0xffffffff;
2099
2100 while (start < end) {
2101 unsigned int *ia = (unsigned int *)(unsigned long)*start;
2102
2103 ia[0] = (ia[0] & ~0x3fffff) | (high_bits >> 10);
2104 __asm__ __volatile__("flush %0" : : "r" (ia));
2105
2106 ia[1] = (ia[1] & ~0x3fffff) | (low_bits >> 10);
2107 __asm__ __volatile__("flush %0" : : "r" (ia + 1));
2108
2109 ia[2] = (ia[2] & ~0x1fff) | (high_bits & 0x3ff);
2110 __asm__ __volatile__("flush %0" : : "r" (ia + 2));
2111
2112 ia[3] = (ia[3] & ~0x1fff) | (low_bits & 0x3ff);
2113 __asm__ __volatile__("flush %0" : : "r" (ia + 3));
2114
2115 start++;
2116 }
2117 }
2118
2119 static void ktsb_phys_patch(void)
2120 {
2121 extern unsigned int __swapper_tsb_phys_patch;
2122 extern unsigned int __swapper_tsb_phys_patch_end;
2123 unsigned long ktsb_pa;
2124
2125 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2126 patch_one_ktsb_phys(&__swapper_tsb_phys_patch,
2127 &__swapper_tsb_phys_patch_end, ktsb_pa);
2128 #ifndef CONFIG_DEBUG_PAGEALLOC
2129 {
2130 extern unsigned int __swapper_4m_tsb_phys_patch;
2131 extern unsigned int __swapper_4m_tsb_phys_patch_end;
2132 ktsb_pa = (kern_base +
2133 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2134 patch_one_ktsb_phys(&__swapper_4m_tsb_phys_patch,
2135 &__swapper_4m_tsb_phys_patch_end, ktsb_pa);
2136 }
2137 #endif
2138 }
2139
2140 static void __init sun4v_ktsb_init(void)
2141 {
2142 unsigned long ktsb_pa;
2143
2144 /* First KTSB for PAGE_SIZE mappings. */
2145 ktsb_pa = kern_base + ((unsigned long)&swapper_tsb[0] - KERNBASE);
2146
2147 switch (PAGE_SIZE) {
2148 case 8 * 1024:
2149 default:
2150 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_8K;
2151 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_8K;
2152 break;
2153
2154 case 64 * 1024:
2155 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_64K;
2156 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_64K;
2157 break;
2158
2159 case 512 * 1024:
2160 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_512K;
2161 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_512K;
2162 break;
2163
2164 case 4 * 1024 * 1024:
2165 ktsb_descr[0].pgsz_idx = HV_PGSZ_IDX_4MB;
2166 ktsb_descr[0].pgsz_mask = HV_PGSZ_MASK_4MB;
2167 break;
2168 }
2169
2170 ktsb_descr[0].assoc = 1;
2171 ktsb_descr[0].num_ttes = KERNEL_TSB_NENTRIES;
2172 ktsb_descr[0].ctx_idx = 0;
2173 ktsb_descr[0].tsb_base = ktsb_pa;
2174 ktsb_descr[0].resv = 0;
2175
2176 #ifndef CONFIG_DEBUG_PAGEALLOC
2177 /* Second KTSB for 4MB/256MB/2GB/16GB mappings. */
2178 ktsb_pa = (kern_base +
2179 ((unsigned long)&swapper_4m_tsb[0] - KERNBASE));
2180
2181 ktsb_descr[1].pgsz_idx = HV_PGSZ_IDX_4MB;
2182 ktsb_descr[1].pgsz_mask = ((HV_PGSZ_MASK_4MB |
2183 HV_PGSZ_MASK_256MB |
2184 HV_PGSZ_MASK_2GB |
2185 HV_PGSZ_MASK_16GB) &
2186 cpu_pgsz_mask);
2187 ktsb_descr[1].assoc = 1;
2188 ktsb_descr[1].num_ttes = KERNEL_TSB4M_NENTRIES;
2189 ktsb_descr[1].ctx_idx = 0;
2190 ktsb_descr[1].tsb_base = ktsb_pa;
2191 ktsb_descr[1].resv = 0;
2192 #endif
2193 }
2194
2195 void sun4v_ktsb_register(void)
2196 {
2197 unsigned long pa, ret;
2198
2199 pa = kern_base + ((unsigned long)&ktsb_descr[0] - KERNBASE);
2200
2201 ret = sun4v_mmu_tsb_ctx0(NUM_KTSB_DESCR, pa);
2202 if (ret != 0) {
2203 prom_printf("hypervisor_mmu_tsb_ctx0[%lx]: "
2204 "errors with %lx\n", pa, ret);
2205 prom_halt();
2206 }
2207 }
2208
2209 static void __init sun4u_linear_pte_xor_finalize(void)
2210 {
2211 #ifndef CONFIG_DEBUG_PAGEALLOC
2212 /* This is where we would add Panther support for
2213 * 32MB and 256MB pages.
2214 */
2215 #endif
2216 }
2217
2218 static void __init sun4v_linear_pte_xor_finalize(void)
2219 {
2220 unsigned long pagecv_flag;
2221
2222 /* Bit 9 of TTE is no longer CV bit on M7 processor and it instead
2223 * enables MCD error. Do not set bit 9 on M7 processor.
2224 */
2225 switch (sun4v_chip_type) {
2226 case SUN4V_CHIP_SPARC_M7:
2227 case SUN4V_CHIP_SPARC_M8:
2228 case SUN4V_CHIP_SPARC_SN:
2229 pagecv_flag = 0x00;
2230 break;
2231 default:
2232 pagecv_flag = _PAGE_CV_4V;
2233 break;
2234 }
2235 #ifndef CONFIG_DEBUG_PAGEALLOC
2236 if (cpu_pgsz_mask & HV_PGSZ_MASK_256MB) {
2237 kern_linear_pte_xor[1] = (_PAGE_VALID | _PAGE_SZ256MB_4V) ^
2238 PAGE_OFFSET;
2239 kern_linear_pte_xor[1] |= (_PAGE_CP_4V | pagecv_flag |
2240 _PAGE_P_4V | _PAGE_W_4V);
2241 } else {
2242 kern_linear_pte_xor[1] = kern_linear_pte_xor[0];
2243 }
2244
2245 if (cpu_pgsz_mask & HV_PGSZ_MASK_2GB) {
2246 kern_linear_pte_xor[2] = (_PAGE_VALID | _PAGE_SZ2GB_4V) ^
2247 PAGE_OFFSET;
2248 kern_linear_pte_xor[2] |= (_PAGE_CP_4V | pagecv_flag |
2249 _PAGE_P_4V | _PAGE_W_4V);
2250 } else {
2251 kern_linear_pte_xor[2] = kern_linear_pte_xor[1];
2252 }
2253
2254 if (cpu_pgsz_mask & HV_PGSZ_MASK_16GB) {
2255 kern_linear_pte_xor[3] = (_PAGE_VALID | _PAGE_SZ16GB_4V) ^
2256 PAGE_OFFSET;
2257 kern_linear_pte_xor[3] |= (_PAGE_CP_4V | pagecv_flag |
2258 _PAGE_P_4V | _PAGE_W_4V);
2259 } else {
2260 kern_linear_pte_xor[3] = kern_linear_pte_xor[2];
2261 }
2262 #endif
2263 }
2264
2265 /* paging_init() sets up the page tables */
2266
2267 static unsigned long last_valid_pfn;
2268
2269 static void sun4u_pgprot_init(void);
2270 static void sun4v_pgprot_init(void);
2271
2272 #define _PAGE_CACHE_4U (_PAGE_CP_4U | _PAGE_CV_4U)
2273 #define _PAGE_CACHE_4V (_PAGE_CP_4V | _PAGE_CV_4V)
2274 #define __DIRTY_BITS_4U (_PAGE_MODIFIED_4U | _PAGE_WRITE_4U | _PAGE_W_4U)
2275 #define __DIRTY_BITS_4V (_PAGE_MODIFIED_4V | _PAGE_WRITE_4V | _PAGE_W_4V)
2276 #define __ACCESS_BITS_4U (_PAGE_ACCESSED_4U | _PAGE_READ_4U | _PAGE_R)
2277 #define __ACCESS_BITS_4V (_PAGE_ACCESSED_4V | _PAGE_READ_4V | _PAGE_R)
2278
2279 /* We need to exclude reserved regions. This exclusion will include
2280 * vmlinux and initrd. To be more precise the initrd size could be used to
2281 * compute a new lower limit because it is freed later during initialization.
2282 */
2283 static void __init reduce_memory(phys_addr_t limit_ram)
2284 {
2285 limit_ram += memblock_reserved_size();
2286 memblock_enforce_memory_limit(limit_ram);
2287 }
2288
2289 void __init paging_init(void)
2290 {
2291 unsigned long end_pfn, shift, phys_base;
2292 unsigned long real_end, i;
2293
2294 setup_page_offset();
2295
2296 /* These build time checkes make sure that the dcache_dirty_cpu()
2297 * folio->flags usage will work.
2298 *
2299 * When a page gets marked as dcache-dirty, we store the
2300 * cpu number starting at bit 32 in the folio->flags. Also,
2301 * functions like clear_dcache_dirty_cpu use the cpu mask
2302 * in 13-bit signed-immediate instruction fields.
2303 */
2304
2305 /*
2306 * Page flags must not reach into upper 32 bits that are used
2307 * for the cpu number
2308 */
2309 BUILD_BUG_ON(NR_PAGEFLAGS > 32);
2310
2311 /*
2312 * The bit fields placed in the high range must not reach below
2313 * the 32 bit boundary. Otherwise we cannot place the cpu field
2314 * at the 32 bit boundary.
2315 */
2316 BUILD_BUG_ON(SECTIONS_WIDTH + NODES_WIDTH + ZONES_WIDTH +
2317 ilog2(roundup_pow_of_two(NR_CPUS)) > 32);
2318
2319 BUILD_BUG_ON(NR_CPUS > 4096);
2320
2321 kern_base = (prom_boot_mapping_phys_low >> ILOG2_4MB) << ILOG2_4MB;
2322 kern_size = (unsigned long)&_end - (unsigned long)KERNBASE;
2323
2324 /* Invalidate both kernel TSBs. */
2325 memset(swapper_tsb, 0x40, sizeof(swapper_tsb));
2326 #ifndef CONFIG_DEBUG_PAGEALLOC
2327 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2328 #endif
2329
2330 /* TTE.cv bit on sparc v9 occupies the same position as TTE.mcde
2331 * bit on M7 processor. This is a conflicting usage of the same
2332 * bit. Enabling TTE.cv on M7 would turn on Memory Corruption
2333 * Detection error on all pages and this will lead to problems
2334 * later. Kernel does not run with MCD enabled and hence rest
2335 * of the required steps to fully configure memory corruption
2336 * detection are not taken. We need to ensure TTE.mcde is not
2337 * set on M7 processor. Compute the value of cacheability
2338 * flag for use later taking this into consideration.
2339 */
2340 switch (sun4v_chip_type) {
2341 case SUN4V_CHIP_SPARC_M7:
2342 case SUN4V_CHIP_SPARC_M8:
2343 case SUN4V_CHIP_SPARC_SN:
2344 page_cache4v_flag = _PAGE_CP_4V;
2345 break;
2346 default:
2347 page_cache4v_flag = _PAGE_CACHE_4V;
2348 break;
2349 }
2350
2351 if (tlb_type == hypervisor)
2352 sun4v_pgprot_init();
2353 else
2354 sun4u_pgprot_init();
2355
2356 if (tlb_type == cheetah_plus ||
2357 tlb_type == hypervisor) {
2358 tsb_phys_patch();
2359 ktsb_phys_patch();
2360 }
2361
2362 if (tlb_type == hypervisor)
2363 sun4v_patch_tlb_handlers();
2364
2365 /* Find available physical memory...
2366 *
2367 * Read it twice in order to work around a bug in openfirmware.
2368 * The call to grab this table itself can cause openfirmware to
2369 * allocate memory, which in turn can take away some space from
2370 * the list of available memory. Reading it twice makes sure
2371 * we really do get the final value.
2372 */
2373 read_obp_translations();
2374 read_obp_memory("reg", &pall[0], &pall_ents);
2375 read_obp_memory("available", &pavail[0], &pavail_ents);
2376 read_obp_memory("available", &pavail[0], &pavail_ents);
2377
2378 phys_base = 0xffffffffffffffffUL;
2379 for (i = 0; i < pavail_ents; i++) {
2380 phys_base = min(phys_base, pavail[i].phys_addr);
2381 memblock_add(pavail[i].phys_addr, pavail[i].reg_size);
2382 }
2383
2384 memblock_reserve(kern_base, kern_size);
2385
2386 find_ramdisk(phys_base);
2387
2388 if (cmdline_memory_size)
2389 reduce_memory(cmdline_memory_size);
2390
2391 memblock_allow_resize();
2392 memblock_dump_all();
2393
2394 set_bit(0, mmu_context_bmap);
2395
2396 shift = kern_base + PAGE_OFFSET - ((unsigned long)KERNBASE);
2397
2398 real_end = (unsigned long)_end;
2399 num_kernel_image_mappings = DIV_ROUND_UP(real_end - KERNBASE, 1 << ILOG2_4MB);
2400 printk("Kernel: Using %d locked TLB entries for main kernel image.\n",
2401 num_kernel_image_mappings);
2402
2403 /* Set kernel pgd to upper alias so physical page computations
2404 * work.
2405 */
2406 init_mm.pgd += ((shift) / (sizeof(pgd_t)));
2407
2408 memset(swapper_pg_dir, 0, sizeof(swapper_pg_dir));
2409
2410 inherit_prom_mappings();
2411
2412 /* Ok, we can use our TLB miss and window trap handlers safely. */
2413 setup_tba();
2414
2415 __flush_tlb_all();
2416
2417 prom_build_devicetree();
2418 of_populate_present_mask();
2419 #ifndef CONFIG_SMP
2420 of_fill_in_cpu_data();
2421 #endif
2422
2423 if (tlb_type == hypervisor) {
2424 sun4v_mdesc_init();
2425 mdesc_populate_present_mask(cpu_all_mask);
2426 #ifndef CONFIG_SMP
2427 mdesc_fill_in_cpu_data(cpu_all_mask);
2428 #endif
2429 mdesc_get_page_sizes(cpu_all_mask, &cpu_pgsz_mask);
2430
2431 sun4v_linear_pte_xor_finalize();
2432
2433 sun4v_ktsb_init();
2434 sun4v_ktsb_register();
2435 } else {
2436 unsigned long impl, ver;
2437
2438 cpu_pgsz_mask = (HV_PGSZ_MASK_8K | HV_PGSZ_MASK_64K |
2439 HV_PGSZ_MASK_512K | HV_PGSZ_MASK_4MB);
2440
2441 __asm__ __volatile__("rdpr %%ver, %0" : "=r" (ver));
2442 impl = ((ver >> 32) & 0xffff);
2443 if (impl == PANTHER_IMPL)
2444 cpu_pgsz_mask |= (HV_PGSZ_MASK_32MB |
2445 HV_PGSZ_MASK_256MB);
2446
2447 sun4u_linear_pte_xor_finalize();
2448 }
2449
2450 /* Flush the TLBs and the 4M TSB so that the updated linear
2451 * pte XOR settings are realized for all mappings.
2452 */
2453 __flush_tlb_all();
2454 #ifndef CONFIG_DEBUG_PAGEALLOC
2455 memset(swapper_4m_tsb, 0x40, sizeof(swapper_4m_tsb));
2456 #endif
2457 __flush_tlb_all();
2458
2459 /* Setup bootmem... */
2460 last_valid_pfn = end_pfn = bootmem_init(phys_base);
2461
2462 kernel_physical_mapping_init();
2463
2464 {
2465 unsigned long max_zone_pfns[MAX_NR_ZONES];
2466
2467 memset(max_zone_pfns, 0, sizeof(max_zone_pfns));
2468
2469 max_zone_pfns[ZONE_NORMAL] = end_pfn;
2470
2471 free_area_init(max_zone_pfns);
2472 }
2473
2474 printk("Booting Linux...\n");
2475 }
2476
2477 int page_in_phys_avail(unsigned long paddr)
2478 {
2479 int i;
2480
2481 paddr &= PAGE_MASK;
2482
2483 for (i = 0; i < pavail_ents; i++) {
2484 unsigned long start, end;
2485
2486 start = pavail[i].phys_addr;
2487 end = start + pavail[i].reg_size;
2488
2489 if (paddr >= start && paddr < end)
2490 return 1;
2491 }
2492 if (paddr >= kern_base && paddr < (kern_base + kern_size))
2493 return 1;
2494 #ifdef CONFIG_BLK_DEV_INITRD
2495 if (paddr >= __pa(initrd_start) &&
2496 paddr < __pa(PAGE_ALIGN(initrd_end)))
2497 return 1;
2498 #endif
2499
2500 return 0;
2501 }
2502
2503 static void __init register_page_bootmem_info(void)
2504 {
2505 #ifdef CONFIG_NUMA
2506 int i;
2507
2508 for_each_online_node(i)
2509 if (NODE_DATA(i)->node_spanned_pages)
2510 register_page_bootmem_info_node(NODE_DATA(i));
2511 #endif
2512 }
2513 void __init mem_init(void)
2514 {
2515 high_memory = __va(last_valid_pfn << PAGE_SHIFT);
2516
2517 memblock_free_all();
2518
2519 /*
2520 * Must be done after boot memory is put on freelist, because here we
2521 * might set fields in deferred struct pages that have not yet been
2522 * initialized, and memblock_free_all() initializes all the reserved
2523 * deferred pages for us.
2524 */
2525 register_page_bootmem_info();
2526
2527 /*
2528 * Set up the zero page, mark it reserved, so that page count
2529 * is not manipulated when freeing the page from user ptes.
2530 */
2531 mem_map_zero = alloc_pages(GFP_KERNEL|__GFP_ZERO, 0);
2532 if (mem_map_zero == NULL) {
2533 prom_printf("paging_init: Cannot alloc zero page.\n");
2534 prom_halt();
2535 }
2536 mark_page_reserved(mem_map_zero);
2537
2538
2539 if (tlb_type == cheetah || tlb_type == cheetah_plus)
2540 cheetah_ecache_flush_init();
2541 }
2542
2543 void free_initmem(void)
2544 {
2545 unsigned long addr, initend;
2546 int do_free = 1;
2547
2548 /* If the physical memory maps were trimmed by kernel command
2549 * line options, don't even try freeing this initmem stuff up.
2550 * The kernel image could have been in the trimmed out region
2551 * and if so the freeing below will free invalid page structs.
2552 */
2553 if (cmdline_memory_size)
2554 do_free = 0;
2555
2556 /*
2557 * The init section is aligned to 8k in vmlinux.lds. Page align for >8k pagesizes.
2558 */
2559 addr = PAGE_ALIGN((unsigned long)(__init_begin));
2560 initend = (unsigned long)(__init_end) & PAGE_MASK;
2561 for (; addr < initend; addr += PAGE_SIZE) {
2562 unsigned long page;
2563
2564 page = (addr +
2565 ((unsigned long) __va(kern_base)) -
2566 ((unsigned long) KERNBASE));
2567 memset((void *)addr, POISON_FREE_INITMEM, PAGE_SIZE);
2568
2569 if (do_free)
2570 free_reserved_page(virt_to_page(page));
2571 }
2572 }
2573
2574 pgprot_t PAGE_KERNEL __read_mostly;
2575 EXPORT_SYMBOL(PAGE_KERNEL);
2576
2577 pgprot_t PAGE_KERNEL_LOCKED __read_mostly;
2578 pgprot_t PAGE_COPY __read_mostly;
2579
2580 pgprot_t PAGE_SHARED __read_mostly;
2581 EXPORT_SYMBOL(PAGE_SHARED);
2582
2583 unsigned long pg_iobits __read_mostly;
2584
2585 unsigned long _PAGE_IE __read_mostly;
2586 EXPORT_SYMBOL(_PAGE_IE);
2587
2588 unsigned long _PAGE_E __read_mostly;
2589 EXPORT_SYMBOL(_PAGE_E);
2590
2591 unsigned long _PAGE_CACHE __read_mostly;
2592 EXPORT_SYMBOL(_PAGE_CACHE);
2593
2594 #ifdef CONFIG_SPARSEMEM_VMEMMAP
2595 int __meminit vmemmap_populate(unsigned long vstart, unsigned long vend,
2596 int node, struct vmem_altmap *altmap)
2597 {
2598 unsigned long pte_base;
2599
2600 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2601 _PAGE_CP_4U | _PAGE_CV_4U |
2602 _PAGE_P_4U | _PAGE_W_4U);
2603 if (tlb_type == hypervisor)
2604 pte_base = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2605 page_cache4v_flag | _PAGE_P_4V | _PAGE_W_4V);
2606
2607 pte_base |= _PAGE_PMD_HUGE;
2608
2609 vstart = vstart & PMD_MASK;
2610 vend = ALIGN(vend, PMD_SIZE);
2611 for (; vstart < vend; vstart += PMD_SIZE) {
2612 pgd_t *pgd = vmemmap_pgd_populate(vstart, node);
2613 unsigned long pte;
2614 p4d_t *p4d;
2615 pud_t *pud;
2616 pmd_t *pmd;
2617
2618 if (!pgd)
2619 return -ENOMEM;
2620
2621 p4d = vmemmap_p4d_populate(pgd, vstart, node);
2622 if (!p4d)
2623 return -ENOMEM;
2624
2625 pud = vmemmap_pud_populate(p4d, vstart, node);
2626 if (!pud)
2627 return -ENOMEM;
2628
2629 pmd = pmd_offset(pud, vstart);
2630 pte = pmd_val(*pmd);
2631 if (!(pte & _PAGE_VALID)) {
2632 void *block = vmemmap_alloc_block(PMD_SIZE, node);
2633
2634 if (!block)
2635 return -ENOMEM;
2636
2637 pmd_val(*pmd) = pte_base | __pa(block);
2638 }
2639 }
2640
2641 return 0;
2642 }
2643 #endif /* CONFIG_SPARSEMEM_VMEMMAP */
2644
2645 /* These are actually filled in at boot time by sun4{u,v}_pgprot_init() */
2646 static pgprot_t protection_map[16] __ro_after_init;
2647
2648 static void prot_init_common(unsigned long page_none,
2649 unsigned long page_shared,
2650 unsigned long page_copy,
2651 unsigned long page_readonly,
2652 unsigned long page_exec_bit)
2653 {
2654 PAGE_COPY = __pgprot(page_copy);
2655 PAGE_SHARED = __pgprot(page_shared);
2656
2657 protection_map[0x0] = __pgprot(page_none);
2658 protection_map[0x1] = __pgprot(page_readonly & ~page_exec_bit);
2659 protection_map[0x2] = __pgprot(page_copy & ~page_exec_bit);
2660 protection_map[0x3] = __pgprot(page_copy & ~page_exec_bit);
2661 protection_map[0x4] = __pgprot(page_readonly);
2662 protection_map[0x5] = __pgprot(page_readonly);
2663 protection_map[0x6] = __pgprot(page_copy);
2664 protection_map[0x7] = __pgprot(page_copy);
2665 protection_map[0x8] = __pgprot(page_none);
2666 protection_map[0x9] = __pgprot(page_readonly & ~page_exec_bit);
2667 protection_map[0xa] = __pgprot(page_shared & ~page_exec_bit);
2668 protection_map[0xb] = __pgprot(page_shared & ~page_exec_bit);
2669 protection_map[0xc] = __pgprot(page_readonly);
2670 protection_map[0xd] = __pgprot(page_readonly);
2671 protection_map[0xe] = __pgprot(page_shared);
2672 protection_map[0xf] = __pgprot(page_shared);
2673 }
2674
2675 static void __init sun4u_pgprot_init(void)
2676 {
2677 unsigned long page_none, page_shared, page_copy, page_readonly;
2678 unsigned long page_exec_bit;
2679 int i;
2680
2681 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2682 _PAGE_CACHE_4U | _PAGE_P_4U |
2683 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2684 _PAGE_EXEC_4U);
2685 PAGE_KERNEL_LOCKED = __pgprot (_PAGE_PRESENT_4U | _PAGE_VALID |
2686 _PAGE_CACHE_4U | _PAGE_P_4U |
2687 __ACCESS_BITS_4U | __DIRTY_BITS_4U |
2688 _PAGE_EXEC_4U | _PAGE_L_4U);
2689
2690 _PAGE_IE = _PAGE_IE_4U;
2691 _PAGE_E = _PAGE_E_4U;
2692 _PAGE_CACHE = _PAGE_CACHE_4U;
2693
2694 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4U | __DIRTY_BITS_4U |
2695 __ACCESS_BITS_4U | _PAGE_E_4U);
2696
2697 #ifdef CONFIG_DEBUG_PAGEALLOC
2698 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2699 #else
2700 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4U) ^
2701 PAGE_OFFSET;
2702 #endif
2703 kern_linear_pte_xor[0] |= (_PAGE_CP_4U | _PAGE_CV_4U |
2704 _PAGE_P_4U | _PAGE_W_4U);
2705
2706 for (i = 1; i < 4; i++)
2707 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2708
2709 _PAGE_ALL_SZ_BITS = (_PAGE_SZ4MB_4U | _PAGE_SZ512K_4U |
2710 _PAGE_SZ64K_4U | _PAGE_SZ8K_4U |
2711 _PAGE_SZ32MB_4U | _PAGE_SZ256MB_4U);
2712
2713
2714 page_none = _PAGE_PRESENT_4U | _PAGE_ACCESSED_4U | _PAGE_CACHE_4U;
2715 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2716 __ACCESS_BITS_4U | _PAGE_WRITE_4U | _PAGE_EXEC_4U);
2717 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2718 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2719 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4U | _PAGE_CACHE_4U |
2720 __ACCESS_BITS_4U | _PAGE_EXEC_4U);
2721
2722 page_exec_bit = _PAGE_EXEC_4U;
2723
2724 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2725 page_exec_bit);
2726 }
2727
2728 static void __init sun4v_pgprot_init(void)
2729 {
2730 unsigned long page_none, page_shared, page_copy, page_readonly;
2731 unsigned long page_exec_bit;
2732 int i;
2733
2734 PAGE_KERNEL = __pgprot (_PAGE_PRESENT_4V | _PAGE_VALID |
2735 page_cache4v_flag | _PAGE_P_4V |
2736 __ACCESS_BITS_4V | __DIRTY_BITS_4V |
2737 _PAGE_EXEC_4V);
2738 PAGE_KERNEL_LOCKED = PAGE_KERNEL;
2739
2740 _PAGE_IE = _PAGE_IE_4V;
2741 _PAGE_E = _PAGE_E_4V;
2742 _PAGE_CACHE = page_cache4v_flag;
2743
2744 #ifdef CONFIG_DEBUG_PAGEALLOC
2745 kern_linear_pte_xor[0] = _PAGE_VALID ^ PAGE_OFFSET;
2746 #else
2747 kern_linear_pte_xor[0] = (_PAGE_VALID | _PAGE_SZ4MB_4V) ^
2748 PAGE_OFFSET;
2749 #endif
2750 kern_linear_pte_xor[0] |= (page_cache4v_flag | _PAGE_P_4V |
2751 _PAGE_W_4V);
2752
2753 for (i = 1; i < 4; i++)
2754 kern_linear_pte_xor[i] = kern_linear_pte_xor[0];
2755
2756 pg_iobits = (_PAGE_VALID | _PAGE_PRESENT_4V | __DIRTY_BITS_4V |
2757 __ACCESS_BITS_4V | _PAGE_E_4V);
2758
2759 _PAGE_ALL_SZ_BITS = (_PAGE_SZ16GB_4V | _PAGE_SZ2GB_4V |
2760 _PAGE_SZ256MB_4V | _PAGE_SZ32MB_4V |
2761 _PAGE_SZ4MB_4V | _PAGE_SZ512K_4V |
2762 _PAGE_SZ64K_4V | _PAGE_SZ8K_4V);
2763
2764 page_none = _PAGE_PRESENT_4V | _PAGE_ACCESSED_4V | page_cache4v_flag;
2765 page_shared = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2766 __ACCESS_BITS_4V | _PAGE_WRITE_4V | _PAGE_EXEC_4V);
2767 page_copy = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2768 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2769 page_readonly = (_PAGE_VALID | _PAGE_PRESENT_4V | page_cache4v_flag |
2770 __ACCESS_BITS_4V | _PAGE_EXEC_4V);
2771
2772 page_exec_bit = _PAGE_EXEC_4V;
2773
2774 prot_init_common(page_none, page_shared, page_copy, page_readonly,
2775 page_exec_bit);
2776 }
2777
2778 unsigned long pte_sz_bits(unsigned long sz)
2779 {
2780 if (tlb_type == hypervisor) {
2781 switch (sz) {
2782 case 8 * 1024:
2783 default:
2784 return _PAGE_SZ8K_4V;
2785 case 64 * 1024:
2786 return _PAGE_SZ64K_4V;
2787 case 512 * 1024:
2788 return _PAGE_SZ512K_4V;
2789 case 4 * 1024 * 1024:
2790 return _PAGE_SZ4MB_4V;
2791 }
2792 } else {
2793 switch (sz) {
2794 case 8 * 1024:
2795 default:
2796 return _PAGE_SZ8K_4U;
2797 case 64 * 1024:
2798 return _PAGE_SZ64K_4U;
2799 case 512 * 1024:
2800 return _PAGE_SZ512K_4U;
2801 case 4 * 1024 * 1024:
2802 return _PAGE_SZ4MB_4U;
2803 }
2804 }
2805 }
2806
2807 pte_t mk_pte_io(unsigned long page, pgprot_t prot, int space, unsigned long page_size)
2808 {
2809 pte_t pte;
2810
2811 pte_val(pte) = page | pgprot_val(pgprot_noncached(prot));
2812 pte_val(pte) |= (((unsigned long)space) << 32);
2813 pte_val(pte) |= pte_sz_bits(page_size);
2814
2815 return pte;
2816 }
2817
2818 static unsigned long kern_large_tte(unsigned long paddr)
2819 {
2820 unsigned long val;
2821
2822 val = (_PAGE_VALID | _PAGE_SZ4MB_4U |
2823 _PAGE_CP_4U | _PAGE_CV_4U | _PAGE_P_4U |
2824 _PAGE_EXEC_4U | _PAGE_L_4U | _PAGE_W_4U);
2825 if (tlb_type == hypervisor)
2826 val = (_PAGE_VALID | _PAGE_SZ4MB_4V |
2827 page_cache4v_flag | _PAGE_P_4V |
2828 _PAGE_EXEC_4V | _PAGE_W_4V);
2829
2830 return val | paddr;
2831 }
2832
2833 /* If not locked, zap it. */
2834 void __flush_tlb_all(void)
2835 {
2836 unsigned long pstate;
2837 int i;
2838
2839 __asm__ __volatile__("flushw\n\t"
2840 "rdpr %%pstate, %0\n\t"
2841 "wrpr %0, %1, %%pstate"
2842 : "=r" (pstate)
2843 : "i" (PSTATE_IE));
2844 if (tlb_type == hypervisor) {
2845 sun4v_mmu_demap_all();
2846 } else if (tlb_type == spitfire) {
2847 for (i = 0; i < 64; i++) {
2848 /* Spitfire Errata #32 workaround */
2849 /* NOTE: Always runs on spitfire, so no
2850 * cheetah+ page size encodings.
2851 */
2852 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2853 "flush %%g6"
2854 : /* No outputs */
2855 : "r" (0),
2856 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2857
2858 if (!(spitfire_get_dtlb_data(i) & _PAGE_L_4U)) {
2859 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2860 "membar #Sync"
2861 : /* no outputs */
2862 : "r" (TLB_TAG_ACCESS), "i" (ASI_DMMU));
2863 spitfire_put_dtlb_data(i, 0x0UL);
2864 }
2865
2866 /* Spitfire Errata #32 workaround */
2867 /* NOTE: Always runs on spitfire, so no
2868 * cheetah+ page size encodings.
2869 */
2870 __asm__ __volatile__("stxa %0, [%1] %2\n\t"
2871 "flush %%g6"
2872 : /* No outputs */
2873 : "r" (0),
2874 "r" (PRIMARY_CONTEXT), "i" (ASI_DMMU));
2875
2876 if (!(spitfire_get_itlb_data(i) & _PAGE_L_4U)) {
2877 __asm__ __volatile__("stxa %%g0, [%0] %1\n\t"
2878 "membar #Sync"
2879 : /* no outputs */
2880 : "r" (TLB_TAG_ACCESS), "i" (ASI_IMMU));
2881 spitfire_put_itlb_data(i, 0x0UL);
2882 }
2883 }
2884 } else if (tlb_type == cheetah || tlb_type == cheetah_plus) {
2885 cheetah_flush_dtlb_all();
2886 cheetah_flush_itlb_all();
2887 }
2888 __asm__ __volatile__("wrpr %0, 0, %%pstate"
2889 : : "r" (pstate));
2890 }
2891
2892 pte_t *pte_alloc_one_kernel(struct mm_struct *mm)
2893 {
2894 struct page *page = alloc_page(GFP_KERNEL | __GFP_ZERO);
2895 pte_t *pte = NULL;
2896
2897 if (page)
2898 pte = (pte_t *) page_address(page);
2899
2900 return pte;
2901 }
2902
2903 pgtable_t pte_alloc_one(struct mm_struct *mm)
2904 {
2905 struct ptdesc *ptdesc = pagetable_alloc(GFP_KERNEL | __GFP_ZERO, 0);
2906
2907 if (!ptdesc)
2908 return NULL;
2909 if (!pagetable_pte_ctor(ptdesc)) {
2910 pagetable_free(ptdesc);
2911 return NULL;
2912 }
2913 return ptdesc_address(ptdesc);
2914 }
2915
2916 void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
2917 {
2918 free_page((unsigned long)pte);
2919 }
2920
2921 static void __pte_free(pgtable_t pte)
2922 {
2923 struct ptdesc *ptdesc = virt_to_ptdesc(pte);
2924
2925 pagetable_pte_dtor(ptdesc);
2926 pagetable_free(ptdesc);
2927 }
2928
2929 void pte_free(struct mm_struct *mm, pgtable_t pte)
2930 {
2931 __pte_free(pte);
2932 }
2933
2934 void pgtable_free(void *table, bool is_page)
2935 {
2936 if (is_page)
2937 __pte_free(table);
2938 else
2939 kmem_cache_free(pgtable_cache, table);
2940 }
2941
2942 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
2943 static void pte_free_now(struct rcu_head *head)
2944 {
2945 struct page *page;
2946
2947 page = container_of(head, struct page, rcu_head);
2948 __pte_free((pgtable_t)page_address(page));
2949 }
2950
2951 void pte_free_defer(struct mm_struct *mm, pgtable_t pgtable)
2952 {
2953 struct page *page;
2954
2955 page = virt_to_page(pgtable);
2956 call_rcu(&page->rcu_head, pte_free_now);
2957 }
2958
2959 void update_mmu_cache_pmd(struct vm_area_struct *vma, unsigned long addr,
2960 pmd_t *pmd)
2961 {
2962 unsigned long pte, flags;
2963 struct mm_struct *mm;
2964 pmd_t entry = *pmd;
2965
2966 if (!pmd_leaf(entry) || !pmd_young(entry))
2967 return;
2968
2969 pte = pmd_val(entry);
2970
2971 /* Don't insert a non-valid PMD into the TSB, we'll deadlock. */
2972 if (!(pte & _PAGE_VALID))
2973 return;
2974
2975 /* We are fabricating 8MB pages using 4MB real hw pages. */
2976 pte |= (addr & (1UL << REAL_HPAGE_SHIFT));
2977
2978 mm = vma->vm_mm;
2979
2980 spin_lock_irqsave(&mm->context.lock, flags);
2981
2982 if (mm->context.tsb_block[MM_TSB_HUGE].tsb != NULL)
2983 __update_mmu_tsb_insert(mm, MM_TSB_HUGE, REAL_HPAGE_SHIFT,
2984 addr, pte);
2985
2986 spin_unlock_irqrestore(&mm->context.lock, flags);
2987 }
2988 #endif /* CONFIG_TRANSPARENT_HUGEPAGE */
2989
2990 #if defined(CONFIG_HUGETLB_PAGE) || defined(CONFIG_TRANSPARENT_HUGEPAGE)
2991 static void context_reload(void *__data)
2992 {
2993 struct mm_struct *mm = __data;
2994
2995 if (mm == current->mm)
2996 load_secondary_context(mm);
2997 }
2998
2999 void hugetlb_setup(struct pt_regs *regs)
3000 {
3001 struct mm_struct *mm = current->mm;
3002 struct tsb_config *tp;
3003
3004 if (faulthandler_disabled() || !mm) {
3005 const struct exception_table_entry *entry;
3006
3007 entry = search_exception_tables(regs->tpc);
3008 if (entry) {
3009 regs->tpc = entry->fixup;
3010 regs->tnpc = regs->tpc + 4;
3011 return;
3012 }
3013 pr_alert("Unexpected HugeTLB setup in atomic context.\n");
3014 die_if_kernel("HugeTSB in atomic", regs);
3015 }
3016
3017 tp = &mm->context.tsb_block[MM_TSB_HUGE];
3018 if (likely(tp->tsb == NULL))
3019 tsb_grow(mm, MM_TSB_HUGE, 0);
3020
3021 tsb_context_switch(mm);
3022 smp_tsb_sync(mm);
3023
3024 /* On UltraSPARC-III+ and later, configure the second half of
3025 * the Data-TLB for huge pages.
3026 */
3027 if (tlb_type == cheetah_plus) {
3028 bool need_context_reload = false;
3029 unsigned long ctx;
3030
3031 spin_lock_irq(&ctx_alloc_lock);
3032 ctx = mm->context.sparc64_ctx_val;
3033 ctx &= ~CTX_PGSZ_MASK;
3034 ctx |= CTX_PGSZ_BASE << CTX_PGSZ0_SHIFT;
3035 ctx |= CTX_PGSZ_HUGE << CTX_PGSZ1_SHIFT;
3036
3037 if (ctx != mm->context.sparc64_ctx_val) {
3038 /* When changing the page size fields, we
3039 * must perform a context flush so that no
3040 * stale entries match. This flush must
3041 * occur with the original context register
3042 * settings.
3043 */
3044 do_flush_tlb_mm(mm);
3045
3046 /* Reload the context register of all processors
3047 * also executing in this address space.
3048 */
3049 mm->context.sparc64_ctx_val = ctx;
3050 need_context_reload = true;
3051 }
3052 spin_unlock_irq(&ctx_alloc_lock);
3053
3054 if (need_context_reload)
3055 on_each_cpu(context_reload, mm, 0);
3056 }
3057 }
3058 #endif
3059
3060 static struct resource code_resource = {
3061 .name = "Kernel code",
3062 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3063 };
3064
3065 static struct resource data_resource = {
3066 .name = "Kernel data",
3067 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3068 };
3069
3070 static struct resource bss_resource = {
3071 .name = "Kernel bss",
3072 .flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM
3073 };
3074
3075 static inline resource_size_t compute_kern_paddr(void *addr)
3076 {
3077 return (resource_size_t) (addr - KERNBASE + kern_base);
3078 }
3079
3080 static void __init kernel_lds_init(void)
3081 {
3082 code_resource.start = compute_kern_paddr(_text);
3083 code_resource.end = compute_kern_paddr(_etext - 1);
3084 data_resource.start = compute_kern_paddr(_etext);
3085 data_resource.end = compute_kern_paddr(_edata - 1);
3086 bss_resource.start = compute_kern_paddr(__bss_start);
3087 bss_resource.end = compute_kern_paddr(_end - 1);
3088 }
3089
3090 static int __init report_memory(void)
3091 {
3092 int i;
3093 struct resource *res;
3094
3095 kernel_lds_init();
3096
3097 for (i = 0; i < pavail_ents; i++) {
3098 res = kzalloc(sizeof(struct resource), GFP_KERNEL);
3099
3100 if (!res) {
3101 pr_warn("Failed to allocate source.\n");
3102 break;
3103 }
3104
3105 res->name = "System RAM";
3106 res->start = pavail[i].phys_addr;
3107 res->end = pavail[i].phys_addr + pavail[i].reg_size - 1;
3108 res->flags = IORESOURCE_BUSY | IORESOURCE_SYSTEM_RAM;
3109
3110 if (insert_resource(&iomem_resource, res) < 0) {
3111 pr_warn("Resource insertion failed.\n");
3112 break;
3113 }
3114
3115 insert_resource(res, &code_resource);
3116 insert_resource(res, &data_resource);
3117 insert_resource(res, &bss_resource);
3118 }
3119
3120 return 0;
3121 }
3122 arch_initcall(report_memory);
3123
3124 #ifdef CONFIG_SMP
3125 #define do_flush_tlb_kernel_range smp_flush_tlb_kernel_range
3126 #else
3127 #define do_flush_tlb_kernel_range __flush_tlb_kernel_range
3128 #endif
3129
3130 void flush_tlb_kernel_range(unsigned long start, unsigned long end)
3131 {
3132 if (start < HI_OBP_ADDRESS && end > LOW_OBP_ADDRESS) {
3133 if (start < LOW_OBP_ADDRESS) {
3134 flush_tsb_kernel_range(start, LOW_OBP_ADDRESS);
3135 do_flush_tlb_kernel_range(start, LOW_OBP_ADDRESS);
3136 }
3137 if (end > HI_OBP_ADDRESS) {
3138 flush_tsb_kernel_range(HI_OBP_ADDRESS, end);
3139 do_flush_tlb_kernel_range(HI_OBP_ADDRESS, end);
3140 }
3141 } else {
3142 flush_tsb_kernel_range(start, end);
3143 do_flush_tlb_kernel_range(start, end);
3144 }
3145 }
3146
3147 void copy_user_highpage(struct page *to, struct page *from,
3148 unsigned long vaddr, struct vm_area_struct *vma)
3149 {
3150 char *vfrom, *vto;
3151
3152 vfrom = kmap_atomic(from);
3153 vto = kmap_atomic(to);
3154 copy_user_page(vto, vfrom, vaddr, to);
3155 kunmap_atomic(vto);
3156 kunmap_atomic(vfrom);
3157
3158 /* If this page has ADI enabled, copy over any ADI tags
3159 * as well
3160 */
3161 if (vma->vm_flags & VM_SPARC_ADI) {
3162 unsigned long pfrom, pto, i, adi_tag;
3163
3164 pfrom = page_to_phys(from);
3165 pto = page_to_phys(to);
3166
3167 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3168 asm volatile("ldxa [%1] %2, %0\n\t"
3169 : "=r" (adi_tag)
3170 : "r" (i), "i" (ASI_MCD_REAL));
3171 asm volatile("stxa %0, [%1] %2\n\t"
3172 :
3173 : "r" (adi_tag), "r" (pto),
3174 "i" (ASI_MCD_REAL));
3175 pto += adi_blksize();
3176 }
3177 asm volatile("membar #Sync\n\t");
3178 }
3179 }
3180 EXPORT_SYMBOL(copy_user_highpage);
3181
3182 void copy_highpage(struct page *to, struct page *from)
3183 {
3184 char *vfrom, *vto;
3185
3186 vfrom = kmap_atomic(from);
3187 vto = kmap_atomic(to);
3188 copy_page(vto, vfrom);
3189 kunmap_atomic(vto);
3190 kunmap_atomic(vfrom);
3191
3192 /* If this platform is ADI enabled, copy any ADI tags
3193 * as well
3194 */
3195 if (adi_capable()) {
3196 unsigned long pfrom, pto, i, adi_tag;
3197
3198 pfrom = page_to_phys(from);
3199 pto = page_to_phys(to);
3200
3201 for (i = pfrom; i < (pfrom + PAGE_SIZE); i += adi_blksize()) {
3202 asm volatile("ldxa [%1] %2, %0\n\t"
3203 : "=r" (adi_tag)
3204 : "r" (i), "i" (ASI_MCD_REAL));
3205 asm volatile("stxa %0, [%1] %2\n\t"
3206 :
3207 : "r" (adi_tag), "r" (pto),
3208 "i" (ASI_MCD_REAL));
3209 pto += adi_blksize();
3210 }
3211 asm volatile("membar #Sync\n\t");
3212 }
3213 }
3214 EXPORT_SYMBOL(copy_highpage);
3215
3216 pgprot_t vm_get_page_prot(unsigned long vm_flags)
3217 {
3218 unsigned long prot = pgprot_val(protection_map[vm_flags &
3219 (VM_READ|VM_WRITE|VM_EXEC|VM_SHARED)]);
3220
3221 if (vm_flags & VM_SPARC_ADI)
3222 prot |= _PAGE_MCD_4V;
3223
3224 return __pgprot(prot);
3225 }
3226 EXPORT_SYMBOL(vm_get_page_prot);
3227
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