1 ########################################################################
2 # Implement fast SHA-512 with SSSE3 instructions. (x86_64)
3 #
4 # Copyright (C) 2013 Intel Corporation.
5 #
6 # Authors:
7 # James Guilford <james.guilford@intel.com>
8 # Kirk Yap <kirk.s.yap@intel.com>
9 # David Cote <david.m.cote@intel.com>
10 # Tim Chen <tim.c.chen@linux.intel.com>
11 #
12 # This software is available to you under a choice of one of two
13 # licenses. You may choose to be licensed under the terms of the GNU
14 # General Public License (GPL) Version 2, available from the file
15 # COPYING in the main directory of this source tree, or the
16 # OpenIB.org BSD license below:
17 #
18 # Redistribution and use in source and binary forms, with or
19 # without modification, are permitted provided that the following
20 # conditions are met:
21 #
22 # - Redistributions of source code must retain the above
23 # copyright notice, this list of conditions and the following
24 # disclaimer.
25 #
26 # - Redistributions in binary form must reproduce the above
27 # copyright notice, this list of conditions and the following
28 # disclaimer in the documentation and/or other materials
29 # provided with the distribution.
30 #
31 # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
32 # EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
33 # MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
34 # NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
35 # BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
36 # ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
37 # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
38 # SOFTWARE.
39 #
40 ########################################################################
41 #
42 # This code is described in an Intel White-Paper:
43 # "Fast SHA-512 Implementations on Intel Architecture Processors"
44 #
45 # To find it, surf to http://www.intel.com/p/en_US/embedded
46 # and search for that title.
47 #
48 ########################################################################
49
50 #include <linux/linkage.h>
51 #include <linux/cfi_types.h>
52
53 .text
54
55 # Virtual Registers
56 # ARG1
57 digest = %rdi
58 # ARG2
59 msg = %rsi
60 # ARG3
61 msglen = %rdx
62 T1 = %rcx
63 T2 = %r8
64 a_64 = %r9
65 b_64 = %r10
66 c_64 = %r11
67 d_64 = %r12
68 e_64 = %r13
69 f_64 = %r14
70 g_64 = %r15
71 h_64 = %rbx
72 tmp0 = %rax
73
74 # Local variables (stack frame)
75
76 W_SIZE = 80*8
77 WK_SIZE = 2*8
78
79 frame_W = 0
80 frame_WK = frame_W + W_SIZE
81 frame_size = frame_WK + WK_SIZE
82
83 # Useful QWORD "arrays" for simpler memory references
84 # MSG, DIGEST, K_t, W_t are arrays
85 # WK_2(t) points to 1 of 2 qwords at frame.WK depending on t being odd/even
86
87 # Input message (arg1)
88 #define MSG(i) 8*i(msg)
89
90 # Output Digest (arg2)
91 #define DIGEST(i) 8*i(digest)
92
93 # SHA Constants (static mem)
94 #define K_t(i) 8*i+K512(%rip)
95
96 # Message Schedule (stack frame)
97 #define W_t(i) 8*i+frame_W(%rsp)
98
99 # W[t]+K[t] (stack frame)
100 #define WK_2(i) 8*((i%2))+frame_WK(%rsp)
101
102 .macro RotateState
103 # Rotate symbols a..h right
104 TMP = h_64
105 h_64 = g_64
106 g_64 = f_64
107 f_64 = e_64
108 e_64 = d_64
109 d_64 = c_64
110 c_64 = b_64
111 b_64 = a_64
112 a_64 = TMP
113 .endm
114
115 .macro SHA512_Round rnd
116
117 # Compute Round %%t
118 mov f_64, T1 # T1 = f
119 mov e_64, tmp0 # tmp = e
120 xor g_64, T1 # T1 = f ^ g
121 ror $23, tmp0 # 41 # tmp = e ror 23
122 and e_64, T1 # T1 = (f ^ g) & e
123 xor e_64, tmp0 # tmp = (e ror 23) ^ e
124 xor g_64, T1 # T1 = ((f ^ g) & e) ^ g = CH(e,f,g)
125 idx = \rnd
126 add WK_2(idx), T1 # W[t] + K[t] from message scheduler
127 ror $4, tmp0 # 18 # tmp = ((e ror 23) ^ e) ror 4
128 xor e_64, tmp0 # tmp = (((e ror 23) ^ e) ror 4) ^ e
129 mov a_64, T2 # T2 = a
130 add h_64, T1 # T1 = CH(e,f,g) + W[t] + K[t] + h
131 ror $14, tmp0 # 14 # tmp = ((((e ror23)^e)ror4)^e)ror14 = S1(e)
132 add tmp0, T1 # T1 = CH(e,f,g) + W[t] + K[t] + S1(e)
133 mov a_64, tmp0 # tmp = a
134 xor c_64, T2 # T2 = a ^ c
135 and c_64, tmp0 # tmp = a & c
136 and b_64, T2 # T2 = (a ^ c) & b
137 xor tmp0, T2 # T2 = ((a ^ c) & b) ^ (a & c) = Maj(a,b,c)
138 mov a_64, tmp0 # tmp = a
139 ror $5, tmp0 # 39 # tmp = a ror 5
140 xor a_64, tmp0 # tmp = (a ror 5) ^ a
141 add T1, d_64 # e(next_state) = d + T1
142 ror $6, tmp0 # 34 # tmp = ((a ror 5) ^ a) ror 6
143 xor a_64, tmp0 # tmp = (((a ror 5) ^ a) ror 6) ^ a
144 lea (T1, T2), h_64 # a(next_state) = T1 + Maj(a,b,c)
145 ror $28, tmp0 # 28 # tmp = ((((a ror5)^a)ror6)^a)ror28 = S0(a)
146 add tmp0, h_64 # a(next_state) = T1 + Maj(a,b,c) S0(a)
147 RotateState
148 .endm
149
150 .macro SHA512_2Sched_2Round_sse rnd
151
152 # Compute rounds t-2 and t-1
153 # Compute message schedule QWORDS t and t+1
154
155 # Two rounds are computed based on the values for K[t-2]+W[t-2] and
156 # K[t-1]+W[t-1] which were previously stored at WK_2 by the message
157 # scheduler.
158 # The two new schedule QWORDS are stored at [W_t(%%t)] and [W_t(%%t+1)].
159 # They are then added to their respective SHA512 constants at
160 # [K_t(%%t)] and [K_t(%%t+1)] and stored at dqword [WK_2(%%t)]
161 # For brievity, the comments following vectored instructions only refer to
162 # the first of a pair of QWORDS.
163 # Eg. XMM2=W[t-2] really means XMM2={W[t-2]|W[t-1]}
164 # The computation of the message schedule and the rounds are tightly
165 # stitched to take advantage of instruction-level parallelism.
166 # For clarity, integer instructions (for the rounds calculation) are indented
167 # by one tab. Vectored instructions (for the message scheduler) are indented
168 # by two tabs.
169
170 mov f_64, T1
171 idx = \rnd -2
172 movdqa W_t(idx), %xmm2 # XMM2 = W[t-2]
173 xor g_64, T1
174 and e_64, T1
175 movdqa %xmm2, %xmm0 # XMM0 = W[t-2]
176 xor g_64, T1
177 idx = \rnd
178 add WK_2(idx), T1
179 idx = \rnd - 15
180 movdqu W_t(idx), %xmm5 # XMM5 = W[t-15]
181 mov e_64, tmp0
182 ror $23, tmp0 # 41
183 movdqa %xmm5, %xmm3 # XMM3 = W[t-15]
184 xor e_64, tmp0
185 ror $4, tmp0 # 18
186 psrlq $61-19, %xmm0 # XMM0 = W[t-2] >> 42
187 xor e_64, tmp0
188 ror $14, tmp0 # 14
189 psrlq $(8-7), %xmm3 # XMM3 = W[t-15] >> 1
190 add tmp0, T1
191 add h_64, T1
192 pxor %xmm2, %xmm0 # XMM0 = (W[t-2] >> 42) ^ W[t-2]
193 mov a_64, T2
194 xor c_64, T2
195 pxor %xmm5, %xmm3 # XMM3 = (W[t-15] >> 1) ^ W[t-15]
196 and b_64, T2
197 mov a_64, tmp0
198 psrlq $(19-6), %xmm0 # XMM0 = ((W[t-2]>>42)^W[t-2])>>13
199 and c_64, tmp0
200 xor tmp0, T2
201 psrlq $(7-1), %xmm3 # XMM3 = ((W[t-15]>>1)^W[t-15])>>6
202 mov a_64, tmp0
203 ror $5, tmp0 # 39
204 pxor %xmm2, %xmm0 # XMM0 = (((W[t-2]>>42)^W[t-2])>>13)^W[t-2]
205 xor a_64, tmp0
206 ror $6, tmp0 # 34
207 pxor %xmm5, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]
208 xor a_64, tmp0
209 ror $28, tmp0 # 28
210 psrlq $6, %xmm0 # XMM0 = ((((W[t-2]>>42)^W[t-2])>>13)^W[t-2])>>6
211 add tmp0, T2
212 add T1, d_64
213 psrlq $1, %xmm3 # XMM3 = (((W[t-15]>>1)^W[t-15])>>6)^W[t-15]>>1
214 lea (T1, T2), h_64
215 RotateState
216 movdqa %xmm2, %xmm1 # XMM1 = W[t-2]
217 mov f_64, T1
218 xor g_64, T1
219 movdqa %xmm5, %xmm4 # XMM4 = W[t-15]
220 and e_64, T1
221 xor g_64, T1
222 psllq $(64-19)-(64-61) , %xmm1 # XMM1 = W[t-2] << 42
223 idx = \rnd + 1
224 add WK_2(idx), T1
225 mov e_64, tmp0
226 psllq $(64-1)-(64-8), %xmm4 # XMM4 = W[t-15] << 7
227 ror $23, tmp0 # 41
228 xor e_64, tmp0
229 pxor %xmm2, %xmm1 # XMM1 = (W[t-2] << 42)^W[t-2]
230 ror $4, tmp0 # 18
231 xor e_64, tmp0
232 pxor %xmm5, %xmm4 # XMM4 = (W[t-15]<<7)^W[t-15]
233 ror $14, tmp0 # 14
234 add tmp0, T1
235 psllq $(64-61), %xmm1 # XMM1 = ((W[t-2] << 42)^W[t-2])<<3
236 add h_64, T1
237 mov a_64, T2
238 psllq $(64-8), %xmm4 # XMM4 = ((W[t-15]<<7)^W[t-15])<<56
239 xor c_64, T2
240 and b_64, T2
241 pxor %xmm1, %xmm0 # XMM0 = s1(W[t-2])
242 mov a_64, tmp0
243 and c_64, tmp0
244 idx = \rnd - 7
245 movdqu W_t(idx), %xmm1 # XMM1 = W[t-7]
246 xor tmp0, T2
247 pxor %xmm4, %xmm3 # XMM3 = s0(W[t-15])
248 mov a_64, tmp0
249 paddq %xmm3, %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15])
250 ror $5, tmp0 # 39
251 idx =\rnd-16
252 paddq W_t(idx), %xmm0 # XMM0 = s1(W[t-2]) + s0(W[t-15]) + W[t-16]
253 xor a_64, tmp0
254 paddq %xmm1, %xmm0 # XMM0 = s1(W[t-2]) + W[t-7] + s0(W[t-15]) + W[t-16]
255 ror $6, tmp0 # 34
256 movdqa %xmm0, W_t(\rnd) # Store scheduled qwords
257 xor a_64, tmp0
258 paddq K_t(\rnd), %xmm0 # Compute W[t]+K[t]
259 ror $28, tmp0 # 28
260 idx = \rnd
261 movdqa %xmm0, WK_2(idx) # Store W[t]+K[t] for next rounds
262 add tmp0, T2
263 add T1, d_64
264 lea (T1, T2), h_64
265 RotateState
266 .endm
267
268 ########################################################################
269 ## void sha512_transform_ssse3(struct sha512_state *state, const u8 *data,
270 ## int blocks);
271 # (struct sha512_state is assumed to begin with u64 state[8])
272 # Purpose: Updates the SHA512 digest stored at "state" with the message
273 # stored in "data".
274 # The size of the message pointed to by "data" must be an integer multiple
275 # of SHA512 message blocks.
276 # "blocks" is the message length in SHA512 blocks.
277 ########################################################################
278 SYM_TYPED_FUNC_START(sha512_transform_ssse3)
279
280 test msglen, msglen
281 je .Lnowork
282
283 # Save GPRs
284 push %rbx
285 push %r12
286 push %r13
287 push %r14
288 push %r15
289
290 # Allocate Stack Space
291 push %rbp
292 mov %rsp, %rbp
293 sub $frame_size, %rsp
294 and $~(0x20 - 1), %rsp
295
296 .Lupdateblock:
297
298 # Load state variables
299 mov DIGEST(0), a_64
300 mov DIGEST(1), b_64
301 mov DIGEST(2), c_64
302 mov DIGEST(3), d_64
303 mov DIGEST(4), e_64
304 mov DIGEST(5), f_64
305 mov DIGEST(6), g_64
306 mov DIGEST(7), h_64
307
308 t = 0
309 .rept 80/2 + 1
310 # (80 rounds) / (2 rounds/iteration) + (1 iteration)
311 # +1 iteration because the scheduler leads hashing by 1 iteration
312 .if t < 2
313 # BSWAP 2 QWORDS
314 movdqa XMM_QWORD_BSWAP(%rip), %xmm1
315 movdqu MSG(t), %xmm0
316 pshufb %xmm1, %xmm0 # BSWAP
317 movdqa %xmm0, W_t(t) # Store Scheduled Pair
318 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
319 movdqa %xmm0, WK_2(t) # Store into WK for rounds
320 .elseif t < 16
321 # BSWAP 2 QWORDS# Compute 2 Rounds
322 movdqu MSG(t), %xmm0
323 pshufb %xmm1, %xmm0 # BSWAP
324 SHA512_Round t-2 # Round t-2
325 movdqa %xmm0, W_t(t) # Store Scheduled Pair
326 paddq K_t(t), %xmm0 # Compute W[t]+K[t]
327 SHA512_Round t-1 # Round t-1
328 movdqa %xmm0, WK_2(t) # Store W[t]+K[t] into WK
329 .elseif t < 79
330 # Schedule 2 QWORDS# Compute 2 Rounds
331 SHA512_2Sched_2Round_sse t
332 .else
333 # Compute 2 Rounds
334 SHA512_Round t-2
335 SHA512_Round t-1
336 .endif
337 t = t+2
338 .endr
339
340 # Update digest
341 add a_64, DIGEST(0)
342 add b_64, DIGEST(1)
343 add c_64, DIGEST(2)
344 add d_64, DIGEST(3)
345 add e_64, DIGEST(4)
346 add f_64, DIGEST(5)
347 add g_64, DIGEST(6)
348 add h_64, DIGEST(7)
349
350 # Advance to next message block
351 add $16*8, msg
352 dec msglen
353 jnz .Lupdateblock
354
355 # Restore Stack Pointer
356 mov %rbp, %rsp
357 pop %rbp
358
359 # Restore GPRs
360 pop %r15
361 pop %r14
362 pop %r13
363 pop %r12
364 pop %rbx
365
366 .Lnowork:
367 RET
368 SYM_FUNC_END(sha512_transform_ssse3)
369
370 ########################################################################
371 ### Binary Data
372
373 .section .rodata.cst16.XMM_QWORD_BSWAP, "aM", @progbits, 16
374 .align 16
375 # Mask for byte-swapping a couple of qwords in an XMM register using (v)pshufb.
376 XMM_QWORD_BSWAP:
377 .octa 0x08090a0b0c0d0e0f0001020304050607
378
379 # Mergeable 640-byte rodata section. This allows linker to merge the table
380 # with other, exactly the same 640-byte fragment of another rodata section
381 # (if such section exists).
382 .section .rodata.cst640.K512, "aM", @progbits, 640
383 .align 64
384 # K[t] used in SHA512 hashing
385 K512:
386 .quad 0x428a2f98d728ae22,0x7137449123ef65cd
387 .quad 0xb5c0fbcfec4d3b2f,0xe9b5dba58189dbbc
388 .quad 0x3956c25bf348b538,0x59f111f1b605d019
389 .quad 0x923f82a4af194f9b,0xab1c5ed5da6d8118
390 .quad 0xd807aa98a3030242,0x12835b0145706fbe
391 .quad 0x243185be4ee4b28c,0x550c7dc3d5ffb4e2
392 .quad 0x72be5d74f27b896f,0x80deb1fe3b1696b1
393 .quad 0x9bdc06a725c71235,0xc19bf174cf692694
394 .quad 0xe49b69c19ef14ad2,0xefbe4786384f25e3
395 .quad 0x0fc19dc68b8cd5b5,0x240ca1cc77ac9c65
396 .quad 0x2de92c6f592b0275,0x4a7484aa6ea6e483
397 .quad 0x5cb0a9dcbd41fbd4,0x76f988da831153b5
398 .quad 0x983e5152ee66dfab,0xa831c66d2db43210
399 .quad 0xb00327c898fb213f,0xbf597fc7beef0ee4
400 .quad 0xc6e00bf33da88fc2,0xd5a79147930aa725
401 .quad 0x06ca6351e003826f,0x142929670a0e6e70
402 .quad 0x27b70a8546d22ffc,0x2e1b21385c26c926
403 .quad 0x4d2c6dfc5ac42aed,0x53380d139d95b3df
404 .quad 0x650a73548baf63de,0x766a0abb3c77b2a8
405 .quad 0x81c2c92e47edaee6,0x92722c851482353b
406 .quad 0xa2bfe8a14cf10364,0xa81a664bbc423001
407 .quad 0xc24b8b70d0f89791,0xc76c51a30654be30
408 .quad 0xd192e819d6ef5218,0xd69906245565a910
409 .quad 0xf40e35855771202a,0x106aa07032bbd1b8
410 .quad 0x19a4c116b8d2d0c8,0x1e376c085141ab53
411 .quad 0x2748774cdf8eeb99,0x34b0bcb5e19b48a8
412 .quad 0x391c0cb3c5c95a63,0x4ed8aa4ae3418acb
413 .quad 0x5b9cca4f7763e373,0x682e6ff3d6b2b8a3
414 .quad 0x748f82ee5defb2fc,0x78a5636f43172f60
415 .quad 0x84c87814a1f0ab72,0x8cc702081a6439ec
416 .quad 0x90befffa23631e28,0xa4506cebde82bde9
417 .quad 0xbef9a3f7b2c67915,0xc67178f2e372532b
418 .quad 0xca273eceea26619c,0xd186b8c721c0c207
419 .quad 0xeada7dd6cde0eb1e,0xf57d4f7fee6ed178
420 .quad 0x06f067aa72176fba,0x0a637dc5a2c898a6
421 .quad 0x113f9804bef90dae,0x1b710b35131c471b
422 .quad 0x28db77f523047d84,0x32caab7b40c72493
423 .quad 0x3c9ebe0a15c9bebc,0x431d67c49c100d4c
424 .quad 0x4cc5d4becb3e42b6,0x597f299cfc657e2a
425 .quad 0x5fcb6fab3ad6faec,0x6c44198c4a475817
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