1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef _ASM_X86_DESC_H
3 #define _ASM_X86_DESC_H
4
5 #include <asm/desc_defs.h>
6 #include <asm/ldt.h>
7 #include <asm/mmu.h>
8 #include <asm/fixmap.h>
9 #include <asm/irq_vectors.h>
10 #include <asm/cpu_entry_area.h>
11
12 #include <linux/debug_locks.h>
13 #include <linux/smp.h>
14 #include <linux/percpu.h>
15
16 static inline void fill_ldt(struct desc_struct *desc, const struct user_desc *info)
17 {
18 desc->limit0 = info->limit & 0x0ffff;
19
20 desc->base0 = (info->base_addr & 0x0000ffff);
21 desc->base1 = (info->base_addr & 0x00ff0000) >> 16;
22
23 desc->type = (info->read_exec_only ^ 1) << 1;
24 desc->type |= info->contents << 2;
25 /* Set the ACCESS bit so it can be mapped RO */
26 desc->type |= 1;
27
28 desc->s = 1;
29 desc->dpl = 0x3;
30 desc->p = info->seg_not_present ^ 1;
31 desc->limit1 = (info->limit & 0xf0000) >> 16;
32 desc->avl = info->useable;
33 desc->d = info->seg_32bit;
34 desc->g = info->limit_in_pages;
35
36 desc->base2 = (info->base_addr & 0xff000000) >> 24;
37 /*
38 * Don't allow setting of the lm bit. It would confuse
39 * user_64bit_mode and would get overridden by sysret anyway.
40 */
41 desc->l = 0;
42 }
43
44 struct gdt_page {
45 struct desc_struct gdt[GDT_ENTRIES];
46 } __attribute__((aligned(PAGE_SIZE)));
47
48 DECLARE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page);
49 DECLARE_INIT_PER_CPU(gdt_page);
50
51 /* Provide the original GDT */
52 static inline struct desc_struct *get_cpu_gdt_rw(unsigned int cpu)
53 {
54 return per_cpu(gdt_page, cpu).gdt;
55 }
56
57 /* Provide the current original GDT */
58 static inline struct desc_struct *get_current_gdt_rw(void)
59 {
60 return this_cpu_ptr(&gdt_page)->gdt;
61 }
62
63 /* Provide the fixmap address of the remapped GDT */
64 static inline struct desc_struct *get_cpu_gdt_ro(int cpu)
65 {
66 return (struct desc_struct *)&get_cpu_entry_area(cpu)->gdt;
67 }
68
69 /* Provide the current read-only GDT */
70 static inline struct desc_struct *get_current_gdt_ro(void)
71 {
72 return get_cpu_gdt_ro(smp_processor_id());
73 }
74
75 /* Provide the physical address of the GDT page. */
76 static inline phys_addr_t get_cpu_gdt_paddr(unsigned int cpu)
77 {
78 return per_cpu_ptr_to_phys(get_cpu_gdt_rw(cpu));
79 }
80
81 static inline void pack_gate(gate_desc *gate, unsigned type, unsigned long func,
82 unsigned dpl, unsigned ist, unsigned seg)
83 {
84 gate->offset_low = (u16) func;
85 gate->bits.p = 1;
86 gate->bits.dpl = dpl;
87 gate->bits.zero = 0;
88 gate->bits.type = type;
89 gate->offset_middle = (u16) (func >> 16);
90 #ifdef CONFIG_X86_64
91 gate->segment = __KERNEL_CS;
92 gate->bits.ist = ist;
93 gate->reserved = 0;
94 gate->offset_high = (u32) (func >> 32);
95 #else
96 gate->segment = seg;
97 gate->bits.ist = 0;
98 #endif
99 }
100
101 static inline int desc_empty(const void *ptr)
102 {
103 const u32 *desc = ptr;
104
105 return !(desc[0] | desc[1]);
106 }
107
108 #ifdef CONFIG_PARAVIRT_XXL
109 #include <asm/paravirt.h>
110 #else
111 #define load_TR_desc() native_load_tr_desc()
112 #define load_gdt(dtr) native_load_gdt(dtr)
113 #define load_idt(dtr) native_load_idt(dtr)
114 #define load_tr(tr) asm volatile("ltr %0"::"m" (tr))
115 #define load_ldt(ldt) asm volatile("lldt %0"::"m" (ldt))
116
117 #define store_gdt(dtr) native_store_gdt(dtr)
118 #define store_tr(tr) (tr = native_store_tr())
119
120 #define load_TLS(t, cpu) native_load_tls(t, cpu)
121 #define set_ldt native_set_ldt
122
123 #define write_ldt_entry(dt, entry, desc) native_write_ldt_entry(dt, entry, desc)
124 #define write_gdt_entry(dt, entry, desc, type) native_write_gdt_entry(dt, entry, desc, type)
125 #define write_idt_entry(dt, entry, g) native_write_idt_entry(dt, entry, g)
126
127 static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
128 {
129 }
130
131 static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
132 {
133 }
134 #endif /* CONFIG_PARAVIRT_XXL */
135
136 #define store_ldt(ldt) asm("sldt %0" : "=m"(ldt))
137
138 static inline void native_write_idt_entry(gate_desc *idt, int entry, const gate_desc *gate)
139 {
140 memcpy(&idt[entry], gate, sizeof(*gate));
141 }
142
143 static inline void native_write_ldt_entry(struct desc_struct *ldt, int entry, const void *desc)
144 {
145 memcpy(&ldt[entry], desc, 8);
146 }
147
148 static inline void
149 native_write_gdt_entry(struct desc_struct *gdt, int entry, const void *desc, int type)
150 {
151 unsigned int size;
152
153 switch (type) {
154 case DESC_TSS: size = sizeof(tss_desc); break;
155 case DESC_LDT: size = sizeof(ldt_desc); break;
156 default: size = sizeof(*gdt); break;
157 }
158
159 memcpy(&gdt[entry], desc, size);
160 }
161
162 static inline void set_tssldt_descriptor(void *d, unsigned long addr,
163 unsigned type, unsigned size)
164 {
165 struct ldttss_desc *desc = d;
166
167 memset(desc, 0, sizeof(*desc));
168
169 desc->limit0 = (u16) size;
170 desc->base0 = (u16) addr;
171 desc->base1 = (addr >> 16) & 0xFF;
172 desc->type = type;
173 desc->p = 1;
174 desc->limit1 = (size >> 16) & 0xF;
175 desc->base2 = (addr >> 24) & 0xFF;
176 #ifdef CONFIG_X86_64
177 desc->base3 = (u32) (addr >> 32);
178 #endif
179 }
180
181 static inline void __set_tss_desc(unsigned cpu, unsigned int entry, struct x86_hw_tss *addr)
182 {
183 struct desc_struct *d = get_cpu_gdt_rw(cpu);
184 tss_desc tss;
185
186 set_tssldt_descriptor(&tss, (unsigned long)addr, DESC_TSS,
187 __KERNEL_TSS_LIMIT);
188 write_gdt_entry(d, entry, &tss, DESC_TSS);
189 }
190
191 #define set_tss_desc(cpu, addr) __set_tss_desc(cpu, GDT_ENTRY_TSS, addr)
192
193 static inline void native_set_ldt(const void *addr, unsigned int entries)
194 {
195 if (likely(entries == 0))
196 asm volatile("lldt %w0"::"q" (0));
197 else {
198 unsigned cpu = smp_processor_id();
199 ldt_desc ldt;
200
201 set_tssldt_descriptor(&ldt, (unsigned long)addr, DESC_LDT,
202 entries * LDT_ENTRY_SIZE - 1);
203 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_LDT,
204 &ldt, DESC_LDT);
205 asm volatile("lldt %w0"::"q" (GDT_ENTRY_LDT*8));
206 }
207 }
208
209 static inline void native_load_gdt(const struct desc_ptr *dtr)
210 {
211 asm volatile("lgdt %0"::"m" (*dtr));
212 }
213
214 static __always_inline void native_load_idt(const struct desc_ptr *dtr)
215 {
216 asm volatile("lidt %0"::"m" (*dtr));
217 }
218
219 static inline void native_store_gdt(struct desc_ptr *dtr)
220 {
221 asm volatile("sgdt %0":"=m" (*dtr));
222 }
223
224 static inline void store_idt(struct desc_ptr *dtr)
225 {
226 asm volatile("sidt %0":"=m" (*dtr));
227 }
228
229 static inline void native_gdt_invalidate(void)
230 {
231 const struct desc_ptr invalid_gdt = {
232 .address = 0,
233 .size = 0
234 };
235
236 native_load_gdt(&invalid_gdt);
237 }
238
239 static inline void native_idt_invalidate(void)
240 {
241 const struct desc_ptr invalid_idt = {
242 .address = 0,
243 .size = 0
244 };
245
246 native_load_idt(&invalid_idt);
247 }
248
249 /*
250 * The LTR instruction marks the TSS GDT entry as busy. On 64-bit, the GDT is
251 * a read-only remapping. To prevent a page fault, the GDT is switched to the
252 * original writeable version when needed.
253 */
254 #ifdef CONFIG_X86_64
255 static inline void native_load_tr_desc(void)
256 {
257 struct desc_ptr gdt;
258 int cpu = raw_smp_processor_id();
259 bool restore = 0;
260 struct desc_struct *fixmap_gdt;
261
262 native_store_gdt(&gdt);
263 fixmap_gdt = get_cpu_gdt_ro(cpu);
264
265 /*
266 * If the current GDT is the read-only fixmap, swap to the original
267 * writeable version. Swap back at the end.
268 */
269 if (gdt.address == (unsigned long)fixmap_gdt) {
270 load_direct_gdt(cpu);
271 restore = 1;
272 }
273 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
274 if (restore)
275 load_fixmap_gdt(cpu);
276 }
277 #else
278 static inline void native_load_tr_desc(void)
279 {
280 asm volatile("ltr %w0"::"q" (GDT_ENTRY_TSS*8));
281 }
282 #endif
283
284 static inline unsigned long native_store_tr(void)
285 {
286 unsigned long tr;
287
288 asm volatile("str %0":"=r" (tr));
289
290 return tr;
291 }
292
293 static inline void native_load_tls(struct thread_struct *t, unsigned int cpu)
294 {
295 struct desc_struct *gdt = get_cpu_gdt_rw(cpu);
296 unsigned int i;
297
298 for (i = 0; i < GDT_ENTRY_TLS_ENTRIES; i++)
299 gdt[GDT_ENTRY_TLS_MIN + i] = t->tls_array[i];
300 }
301
302 DECLARE_PER_CPU(bool, __tss_limit_invalid);
303
304 static inline void force_reload_TR(void)
305 {
306 struct desc_struct *d = get_current_gdt_rw();
307 tss_desc tss;
308
309 memcpy(&tss, &d[GDT_ENTRY_TSS], sizeof(tss_desc));
310
311 /*
312 * LTR requires an available TSS, and the TSS is currently
313 * busy. Make it be available so that LTR will work.
314 */
315 tss.type = DESC_TSS;
316 write_gdt_entry(d, GDT_ENTRY_TSS, &tss, DESC_TSS);
317
318 load_TR_desc();
319 this_cpu_write(__tss_limit_invalid, false);
320 }
321
322 /*
323 * Call this if you need the TSS limit to be correct, which should be the case
324 * if and only if you have TIF_IO_BITMAP set or you're switching to a task
325 * with TIF_IO_BITMAP set.
326 */
327 static inline void refresh_tss_limit(void)
328 {
329 DEBUG_LOCKS_WARN_ON(preemptible());
330
331 if (unlikely(this_cpu_read(__tss_limit_invalid)))
332 force_reload_TR();
333 }
334
335 /*
336 * If you do something evil that corrupts the cached TSS limit (I'm looking
337 * at you, VMX exits), call this function.
338 *
339 * The optimization here is that the TSS limit only matters for Linux if the
340 * IO bitmap is in use. If the TSS limit gets forced to its minimum value,
341 * everything works except that IO bitmap will be ignored and all CPL 3 IO
342 * instructions will #GP, which is exactly what we want for normal tasks.
343 */
344 static inline void invalidate_tss_limit(void)
345 {
346 DEBUG_LOCKS_WARN_ON(preemptible());
347
348 if (unlikely(test_thread_flag(TIF_IO_BITMAP)))
349 force_reload_TR();
350 else
351 this_cpu_write(__tss_limit_invalid, true);
352 }
353
354 /* This intentionally ignores lm, since 32-bit apps don't have that field. */
355 #define LDT_empty(info) \
356 ((info)->base_addr == 0 && \
357 (info)->limit == 0 && \
358 (info)->contents == 0 && \
359 (info)->read_exec_only == 1 && \
360 (info)->seg_32bit == 0 && \
361 (info)->limit_in_pages == 0 && \
362 (info)->seg_not_present == 1 && \
363 (info)->useable == 0)
364
365 /* Lots of programs expect an all-zero user_desc to mean "no segment at all". */
366 static inline bool LDT_zero(const struct user_desc *info)
367 {
368 return (info->base_addr == 0 &&
369 info->limit == 0 &&
370 info->contents == 0 &&
371 info->read_exec_only == 0 &&
372 info->seg_32bit == 0 &&
373 info->limit_in_pages == 0 &&
374 info->seg_not_present == 0 &&
375 info->useable == 0);
376 }
377
378 static inline void clear_LDT(void)
379 {
380 set_ldt(NULL, 0);
381 }
382
383 static inline unsigned long get_desc_base(const struct desc_struct *desc)
384 {
385 return (unsigned)(desc->base0 | ((desc->base1) << 16) | ((desc->base2) << 24));
386 }
387
388 static inline void set_desc_base(struct desc_struct *desc, unsigned long base)
389 {
390 desc->base0 = base & 0xffff;
391 desc->base1 = (base >> 16) & 0xff;
392 desc->base2 = (base >> 24) & 0xff;
393 }
394
395 static inline unsigned long get_desc_limit(const struct desc_struct *desc)
396 {
397 return desc->limit0 | (desc->limit1 << 16);
398 }
399
400 static inline void set_desc_limit(struct desc_struct *desc, unsigned long limit)
401 {
402 desc->limit0 = limit & 0xffff;
403 desc->limit1 = (limit >> 16) & 0xf;
404 }
405
406 static inline void init_idt_data(struct idt_data *data, unsigned int n,
407 const void *addr)
408 {
409 BUG_ON(n > 0xFF);
410
411 memset(data, 0, sizeof(*data));
412 data->vector = n;
413 data->addr = addr;
414 data->segment = __KERNEL_CS;
415 data->bits.type = GATE_INTERRUPT;
416 data->bits.p = 1;
417 }
418
419 static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
420 {
421 unsigned long addr = (unsigned long) d->addr;
422
423 gate->offset_low = (u16) addr;
424 gate->segment = (u16) d->segment;
425 gate->bits = d->bits;
426 gate->offset_middle = (u16) (addr >> 16);
427 #ifdef CONFIG_X86_64
428 gate->offset_high = (u32) (addr >> 32);
429 gate->reserved = 0;
430 #endif
431 }
432
433 extern unsigned long system_vectors[];
434
435 extern void load_current_idt(void);
436 extern void idt_setup_early_handler(void);
437 extern void idt_setup_early_traps(void);
438 extern void idt_setup_traps(void);
439 extern void idt_setup_apic_and_irq_gates(void);
440 extern bool idt_is_f00f_address(unsigned long address);
441
442 #ifdef CONFIG_X86_64
443 extern void idt_setup_early_pf(void);
444 #else
445 static inline void idt_setup_early_pf(void) { }
446 #endif
447
448 extern void idt_invalidate(void);
449
450 #endif /* _ASM_X86_DESC_H */
451
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