1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Netburst Performance Events (P4, old Xeon)
4 */
5
6 #ifndef PERF_EVENT_P4_H
7 #define PERF_EVENT_P4_H
8
9 #include <linux/cpu.h>
10 #include <linux/bitops.h>
11
12 /*
13 * NetBurst has performance MSRs shared between
14 * threads if HT is turned on, ie for both logical
15 * processors (mem: in turn in Atom with HT support
16 * perf-MSRs are not shared and every thread has its
17 * own perf-MSRs set)
18 */
19 #define ARCH_P4_TOTAL_ESCR (46)
20 #define ARCH_P4_RESERVED_ESCR (2) /* IQ_ESCR(0,1) not always present */
21 #define ARCH_P4_MAX_ESCR (ARCH_P4_TOTAL_ESCR - ARCH_P4_RESERVED_ESCR)
22 #define ARCH_P4_MAX_CCCR (18)
23
24 #define ARCH_P4_CNTRVAL_BITS (40)
25 #define ARCH_P4_CNTRVAL_MASK ((1ULL << ARCH_P4_CNTRVAL_BITS) - 1)
26 #define ARCH_P4_UNFLAGGED_BIT ((1ULL) << (ARCH_P4_CNTRVAL_BITS - 1))
27
28 #define P4_ESCR_EVENT_MASK 0x7e000000ULL
29 #define P4_ESCR_EVENT_SHIFT 25
30 #define P4_ESCR_EVENTMASK_MASK 0x01fffe00ULL
31 #define P4_ESCR_EVENTMASK_SHIFT 9
32 #define P4_ESCR_TAG_MASK 0x000001e0ULL
33 #define P4_ESCR_TAG_SHIFT 5
34 #define P4_ESCR_TAG_ENABLE 0x00000010ULL
35 #define P4_ESCR_T0_OS 0x00000008ULL
36 #define P4_ESCR_T0_USR 0x00000004ULL
37 #define P4_ESCR_T1_OS 0x00000002ULL
38 #define P4_ESCR_T1_USR 0x00000001ULL
39
40 #define P4_ESCR_EVENT(v) ((v) << P4_ESCR_EVENT_SHIFT)
41 #define P4_ESCR_EMASK(v) ((v) << P4_ESCR_EVENTMASK_SHIFT)
42 #define P4_ESCR_TAG(v) ((v) << P4_ESCR_TAG_SHIFT)
43
44 #define P4_CCCR_OVF 0x80000000ULL
45 #define P4_CCCR_CASCADE 0x40000000ULL
46 #define P4_CCCR_OVF_PMI_T0 0x04000000ULL
47 #define P4_CCCR_OVF_PMI_T1 0x08000000ULL
48 #define P4_CCCR_FORCE_OVF 0x02000000ULL
49 #define P4_CCCR_EDGE 0x01000000ULL
50 #define P4_CCCR_THRESHOLD_MASK 0x00f00000ULL
51 #define P4_CCCR_THRESHOLD_SHIFT 20
52 #define P4_CCCR_COMPLEMENT 0x00080000ULL
53 #define P4_CCCR_COMPARE 0x00040000ULL
54 #define P4_CCCR_ESCR_SELECT_MASK 0x0000e000ULL
55 #define P4_CCCR_ESCR_SELECT_SHIFT 13
56 #define P4_CCCR_ENABLE 0x00001000ULL
57 #define P4_CCCR_THREAD_SINGLE 0x00010000ULL
58 #define P4_CCCR_THREAD_BOTH 0x00020000ULL
59 #define P4_CCCR_THREAD_ANY 0x00030000ULL
60 #define P4_CCCR_RESERVED 0x00000fffULL
61
62 #define P4_CCCR_THRESHOLD(v) ((v) << P4_CCCR_THRESHOLD_SHIFT)
63 #define P4_CCCR_ESEL(v) ((v) << P4_CCCR_ESCR_SELECT_SHIFT)
64
65 #define P4_GEN_ESCR_EMASK(class, name, bit) \
66 class##__##name = ((1ULL << bit) << P4_ESCR_EVENTMASK_SHIFT)
67 #define P4_ESCR_EMASK_BIT(class, name) class##__##name
68
69 /*
70 * config field is 64bit width and consists of
71 * HT << 63 | ESCR << 32 | CCCR
72 * where HT is HyperThreading bit (since ESCR
73 * has it reserved we may use it for own purpose)
74 *
75 * note that this is NOT the addresses of respective
76 * ESCR and CCCR but rather an only packed value should
77 * be unpacked and written to a proper addresses
78 *
79 * the base idea is to pack as much info as possible
80 */
81 #define p4_config_pack_escr(v) (((u64)(v)) << 32)
82 #define p4_config_pack_cccr(v) (((u64)(v)) & 0xffffffffULL)
83 #define p4_config_unpack_escr(v) (((u64)(v)) >> 32)
84 #define p4_config_unpack_cccr(v) (((u64)(v)) & 0xffffffffULL)
85
86 #define p4_config_unpack_emask(v) \
87 ({ \
88 u32 t = p4_config_unpack_escr((v)); \
89 t = t & P4_ESCR_EVENTMASK_MASK; \
90 t = t >> P4_ESCR_EVENTMASK_SHIFT; \
91 t; \
92 })
93
94 #define p4_config_unpack_event(v) \
95 ({ \
96 u32 t = p4_config_unpack_escr((v)); \
97 t = t & P4_ESCR_EVENT_MASK; \
98 t = t >> P4_ESCR_EVENT_SHIFT; \
99 t; \
100 })
101
102 #define P4_CONFIG_HT_SHIFT 63
103 #define P4_CONFIG_HT (1ULL << P4_CONFIG_HT_SHIFT)
104
105 /*
106 * If an event has alias it should be marked
107 * with a special bit. (Don't forget to check
108 * P4_PEBS_CONFIG_MASK and related bits on
109 * modification.)
110 */
111 #define P4_CONFIG_ALIASABLE (1ULL << 9)
112
113 /*
114 * The bits we allow to pass for RAW events
115 */
116 #define P4_CONFIG_MASK_ESCR \
117 P4_ESCR_EVENT_MASK | \
118 P4_ESCR_EVENTMASK_MASK | \
119 P4_ESCR_TAG_MASK | \
120 P4_ESCR_TAG_ENABLE
121
122 #define P4_CONFIG_MASK_CCCR \
123 P4_CCCR_EDGE | \
124 P4_CCCR_THRESHOLD_MASK | \
125 P4_CCCR_COMPLEMENT | \
126 P4_CCCR_COMPARE | \
127 P4_CCCR_THREAD_ANY | \
128 P4_CCCR_RESERVED
129
130 /* some dangerous bits are reserved for kernel internals */
131 #define P4_CONFIG_MASK \
132 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR)) | \
133 (p4_config_pack_cccr(P4_CONFIG_MASK_CCCR))
134
135 /*
136 * In case of event aliasing we need to preserve some
137 * caller bits, otherwise the mapping won't be complete.
138 */
139 #define P4_CONFIG_EVENT_ALIAS_MASK \
140 (p4_config_pack_escr(P4_CONFIG_MASK_ESCR) | \
141 p4_config_pack_cccr(P4_CCCR_EDGE | \
142 P4_CCCR_THRESHOLD_MASK | \
143 P4_CCCR_COMPLEMENT | \
144 P4_CCCR_COMPARE))
145
146 #define P4_CONFIG_EVENT_ALIAS_IMMUTABLE_BITS \
147 ((P4_CONFIG_HT) | \
148 p4_config_pack_escr(P4_ESCR_T0_OS | \
149 P4_ESCR_T0_USR | \
150 P4_ESCR_T1_OS | \
151 P4_ESCR_T1_USR) | \
152 p4_config_pack_cccr(P4_CCCR_OVF | \
153 P4_CCCR_CASCADE | \
154 P4_CCCR_FORCE_OVF | \
155 P4_CCCR_THREAD_ANY | \
156 P4_CCCR_OVF_PMI_T0 | \
157 P4_CCCR_OVF_PMI_T1 | \
158 P4_CONFIG_ALIASABLE))
159
160 static inline bool p4_is_event_cascaded(u64 config)
161 {
162 u32 cccr = p4_config_unpack_cccr(config);
163 return !!(cccr & P4_CCCR_CASCADE);
164 }
165
166 static inline int p4_ht_config_thread(u64 config)
167 {
168 return !!(config & P4_CONFIG_HT);
169 }
170
171 static inline u64 p4_set_ht_bit(u64 config)
172 {
173 return config | P4_CONFIG_HT;
174 }
175
176 static inline u64 p4_clear_ht_bit(u64 config)
177 {
178 return config & ~P4_CONFIG_HT;
179 }
180
181 static inline int p4_ht_active(void)
182 {
183 #ifdef CONFIG_SMP
184 return __max_threads_per_core > 1;
185 #endif
186 return 0;
187 }
188
189 static inline int p4_ht_thread(int cpu)
190 {
191 #ifdef CONFIG_SMP
192 if (__max_threads_per_core == 2)
193 return cpu != cpumask_first(this_cpu_cpumask_var_ptr(cpu_sibling_map));
194 #endif
195 return 0;
196 }
197
198 static inline int p4_should_swap_ts(u64 config, int cpu)
199 {
200 return p4_ht_config_thread(config) ^ p4_ht_thread(cpu);
201 }
202
203 static inline u32 p4_default_cccr_conf(int cpu)
204 {
205 /*
206 * Note that P4_CCCR_THREAD_ANY is "required" on
207 * non-HT machines (on HT machines we count TS events
208 * regardless the state of second logical processor
209 */
210 u32 cccr = P4_CCCR_THREAD_ANY;
211
212 if (!p4_ht_thread(cpu))
213 cccr |= P4_CCCR_OVF_PMI_T0;
214 else
215 cccr |= P4_CCCR_OVF_PMI_T1;
216
217 return cccr;
218 }
219
220 static inline u32 p4_default_escr_conf(int cpu, int exclude_os, int exclude_usr)
221 {
222 u32 escr = 0;
223
224 if (!p4_ht_thread(cpu)) {
225 if (!exclude_os)
226 escr |= P4_ESCR_T0_OS;
227 if (!exclude_usr)
228 escr |= P4_ESCR_T0_USR;
229 } else {
230 if (!exclude_os)
231 escr |= P4_ESCR_T1_OS;
232 if (!exclude_usr)
233 escr |= P4_ESCR_T1_USR;
234 }
235
236 return escr;
237 }
238
239 /*
240 * This are the events which should be used in "Event Select"
241 * field of ESCR register, they are like unique keys which allow
242 * the kernel to determinate which CCCR and COUNTER should be
243 * used to track an event
244 */
245 enum P4_EVENTS {
246 P4_EVENT_TC_DELIVER_MODE,
247 P4_EVENT_BPU_FETCH_REQUEST,
248 P4_EVENT_ITLB_REFERENCE,
249 P4_EVENT_MEMORY_CANCEL,
250 P4_EVENT_MEMORY_COMPLETE,
251 P4_EVENT_LOAD_PORT_REPLAY,
252 P4_EVENT_STORE_PORT_REPLAY,
253 P4_EVENT_MOB_LOAD_REPLAY,
254 P4_EVENT_PAGE_WALK_TYPE,
255 P4_EVENT_BSQ_CACHE_REFERENCE,
256 P4_EVENT_IOQ_ALLOCATION,
257 P4_EVENT_IOQ_ACTIVE_ENTRIES,
258 P4_EVENT_FSB_DATA_ACTIVITY,
259 P4_EVENT_BSQ_ALLOCATION,
260 P4_EVENT_BSQ_ACTIVE_ENTRIES,
261 P4_EVENT_SSE_INPUT_ASSIST,
262 P4_EVENT_PACKED_SP_UOP,
263 P4_EVENT_PACKED_DP_UOP,
264 P4_EVENT_SCALAR_SP_UOP,
265 P4_EVENT_SCALAR_DP_UOP,
266 P4_EVENT_64BIT_MMX_UOP,
267 P4_EVENT_128BIT_MMX_UOP,
268 P4_EVENT_X87_FP_UOP,
269 P4_EVENT_TC_MISC,
270 P4_EVENT_GLOBAL_POWER_EVENTS,
271 P4_EVENT_TC_MS_XFER,
272 P4_EVENT_UOP_QUEUE_WRITES,
273 P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE,
274 P4_EVENT_RETIRED_BRANCH_TYPE,
275 P4_EVENT_RESOURCE_STALL,
276 P4_EVENT_WC_BUFFER,
277 P4_EVENT_B2B_CYCLES,
278 P4_EVENT_BNR,
279 P4_EVENT_SNOOP,
280 P4_EVENT_RESPONSE,
281 P4_EVENT_FRONT_END_EVENT,
282 P4_EVENT_EXECUTION_EVENT,
283 P4_EVENT_REPLAY_EVENT,
284 P4_EVENT_INSTR_RETIRED,
285 P4_EVENT_UOPS_RETIRED,
286 P4_EVENT_UOP_TYPE,
287 P4_EVENT_BRANCH_RETIRED,
288 P4_EVENT_MISPRED_BRANCH_RETIRED,
289 P4_EVENT_X87_ASSIST,
290 P4_EVENT_MACHINE_CLEAR,
291 P4_EVENT_INSTR_COMPLETED,
292 };
293
294 #define P4_OPCODE(event) event##_OPCODE
295 #define P4_OPCODE_ESEL(opcode) ((opcode & 0x00ff) >> 0)
296 #define P4_OPCODE_EVNT(opcode) ((opcode & 0xff00) >> 8)
297 #define P4_OPCODE_PACK(event, sel) (((event) << 8) | sel)
298
299 /*
300 * Comments below the event represent ESCR restriction
301 * for this event and counter index per ESCR
302 *
303 * MSR_P4_IQ_ESCR0 and MSR_P4_IQ_ESCR1 are available only on early
304 * processor builds (family 0FH, models 01H-02H). These MSRs
305 * are not available on later versions, so that we don't use
306 * them completely
307 *
308 * Also note that CCCR1 do not have P4_CCCR_ENABLE bit properly
309 * working so that we should not use this CCCR and respective
310 * counter as result
311 */
312 enum P4_EVENT_OPCODES {
313 P4_OPCODE(P4_EVENT_TC_DELIVER_MODE) = P4_OPCODE_PACK(0x01, 0x01),
314 /*
315 * MSR_P4_TC_ESCR0: 4, 5
316 * MSR_P4_TC_ESCR1: 6, 7
317 */
318
319 P4_OPCODE(P4_EVENT_BPU_FETCH_REQUEST) = P4_OPCODE_PACK(0x03, 0x00),
320 /*
321 * MSR_P4_BPU_ESCR0: 0, 1
322 * MSR_P4_BPU_ESCR1: 2, 3
323 */
324
325 P4_OPCODE(P4_EVENT_ITLB_REFERENCE) = P4_OPCODE_PACK(0x18, 0x03),
326 /*
327 * MSR_P4_ITLB_ESCR0: 0, 1
328 * MSR_P4_ITLB_ESCR1: 2, 3
329 */
330
331 P4_OPCODE(P4_EVENT_MEMORY_CANCEL) = P4_OPCODE_PACK(0x02, 0x05),
332 /*
333 * MSR_P4_DAC_ESCR0: 8, 9
334 * MSR_P4_DAC_ESCR1: 10, 11
335 */
336
337 P4_OPCODE(P4_EVENT_MEMORY_COMPLETE) = P4_OPCODE_PACK(0x08, 0x02),
338 /*
339 * MSR_P4_SAAT_ESCR0: 8, 9
340 * MSR_P4_SAAT_ESCR1: 10, 11
341 */
342
343 P4_OPCODE(P4_EVENT_LOAD_PORT_REPLAY) = P4_OPCODE_PACK(0x04, 0x02),
344 /*
345 * MSR_P4_SAAT_ESCR0: 8, 9
346 * MSR_P4_SAAT_ESCR1: 10, 11
347 */
348
349 P4_OPCODE(P4_EVENT_STORE_PORT_REPLAY) = P4_OPCODE_PACK(0x05, 0x02),
350 /*
351 * MSR_P4_SAAT_ESCR0: 8, 9
352 * MSR_P4_SAAT_ESCR1: 10, 11
353 */
354
355 P4_OPCODE(P4_EVENT_MOB_LOAD_REPLAY) = P4_OPCODE_PACK(0x03, 0x02),
356 /*
357 * MSR_P4_MOB_ESCR0: 0, 1
358 * MSR_P4_MOB_ESCR1: 2, 3
359 */
360
361 P4_OPCODE(P4_EVENT_PAGE_WALK_TYPE) = P4_OPCODE_PACK(0x01, 0x04),
362 /*
363 * MSR_P4_PMH_ESCR0: 0, 1
364 * MSR_P4_PMH_ESCR1: 2, 3
365 */
366
367 P4_OPCODE(P4_EVENT_BSQ_CACHE_REFERENCE) = P4_OPCODE_PACK(0x0c, 0x07),
368 /*
369 * MSR_P4_BSU_ESCR0: 0, 1
370 * MSR_P4_BSU_ESCR1: 2, 3
371 */
372
373 P4_OPCODE(P4_EVENT_IOQ_ALLOCATION) = P4_OPCODE_PACK(0x03, 0x06),
374 /*
375 * MSR_P4_FSB_ESCR0: 0, 1
376 * MSR_P4_FSB_ESCR1: 2, 3
377 */
378
379 P4_OPCODE(P4_EVENT_IOQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x1a, 0x06),
380 /*
381 * MSR_P4_FSB_ESCR1: 2, 3
382 */
383
384 P4_OPCODE(P4_EVENT_FSB_DATA_ACTIVITY) = P4_OPCODE_PACK(0x17, 0x06),
385 /*
386 * MSR_P4_FSB_ESCR0: 0, 1
387 * MSR_P4_FSB_ESCR1: 2, 3
388 */
389
390 P4_OPCODE(P4_EVENT_BSQ_ALLOCATION) = P4_OPCODE_PACK(0x05, 0x07),
391 /*
392 * MSR_P4_BSU_ESCR0: 0, 1
393 */
394
395 P4_OPCODE(P4_EVENT_BSQ_ACTIVE_ENTRIES) = P4_OPCODE_PACK(0x06, 0x07),
396 /*
397 * NOTE: no ESCR name in docs, it's guessed
398 * MSR_P4_BSU_ESCR1: 2, 3
399 */
400
401 P4_OPCODE(P4_EVENT_SSE_INPUT_ASSIST) = P4_OPCODE_PACK(0x34, 0x01),
402 /*
403 * MSR_P4_FIRM_ESCR0: 8, 9
404 * MSR_P4_FIRM_ESCR1: 10, 11
405 */
406
407 P4_OPCODE(P4_EVENT_PACKED_SP_UOP) = P4_OPCODE_PACK(0x08, 0x01),
408 /*
409 * MSR_P4_FIRM_ESCR0: 8, 9
410 * MSR_P4_FIRM_ESCR1: 10, 11
411 */
412
413 P4_OPCODE(P4_EVENT_PACKED_DP_UOP) = P4_OPCODE_PACK(0x0c, 0x01),
414 /*
415 * MSR_P4_FIRM_ESCR0: 8, 9
416 * MSR_P4_FIRM_ESCR1: 10, 11
417 */
418
419 P4_OPCODE(P4_EVENT_SCALAR_SP_UOP) = P4_OPCODE_PACK(0x0a, 0x01),
420 /*
421 * MSR_P4_FIRM_ESCR0: 8, 9
422 * MSR_P4_FIRM_ESCR1: 10, 11
423 */
424
425 P4_OPCODE(P4_EVENT_SCALAR_DP_UOP) = P4_OPCODE_PACK(0x0e, 0x01),
426 /*
427 * MSR_P4_FIRM_ESCR0: 8, 9
428 * MSR_P4_FIRM_ESCR1: 10, 11
429 */
430
431 P4_OPCODE(P4_EVENT_64BIT_MMX_UOP) = P4_OPCODE_PACK(0x02, 0x01),
432 /*
433 * MSR_P4_FIRM_ESCR0: 8, 9
434 * MSR_P4_FIRM_ESCR1: 10, 11
435 */
436
437 P4_OPCODE(P4_EVENT_128BIT_MMX_UOP) = P4_OPCODE_PACK(0x1a, 0x01),
438 /*
439 * MSR_P4_FIRM_ESCR0: 8, 9
440 * MSR_P4_FIRM_ESCR1: 10, 11
441 */
442
443 P4_OPCODE(P4_EVENT_X87_FP_UOP) = P4_OPCODE_PACK(0x04, 0x01),
444 /*
445 * MSR_P4_FIRM_ESCR0: 8, 9
446 * MSR_P4_FIRM_ESCR1: 10, 11
447 */
448
449 P4_OPCODE(P4_EVENT_TC_MISC) = P4_OPCODE_PACK(0x06, 0x01),
450 /*
451 * MSR_P4_TC_ESCR0: 4, 5
452 * MSR_P4_TC_ESCR1: 6, 7
453 */
454
455 P4_OPCODE(P4_EVENT_GLOBAL_POWER_EVENTS) = P4_OPCODE_PACK(0x13, 0x06),
456 /*
457 * MSR_P4_FSB_ESCR0: 0, 1
458 * MSR_P4_FSB_ESCR1: 2, 3
459 */
460
461 P4_OPCODE(P4_EVENT_TC_MS_XFER) = P4_OPCODE_PACK(0x05, 0x00),
462 /*
463 * MSR_P4_MS_ESCR0: 4, 5
464 * MSR_P4_MS_ESCR1: 6, 7
465 */
466
467 P4_OPCODE(P4_EVENT_UOP_QUEUE_WRITES) = P4_OPCODE_PACK(0x09, 0x00),
468 /*
469 * MSR_P4_MS_ESCR0: 4, 5
470 * MSR_P4_MS_ESCR1: 6, 7
471 */
472
473 P4_OPCODE(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x05, 0x02),
474 /*
475 * MSR_P4_TBPU_ESCR0: 4, 5
476 * MSR_P4_TBPU_ESCR1: 6, 7
477 */
478
479 P4_OPCODE(P4_EVENT_RETIRED_BRANCH_TYPE) = P4_OPCODE_PACK(0x04, 0x02),
480 /*
481 * MSR_P4_TBPU_ESCR0: 4, 5
482 * MSR_P4_TBPU_ESCR1: 6, 7
483 */
484
485 P4_OPCODE(P4_EVENT_RESOURCE_STALL) = P4_OPCODE_PACK(0x01, 0x01),
486 /*
487 * MSR_P4_ALF_ESCR0: 12, 13, 16
488 * MSR_P4_ALF_ESCR1: 14, 15, 17
489 */
490
491 P4_OPCODE(P4_EVENT_WC_BUFFER) = P4_OPCODE_PACK(0x05, 0x05),
492 /*
493 * MSR_P4_DAC_ESCR0: 8, 9
494 * MSR_P4_DAC_ESCR1: 10, 11
495 */
496
497 P4_OPCODE(P4_EVENT_B2B_CYCLES) = P4_OPCODE_PACK(0x16, 0x03),
498 /*
499 * MSR_P4_FSB_ESCR0: 0, 1
500 * MSR_P4_FSB_ESCR1: 2, 3
501 */
502
503 P4_OPCODE(P4_EVENT_BNR) = P4_OPCODE_PACK(0x08, 0x03),
504 /*
505 * MSR_P4_FSB_ESCR0: 0, 1
506 * MSR_P4_FSB_ESCR1: 2, 3
507 */
508
509 P4_OPCODE(P4_EVENT_SNOOP) = P4_OPCODE_PACK(0x06, 0x03),
510 /*
511 * MSR_P4_FSB_ESCR0: 0, 1
512 * MSR_P4_FSB_ESCR1: 2, 3
513 */
514
515 P4_OPCODE(P4_EVENT_RESPONSE) = P4_OPCODE_PACK(0x04, 0x03),
516 /*
517 * MSR_P4_FSB_ESCR0: 0, 1
518 * MSR_P4_FSB_ESCR1: 2, 3
519 */
520
521 P4_OPCODE(P4_EVENT_FRONT_END_EVENT) = P4_OPCODE_PACK(0x08, 0x05),
522 /*
523 * MSR_P4_CRU_ESCR2: 12, 13, 16
524 * MSR_P4_CRU_ESCR3: 14, 15, 17
525 */
526
527 P4_OPCODE(P4_EVENT_EXECUTION_EVENT) = P4_OPCODE_PACK(0x0c, 0x05),
528 /*
529 * MSR_P4_CRU_ESCR2: 12, 13, 16
530 * MSR_P4_CRU_ESCR3: 14, 15, 17
531 */
532
533 P4_OPCODE(P4_EVENT_REPLAY_EVENT) = P4_OPCODE_PACK(0x09, 0x05),
534 /*
535 * MSR_P4_CRU_ESCR2: 12, 13, 16
536 * MSR_P4_CRU_ESCR3: 14, 15, 17
537 */
538
539 P4_OPCODE(P4_EVENT_INSTR_RETIRED) = P4_OPCODE_PACK(0x02, 0x04),
540 /*
541 * MSR_P4_CRU_ESCR0: 12, 13, 16
542 * MSR_P4_CRU_ESCR1: 14, 15, 17
543 */
544
545 P4_OPCODE(P4_EVENT_UOPS_RETIRED) = P4_OPCODE_PACK(0x01, 0x04),
546 /*
547 * MSR_P4_CRU_ESCR0: 12, 13, 16
548 * MSR_P4_CRU_ESCR1: 14, 15, 17
549 */
550
551 P4_OPCODE(P4_EVENT_UOP_TYPE) = P4_OPCODE_PACK(0x02, 0x02),
552 /*
553 * MSR_P4_RAT_ESCR0: 12, 13, 16
554 * MSR_P4_RAT_ESCR1: 14, 15, 17
555 */
556
557 P4_OPCODE(P4_EVENT_BRANCH_RETIRED) = P4_OPCODE_PACK(0x06, 0x05),
558 /*
559 * MSR_P4_CRU_ESCR2: 12, 13, 16
560 * MSR_P4_CRU_ESCR3: 14, 15, 17
561 */
562
563 P4_OPCODE(P4_EVENT_MISPRED_BRANCH_RETIRED) = P4_OPCODE_PACK(0x03, 0x04),
564 /*
565 * MSR_P4_CRU_ESCR0: 12, 13, 16
566 * MSR_P4_CRU_ESCR1: 14, 15, 17
567 */
568
569 P4_OPCODE(P4_EVENT_X87_ASSIST) = P4_OPCODE_PACK(0x03, 0x05),
570 /*
571 * MSR_P4_CRU_ESCR2: 12, 13, 16
572 * MSR_P4_CRU_ESCR3: 14, 15, 17
573 */
574
575 P4_OPCODE(P4_EVENT_MACHINE_CLEAR) = P4_OPCODE_PACK(0x02, 0x05),
576 /*
577 * MSR_P4_CRU_ESCR2: 12, 13, 16
578 * MSR_P4_CRU_ESCR3: 14, 15, 17
579 */
580
581 P4_OPCODE(P4_EVENT_INSTR_COMPLETED) = P4_OPCODE_PACK(0x07, 0x04),
582 /*
583 * MSR_P4_CRU_ESCR0: 12, 13, 16
584 * MSR_P4_CRU_ESCR1: 14, 15, 17
585 */
586 };
587
588 /*
589 * a caller should use P4_ESCR_EMASK_NAME helper to
590 * pick the EventMask needed, for example
591 *
592 * P4_ESCR_EMASK_BIT(P4_EVENT_TC_DELIVER_MODE, DD)
593 */
594 enum P4_ESCR_EMASKS {
595 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DD, 0),
596 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DB, 1),
597 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, DI, 2),
598 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BD, 3),
599 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BB, 4),
600 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, BI, 5),
601 P4_GEN_ESCR_EMASK(P4_EVENT_TC_DELIVER_MODE, ID, 6),
602
603 P4_GEN_ESCR_EMASK(P4_EVENT_BPU_FETCH_REQUEST, TCMISS, 0),
604
605 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT, 0),
606 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, MISS, 1),
607 P4_GEN_ESCR_EMASK(P4_EVENT_ITLB_REFERENCE, HIT_UK, 2),
608
609 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, ST_RB_FULL, 2),
610 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_CANCEL, 64K_CONF, 3),
611
612 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, LSC, 0),
613 P4_GEN_ESCR_EMASK(P4_EVENT_MEMORY_COMPLETE, SSC, 1),
614
615 P4_GEN_ESCR_EMASK(P4_EVENT_LOAD_PORT_REPLAY, SPLIT_LD, 1),
616
617 P4_GEN_ESCR_EMASK(P4_EVENT_STORE_PORT_REPLAY, SPLIT_ST, 1),
618
619 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STA, 1),
620 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, NO_STD, 3),
621 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, PARTIAL_DATA, 4),
622 P4_GEN_ESCR_EMASK(P4_EVENT_MOB_LOAD_REPLAY, UNALGN_ADDR, 5),
623
624 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, DTMISS, 0),
625 P4_GEN_ESCR_EMASK(P4_EVENT_PAGE_WALK_TYPE, ITMISS, 1),
626
627 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITS, 0),
628 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITE, 1),
629 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_HITM, 2),
630 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITS, 3),
631 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITE, 4),
632 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_HITM, 5),
633 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_2ndL_MISS, 8),
634 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, RD_3rdL_MISS, 9),
635 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_CACHE_REFERENCE, WR_2ndL_MISS, 10),
636
637 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, DEFAULT, 0),
638 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_READ, 5),
639 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, ALL_WRITE, 6),
640 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_UC, 7),
641 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WC, 8),
642 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WT, 9),
643 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WP, 10),
644 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, MEM_WB, 11),
645 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OWN, 13),
646 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, OTHER, 14),
647 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ALLOCATION, PREFETCH, 15),
648
649 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, DEFAULT, 0),
650 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_READ, 5),
651 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, ALL_WRITE, 6),
652 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_UC, 7),
653 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WC, 8),
654 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WT, 9),
655 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WP, 10),
656 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, MEM_WB, 11),
657 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OWN, 13),
658 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, OTHER, 14),
659 P4_GEN_ESCR_EMASK(P4_EVENT_IOQ_ACTIVE_ENTRIES, PREFETCH, 15),
660
661 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_DRV, 0),
662 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OWN, 1),
663 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DRDY_OTHER, 2),
664 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_DRV, 3),
665 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OWN, 4),
666 P4_GEN_ESCR_EMASK(P4_EVENT_FSB_DATA_ACTIVITY, DBSY_OTHER, 5),
667
668 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE0, 0),
669 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_TYPE1, 1),
670 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN0, 2),
671 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LEN1, 3),
672 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_IO_TYPE, 5),
673 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_LOCK_TYPE, 6),
674 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_CACHE_TYPE, 7),
675 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_SPLIT_TYPE, 8),
676 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_DEM_TYPE, 9),
677 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, REQ_ORD_TYPE, 10),
678 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE0, 11),
679 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE1, 12),
680 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ALLOCATION, MEM_TYPE2, 13),
681
682 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE0, 0),
683 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_TYPE1, 1),
684 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN0, 2),
685 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LEN1, 3),
686 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_IO_TYPE, 5),
687 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_LOCK_TYPE, 6),
688 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_CACHE_TYPE, 7),
689 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_SPLIT_TYPE, 8),
690 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_DEM_TYPE, 9),
691 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, REQ_ORD_TYPE, 10),
692 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE0, 11),
693 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE1, 12),
694 P4_GEN_ESCR_EMASK(P4_EVENT_BSQ_ACTIVE_ENTRIES, MEM_TYPE2, 13),
695
696 P4_GEN_ESCR_EMASK(P4_EVENT_SSE_INPUT_ASSIST, ALL, 15),
697
698 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_SP_UOP, ALL, 15),
699
700 P4_GEN_ESCR_EMASK(P4_EVENT_PACKED_DP_UOP, ALL, 15),
701
702 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_SP_UOP, ALL, 15),
703
704 P4_GEN_ESCR_EMASK(P4_EVENT_SCALAR_DP_UOP, ALL, 15),
705
706 P4_GEN_ESCR_EMASK(P4_EVENT_64BIT_MMX_UOP, ALL, 15),
707
708 P4_GEN_ESCR_EMASK(P4_EVENT_128BIT_MMX_UOP, ALL, 15),
709
710 P4_GEN_ESCR_EMASK(P4_EVENT_X87_FP_UOP, ALL, 15),
711
712 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MISC, FLUSH, 4),
713
714 P4_GEN_ESCR_EMASK(P4_EVENT_GLOBAL_POWER_EVENTS, RUNNING, 0),
715
716 P4_GEN_ESCR_EMASK(P4_EVENT_TC_MS_XFER, CISC, 0),
717
718 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_BUILD, 0),
719 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_TC_DELIVER, 1),
720 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_QUEUE_WRITES, FROM_ROM, 2),
721
722 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CONDITIONAL, 1),
723 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, CALL, 2),
724 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, RETURN, 3),
725 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_MISPRED_BRANCH_TYPE, INDIRECT, 4),
726
727 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CONDITIONAL, 1),
728 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, CALL, 2),
729 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, RETURN, 3),
730 P4_GEN_ESCR_EMASK(P4_EVENT_RETIRED_BRANCH_TYPE, INDIRECT, 4),
731
732 P4_GEN_ESCR_EMASK(P4_EVENT_RESOURCE_STALL, SBFULL, 5),
733
734 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_EVICTS, 0),
735 P4_GEN_ESCR_EMASK(P4_EVENT_WC_BUFFER, WCB_FULL_EVICTS, 1),
736
737 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, NBOGUS, 0),
738 P4_GEN_ESCR_EMASK(P4_EVENT_FRONT_END_EVENT, BOGUS, 1),
739
740 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS0, 0),
741 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS1, 1),
742 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS2, 2),
743 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, NBOGUS3, 3),
744 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS0, 4),
745 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS1, 5),
746 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS2, 6),
747 P4_GEN_ESCR_EMASK(P4_EVENT_EXECUTION_EVENT, BOGUS3, 7),
748
749 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, NBOGUS, 0),
750 P4_GEN_ESCR_EMASK(P4_EVENT_REPLAY_EVENT, BOGUS, 1),
751
752 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSNTAG, 0),
753 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, NBOGUSTAG, 1),
754 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSNTAG, 2),
755 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_RETIRED, BOGUSTAG, 3),
756
757 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, NBOGUS, 0),
758 P4_GEN_ESCR_EMASK(P4_EVENT_UOPS_RETIRED, BOGUS, 1),
759
760 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGLOADS, 1),
761 P4_GEN_ESCR_EMASK(P4_EVENT_UOP_TYPE, TAGSTORES, 2),
762
763 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNP, 0),
764 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMNM, 1),
765 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTP, 2),
766 P4_GEN_ESCR_EMASK(P4_EVENT_BRANCH_RETIRED, MMTM, 3),
767
768 P4_GEN_ESCR_EMASK(P4_EVENT_MISPRED_BRANCH_RETIRED, NBOGUS, 0),
769
770 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSU, 0),
771 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, FPSO, 1),
772 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAO, 2),
773 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, POAU, 3),
774 P4_GEN_ESCR_EMASK(P4_EVENT_X87_ASSIST, PREA, 4),
775
776 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, CLEAR, 0),
777 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, MOCLEAR, 1),
778 P4_GEN_ESCR_EMASK(P4_EVENT_MACHINE_CLEAR, SMCLEAR, 2),
779
780 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, NBOGUS, 0),
781 P4_GEN_ESCR_EMASK(P4_EVENT_INSTR_COMPLETED, BOGUS, 1),
782 };
783
784 /*
785 * Note we have UOP and PEBS bits reserved for now
786 * just in case if we will need them once
787 */
788 #define P4_PEBS_CONFIG_ENABLE (1ULL << 7)
789 #define P4_PEBS_CONFIG_UOP_TAG (1ULL << 8)
790 #define P4_PEBS_CONFIG_METRIC_MASK 0x3FLL
791 #define P4_PEBS_CONFIG_MASK 0xFFLL
792
793 /*
794 * mem: Only counters MSR_IQ_COUNTER4 (16) and
795 * MSR_IQ_COUNTER5 (17) are allowed for PEBS sampling
796 */
797 #define P4_PEBS_ENABLE 0x02000000ULL
798 #define P4_PEBS_ENABLE_UOP_TAG 0x01000000ULL
799
800 #define p4_config_unpack_metric(v) (((u64)(v)) & P4_PEBS_CONFIG_METRIC_MASK)
801 #define p4_config_unpack_pebs(v) (((u64)(v)) & P4_PEBS_CONFIG_MASK)
802
803 #define p4_config_pebs_has(v, mask) (p4_config_unpack_pebs(v) & (mask))
804
805 enum P4_PEBS_METRIC {
806 P4_PEBS_METRIC__none,
807
808 P4_PEBS_METRIC__1stl_cache_load_miss_retired,
809 P4_PEBS_METRIC__2ndl_cache_load_miss_retired,
810 P4_PEBS_METRIC__dtlb_load_miss_retired,
811 P4_PEBS_METRIC__dtlb_store_miss_retired,
812 P4_PEBS_METRIC__dtlb_all_miss_retired,
813 P4_PEBS_METRIC__tagged_mispred_branch,
814 P4_PEBS_METRIC__mob_load_replay_retired,
815 P4_PEBS_METRIC__split_load_retired,
816 P4_PEBS_METRIC__split_store_retired,
817
818 P4_PEBS_METRIC__max
819 };
820
821 /*
822 * Notes on internal configuration of ESCR+CCCR tuples
823 *
824 * Since P4 has quite the different architecture of
825 * performance registers in compare with "architectural"
826 * once and we have on 64 bits to keep configuration
827 * of performance event, the following trick is used.
828 *
829 * 1) Since both ESCR and CCCR registers have only low
830 * 32 bits valuable, we pack them into a single 64 bit
831 * configuration. Low 32 bits of such config correspond
832 * to low 32 bits of CCCR register and high 32 bits
833 * correspond to low 32 bits of ESCR register.
834 *
835 * 2) The meaning of every bit of such config field can
836 * be found in Intel SDM but it should be noted that
837 * we "borrow" some reserved bits for own usage and
838 * clean them or set to a proper value when we do
839 * a real write to hardware registers.
840 *
841 * 3) The format of bits of config is the following
842 * and should be either 0 or set to some predefined
843 * values:
844 *
845 * Low 32 bits
846 * -----------
847 * 0-6: P4_PEBS_METRIC enum
848 * 7-11: reserved
849 * 12: reserved (Enable)
850 * 13-15: reserved (ESCR select)
851 * 16-17: Active Thread
852 * 18: Compare
853 * 19: Complement
854 * 20-23: Threshold
855 * 24: Edge
856 * 25: reserved (FORCE_OVF)
857 * 26: reserved (OVF_PMI_T0)
858 * 27: reserved (OVF_PMI_T1)
859 * 28-29: reserved
860 * 30: reserved (Cascade)
861 * 31: reserved (OVF)
862 *
863 * High 32 bits
864 * ------------
865 * 0: reserved (T1_USR)
866 * 1: reserved (T1_OS)
867 * 2: reserved (T0_USR)
868 * 3: reserved (T0_OS)
869 * 4: Tag Enable
870 * 5-8: Tag Value
871 * 9-24: Event Mask (may use P4_ESCR_EMASK_BIT helper)
872 * 25-30: enum P4_EVENTS
873 * 31: reserved (HT thread)
874 */
875
876 #endif /* PERF_EVENT_P4_H */
877
878
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