1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef __SVM_H
3 #define __SVM_H
4
5 #include <uapi/asm/svm.h>
6 #include <uapi/asm/kvm.h>
7
8 #include <asm/hyperv-tlfs.h>
9
10 /*
11 * 32-bit intercept words in the VMCB Control Area, starting
12 * at Byte offset 000h.
13 */
14
15 enum intercept_words {
16 INTERCEPT_CR = 0,
17 INTERCEPT_DR,
18 INTERCEPT_EXCEPTION,
19 INTERCEPT_WORD3,
20 INTERCEPT_WORD4,
21 INTERCEPT_WORD5,
22 MAX_INTERCEPT,
23 };
24
25 enum {
26 /* Byte offset 000h (word 0) */
27 INTERCEPT_CR0_READ = 0,
28 INTERCEPT_CR3_READ = 3,
29 INTERCEPT_CR4_READ = 4,
30 INTERCEPT_CR8_READ = 8,
31 INTERCEPT_CR0_WRITE = 16,
32 INTERCEPT_CR3_WRITE = 16 + 3,
33 INTERCEPT_CR4_WRITE = 16 + 4,
34 INTERCEPT_CR8_WRITE = 16 + 8,
35 /* Byte offset 004h (word 1) */
36 INTERCEPT_DR0_READ = 32,
37 INTERCEPT_DR1_READ,
38 INTERCEPT_DR2_READ,
39 INTERCEPT_DR3_READ,
40 INTERCEPT_DR4_READ,
41 INTERCEPT_DR5_READ,
42 INTERCEPT_DR6_READ,
43 INTERCEPT_DR7_READ,
44 INTERCEPT_DR0_WRITE = 48,
45 INTERCEPT_DR1_WRITE,
46 INTERCEPT_DR2_WRITE,
47 INTERCEPT_DR3_WRITE,
48 INTERCEPT_DR4_WRITE,
49 INTERCEPT_DR5_WRITE,
50 INTERCEPT_DR6_WRITE,
51 INTERCEPT_DR7_WRITE,
52 /* Byte offset 008h (word 2) */
53 INTERCEPT_EXCEPTION_OFFSET = 64,
54 /* Byte offset 00Ch (word 3) */
55 INTERCEPT_INTR = 96,
56 INTERCEPT_NMI,
57 INTERCEPT_SMI,
58 INTERCEPT_INIT,
59 INTERCEPT_VINTR,
60 INTERCEPT_SELECTIVE_CR0,
61 INTERCEPT_STORE_IDTR,
62 INTERCEPT_STORE_GDTR,
63 INTERCEPT_STORE_LDTR,
64 INTERCEPT_STORE_TR,
65 INTERCEPT_LOAD_IDTR,
66 INTERCEPT_LOAD_GDTR,
67 INTERCEPT_LOAD_LDTR,
68 INTERCEPT_LOAD_TR,
69 INTERCEPT_RDTSC,
70 INTERCEPT_RDPMC,
71 INTERCEPT_PUSHF,
72 INTERCEPT_POPF,
73 INTERCEPT_CPUID,
74 INTERCEPT_RSM,
75 INTERCEPT_IRET,
76 INTERCEPT_INTn,
77 INTERCEPT_INVD,
78 INTERCEPT_PAUSE,
79 INTERCEPT_HLT,
80 INTERCEPT_INVLPG,
81 INTERCEPT_INVLPGA,
82 INTERCEPT_IOIO_PROT,
83 INTERCEPT_MSR_PROT,
84 INTERCEPT_TASK_SWITCH,
85 INTERCEPT_FERR_FREEZE,
86 INTERCEPT_SHUTDOWN,
87 /* Byte offset 010h (word 4) */
88 INTERCEPT_VMRUN = 128,
89 INTERCEPT_VMMCALL,
90 INTERCEPT_VMLOAD,
91 INTERCEPT_VMSAVE,
92 INTERCEPT_STGI,
93 INTERCEPT_CLGI,
94 INTERCEPT_SKINIT,
95 INTERCEPT_RDTSCP,
96 INTERCEPT_ICEBP,
97 INTERCEPT_WBINVD,
98 INTERCEPT_MONITOR,
99 INTERCEPT_MWAIT,
100 INTERCEPT_MWAIT_COND,
101 INTERCEPT_XSETBV,
102 INTERCEPT_RDPRU,
103 TRAP_EFER_WRITE,
104 TRAP_CR0_WRITE,
105 TRAP_CR1_WRITE,
106 TRAP_CR2_WRITE,
107 TRAP_CR3_WRITE,
108 TRAP_CR4_WRITE,
109 TRAP_CR5_WRITE,
110 TRAP_CR6_WRITE,
111 TRAP_CR7_WRITE,
112 TRAP_CR8_WRITE,
113 /* Byte offset 014h (word 5) */
114 INTERCEPT_INVLPGB = 160,
115 INTERCEPT_INVLPGB_ILLEGAL,
116 INTERCEPT_INVPCID,
117 INTERCEPT_MCOMMIT,
118 INTERCEPT_TLBSYNC,
119 };
120
121
122 struct __attribute__ ((__packed__)) vmcb_control_area {
123 u32 intercepts[MAX_INTERCEPT];
124 u32 reserved_1[15 - MAX_INTERCEPT];
125 u16 pause_filter_thresh;
126 u16 pause_filter_count;
127 u64 iopm_base_pa;
128 u64 msrpm_base_pa;
129 u64 tsc_offset;
130 u32 asid;
131 u8 tlb_ctl;
132 u8 reserved_2[3];
133 u32 int_ctl;
134 u32 int_vector;
135 u32 int_state;
136 u8 reserved_3[4];
137 u32 exit_code;
138 u32 exit_code_hi;
139 u64 exit_info_1;
140 u64 exit_info_2;
141 u32 exit_int_info;
142 u32 exit_int_info_err;
143 u64 nested_ctl;
144 u64 avic_vapic_bar;
145 u64 ghcb_gpa;
146 u32 event_inj;
147 u32 event_inj_err;
148 u64 nested_cr3;
149 u64 virt_ext;
150 u32 clean;
151 u32 reserved_5;
152 u64 next_rip;
153 u8 insn_len;
154 u8 insn_bytes[15];
155 u64 avic_backing_page; /* Offset 0xe0 */
156 u8 reserved_6[8]; /* Offset 0xe8 */
157 u64 avic_logical_id; /* Offset 0xf0 */
158 u64 avic_physical_id; /* Offset 0xf8 */
159 u8 reserved_7[8];
160 u64 vmsa_pa; /* Used for an SEV-ES guest */
161 u8 reserved_8[720];
162 /*
163 * Offset 0x3e0, 32 bytes reserved
164 * for use by hypervisor/software.
165 */
166 union {
167 struct hv_vmcb_enlightenments hv_enlightenments;
168 u8 reserved_sw[32];
169 };
170 };
171
172
173 #define TLB_CONTROL_DO_NOTHING 0
174 #define TLB_CONTROL_FLUSH_ALL_ASID 1
175 #define TLB_CONTROL_FLUSH_ASID 3
176 #define TLB_CONTROL_FLUSH_ASID_LOCAL 7
177
178 #define V_TPR_MASK 0x0f
179
180 #define V_IRQ_SHIFT 8
181 #define V_IRQ_MASK (1 << V_IRQ_SHIFT)
182
183 #define V_GIF_SHIFT 9
184 #define V_GIF_MASK (1 << V_GIF_SHIFT)
185
186 #define V_NMI_PENDING_SHIFT 11
187 #define V_NMI_PENDING_MASK (1 << V_NMI_PENDING_SHIFT)
188
189 #define V_NMI_BLOCKING_SHIFT 12
190 #define V_NMI_BLOCKING_MASK (1 << V_NMI_BLOCKING_SHIFT)
191
192 #define V_INTR_PRIO_SHIFT 16
193 #define V_INTR_PRIO_MASK (0x0f << V_INTR_PRIO_SHIFT)
194
195 #define V_IGN_TPR_SHIFT 20
196 #define V_IGN_TPR_MASK (1 << V_IGN_TPR_SHIFT)
197
198 #define V_IRQ_INJECTION_BITS_MASK (V_IRQ_MASK | V_INTR_PRIO_MASK | V_IGN_TPR_MASK)
199
200 #define V_INTR_MASKING_SHIFT 24
201 #define V_INTR_MASKING_MASK (1 << V_INTR_MASKING_SHIFT)
202
203 #define V_GIF_ENABLE_SHIFT 25
204 #define V_GIF_ENABLE_MASK (1 << V_GIF_ENABLE_SHIFT)
205
206 #define V_NMI_ENABLE_SHIFT 26
207 #define V_NMI_ENABLE_MASK (1 << V_NMI_ENABLE_SHIFT)
208
209 #define AVIC_ENABLE_SHIFT 31
210 #define AVIC_ENABLE_MASK (1 << AVIC_ENABLE_SHIFT)
211
212 #define X2APIC_MODE_SHIFT 30
213 #define X2APIC_MODE_MASK (1 << X2APIC_MODE_SHIFT)
214
215 #define LBR_CTL_ENABLE_MASK BIT_ULL(0)
216 #define VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK BIT_ULL(1)
217
218 #define SVM_INTERRUPT_SHADOW_MASK BIT_ULL(0)
219 #define SVM_GUEST_INTERRUPT_MASK BIT_ULL(1)
220
221 #define SVM_IOIO_STR_SHIFT 2
222 #define SVM_IOIO_REP_SHIFT 3
223 #define SVM_IOIO_SIZE_SHIFT 4
224 #define SVM_IOIO_ASIZE_SHIFT 7
225
226 #define SVM_IOIO_TYPE_MASK 1
227 #define SVM_IOIO_STR_MASK (1 << SVM_IOIO_STR_SHIFT)
228 #define SVM_IOIO_REP_MASK (1 << SVM_IOIO_REP_SHIFT)
229 #define SVM_IOIO_SIZE_MASK (7 << SVM_IOIO_SIZE_SHIFT)
230 #define SVM_IOIO_ASIZE_MASK (7 << SVM_IOIO_ASIZE_SHIFT)
231
232 #define SVM_NESTED_CTL_NP_ENABLE BIT(0)
233 #define SVM_NESTED_CTL_SEV_ENABLE BIT(1)
234 #define SVM_NESTED_CTL_SEV_ES_ENABLE BIT(2)
235
236
237 #define SVM_TSC_RATIO_RSVD 0xffffff0000000000ULL
238 #define SVM_TSC_RATIO_MIN 0x0000000000000001ULL
239 #define SVM_TSC_RATIO_MAX 0x000000ffffffffffULL
240 #define SVM_TSC_RATIO_DEFAULT 0x0100000000ULL
241
242
243 /* AVIC */
244 #define AVIC_LOGICAL_ID_ENTRY_GUEST_PHYSICAL_ID_MASK (0xFFULL)
245 #define AVIC_LOGICAL_ID_ENTRY_VALID_BIT 31
246 #define AVIC_LOGICAL_ID_ENTRY_VALID_MASK (1 << 31)
247
248 #define AVIC_PHYSICAL_ID_ENTRY_HOST_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
249 #define AVIC_PHYSICAL_ID_ENTRY_BACKING_PAGE_MASK (0xFFFFFFFFFFULL << 12)
250 #define AVIC_PHYSICAL_ID_ENTRY_IS_RUNNING_MASK (1ULL << 62)
251 #define AVIC_PHYSICAL_ID_ENTRY_VALID_MASK (1ULL << 63)
252 #define AVIC_PHYSICAL_ID_TABLE_SIZE_MASK (0xFFULL)
253
254 #define AVIC_DOORBELL_PHYSICAL_ID_MASK GENMASK_ULL(11, 0)
255
256 #define VMCB_AVIC_APIC_BAR_MASK 0xFFFFFFFFFF000ULL
257
258 #define AVIC_UNACCEL_ACCESS_WRITE_MASK 1
259 #define AVIC_UNACCEL_ACCESS_OFFSET_MASK 0xFF0
260 #define AVIC_UNACCEL_ACCESS_VECTOR_MASK 0xFFFFFFFF
261
262 enum avic_ipi_failure_cause {
263 AVIC_IPI_FAILURE_INVALID_INT_TYPE,
264 AVIC_IPI_FAILURE_TARGET_NOT_RUNNING,
265 AVIC_IPI_FAILURE_INVALID_TARGET,
266 AVIC_IPI_FAILURE_INVALID_BACKING_PAGE,
267 AVIC_IPI_FAILURE_INVALID_IPI_VECTOR,
268 };
269
270 #define AVIC_PHYSICAL_MAX_INDEX_MASK GENMASK_ULL(8, 0)
271
272 /*
273 * For AVIC, the max index allowed for physical APIC ID table is 0xfe (254), as
274 * 0xff is a broadcast to all CPUs, i.e. can't be targeted individually.
275 */
276 #define AVIC_MAX_PHYSICAL_ID 0XFEULL
277
278 /*
279 * For x2AVIC, the max index allowed for physical APIC ID table is 0x1ff (511).
280 */
281 #define X2AVIC_MAX_PHYSICAL_ID 0x1FFUL
282
283 static_assert((AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == AVIC_MAX_PHYSICAL_ID);
284 static_assert((X2AVIC_MAX_PHYSICAL_ID & AVIC_PHYSICAL_MAX_INDEX_MASK) == X2AVIC_MAX_PHYSICAL_ID);
285
286 #define AVIC_HPA_MASK ~((0xFFFULL << 52) | 0xFFF)
287
288 #define SVM_SEV_FEAT_SNP_ACTIVE BIT(0)
289 #define SVM_SEV_FEAT_RESTRICTED_INJECTION BIT(3)
290 #define SVM_SEV_FEAT_ALTERNATE_INJECTION BIT(4)
291 #define SVM_SEV_FEAT_DEBUG_SWAP BIT(5)
292
293 #define SVM_SEV_FEAT_INT_INJ_MODES \
294 (SVM_SEV_FEAT_RESTRICTED_INJECTION | \
295 SVM_SEV_FEAT_ALTERNATE_INJECTION)
296
297 struct vmcb_seg {
298 u16 selector;
299 u16 attrib;
300 u32 limit;
301 u64 base;
302 } __packed;
303
304 /* Save area definition for legacy and SEV-MEM guests */
305 struct vmcb_save_area {
306 struct vmcb_seg es;
307 struct vmcb_seg cs;
308 struct vmcb_seg ss;
309 struct vmcb_seg ds;
310 struct vmcb_seg fs;
311 struct vmcb_seg gs;
312 struct vmcb_seg gdtr;
313 struct vmcb_seg ldtr;
314 struct vmcb_seg idtr;
315 struct vmcb_seg tr;
316 /* Reserved fields are named following their struct offset */
317 u8 reserved_0xa0[42];
318 u8 vmpl;
319 u8 cpl;
320 u8 reserved_0xcc[4];
321 u64 efer;
322 u8 reserved_0xd8[112];
323 u64 cr4;
324 u64 cr3;
325 u64 cr0;
326 u64 dr7;
327 u64 dr6;
328 u64 rflags;
329 u64 rip;
330 u8 reserved_0x180[88];
331 u64 rsp;
332 u64 s_cet;
333 u64 ssp;
334 u64 isst_addr;
335 u64 rax;
336 u64 star;
337 u64 lstar;
338 u64 cstar;
339 u64 sfmask;
340 u64 kernel_gs_base;
341 u64 sysenter_cs;
342 u64 sysenter_esp;
343 u64 sysenter_eip;
344 u64 cr2;
345 u8 reserved_0x248[32];
346 u64 g_pat;
347 u64 dbgctl;
348 u64 br_from;
349 u64 br_to;
350 u64 last_excp_from;
351 u64 last_excp_to;
352 u8 reserved_0x298[72];
353 u64 spec_ctrl; /* Guest version of SPEC_CTRL at 0x2E0 */
354 } __packed;
355
356 /* Save area definition for SEV-ES and SEV-SNP guests */
357 struct sev_es_save_area {
358 struct vmcb_seg es;
359 struct vmcb_seg cs;
360 struct vmcb_seg ss;
361 struct vmcb_seg ds;
362 struct vmcb_seg fs;
363 struct vmcb_seg gs;
364 struct vmcb_seg gdtr;
365 struct vmcb_seg ldtr;
366 struct vmcb_seg idtr;
367 struct vmcb_seg tr;
368 u64 pl0_ssp;
369 u64 pl1_ssp;
370 u64 pl2_ssp;
371 u64 pl3_ssp;
372 u64 u_cet;
373 u8 reserved_0xc8[2];
374 u8 vmpl;
375 u8 cpl;
376 u8 reserved_0xcc[4];
377 u64 efer;
378 u8 reserved_0xd8[104];
379 u64 xss;
380 u64 cr4;
381 u64 cr3;
382 u64 cr0;
383 u64 dr7;
384 u64 dr6;
385 u64 rflags;
386 u64 rip;
387 u64 dr0;
388 u64 dr1;
389 u64 dr2;
390 u64 dr3;
391 u64 dr0_addr_mask;
392 u64 dr1_addr_mask;
393 u64 dr2_addr_mask;
394 u64 dr3_addr_mask;
395 u8 reserved_0x1c0[24];
396 u64 rsp;
397 u64 s_cet;
398 u64 ssp;
399 u64 isst_addr;
400 u64 rax;
401 u64 star;
402 u64 lstar;
403 u64 cstar;
404 u64 sfmask;
405 u64 kernel_gs_base;
406 u64 sysenter_cs;
407 u64 sysenter_esp;
408 u64 sysenter_eip;
409 u64 cr2;
410 u8 reserved_0x248[32];
411 u64 g_pat;
412 u64 dbgctl;
413 u64 br_from;
414 u64 br_to;
415 u64 last_excp_from;
416 u64 last_excp_to;
417 u8 reserved_0x298[80];
418 u32 pkru;
419 u32 tsc_aux;
420 u8 reserved_0x2f0[24];
421 u64 rcx;
422 u64 rdx;
423 u64 rbx;
424 u64 reserved_0x320; /* rsp already available at 0x01d8 */
425 u64 rbp;
426 u64 rsi;
427 u64 rdi;
428 u64 r8;
429 u64 r9;
430 u64 r10;
431 u64 r11;
432 u64 r12;
433 u64 r13;
434 u64 r14;
435 u64 r15;
436 u8 reserved_0x380[16];
437 u64 guest_exit_info_1;
438 u64 guest_exit_info_2;
439 u64 guest_exit_int_info;
440 u64 guest_nrip;
441 u64 sev_features;
442 u64 vintr_ctrl;
443 u64 guest_exit_code;
444 u64 virtual_tom;
445 u64 tlb_id;
446 u64 pcpu_id;
447 u64 event_inj;
448 u64 xcr0;
449 u8 reserved_0x3f0[16];
450
451 /* Floating point area */
452 u64 x87_dp;
453 u32 mxcsr;
454 u16 x87_ftw;
455 u16 x87_fsw;
456 u16 x87_fcw;
457 u16 x87_fop;
458 u16 x87_ds;
459 u16 x87_cs;
460 u64 x87_rip;
461 u8 fpreg_x87[80];
462 u8 fpreg_xmm[256];
463 u8 fpreg_ymm[256];
464 } __packed;
465
466 struct ghcb_save_area {
467 u8 reserved_0x0[203];
468 u8 cpl;
469 u8 reserved_0xcc[116];
470 u64 xss;
471 u8 reserved_0x148[24];
472 u64 dr7;
473 u8 reserved_0x168[16];
474 u64 rip;
475 u8 reserved_0x180[88];
476 u64 rsp;
477 u8 reserved_0x1e0[24];
478 u64 rax;
479 u8 reserved_0x200[264];
480 u64 rcx;
481 u64 rdx;
482 u64 rbx;
483 u8 reserved_0x320[8];
484 u64 rbp;
485 u64 rsi;
486 u64 rdi;
487 u64 r8;
488 u64 r9;
489 u64 r10;
490 u64 r11;
491 u64 r12;
492 u64 r13;
493 u64 r14;
494 u64 r15;
495 u8 reserved_0x380[16];
496 u64 sw_exit_code;
497 u64 sw_exit_info_1;
498 u64 sw_exit_info_2;
499 u64 sw_scratch;
500 u8 reserved_0x3b0[56];
501 u64 xcr0;
502 u8 valid_bitmap[16];
503 u64 x87_state_gpa;
504 } __packed;
505
506 #define GHCB_SHARED_BUF_SIZE 2032
507
508 struct ghcb {
509 struct ghcb_save_area save;
510 u8 reserved_save[2048 - sizeof(struct ghcb_save_area)];
511
512 u8 shared_buffer[GHCB_SHARED_BUF_SIZE];
513
514 u8 reserved_0xff0[10];
515 u16 protocol_version; /* negotiated SEV-ES/GHCB protocol version */
516 u32 ghcb_usage;
517 } __packed;
518
519
520 #define EXPECTED_VMCB_SAVE_AREA_SIZE 744
521 #define EXPECTED_GHCB_SAVE_AREA_SIZE 1032
522 #define EXPECTED_SEV_ES_SAVE_AREA_SIZE 1648
523 #define EXPECTED_VMCB_CONTROL_AREA_SIZE 1024
524 #define EXPECTED_GHCB_SIZE PAGE_SIZE
525
526 #define BUILD_BUG_RESERVED_OFFSET(x, y) \
527 ASSERT_STRUCT_OFFSET(struct x, reserved ## _ ## y, y)
528
529 static inline void __unused_size_checks(void)
530 {
531 BUILD_BUG_ON(sizeof(struct vmcb_save_area) != EXPECTED_VMCB_SAVE_AREA_SIZE);
532 BUILD_BUG_ON(sizeof(struct ghcb_save_area) != EXPECTED_GHCB_SAVE_AREA_SIZE);
533 BUILD_BUG_ON(sizeof(struct sev_es_save_area) != EXPECTED_SEV_ES_SAVE_AREA_SIZE);
534 BUILD_BUG_ON(sizeof(struct vmcb_control_area) != EXPECTED_VMCB_CONTROL_AREA_SIZE);
535 BUILD_BUG_ON(sizeof(struct ghcb) != EXPECTED_GHCB_SIZE);
536
537 /* Check offsets of reserved fields */
538
539 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xa0);
540 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xcc);
541 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0xd8);
542 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x180);
543 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x248);
544 BUILD_BUG_RESERVED_OFFSET(vmcb_save_area, 0x298);
545
546 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xc8);
547 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xcc);
548 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0xd8);
549 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x1c0);
550 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x248);
551 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x298);
552 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x2f0);
553 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x320);
554 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x380);
555 BUILD_BUG_RESERVED_OFFSET(sev_es_save_area, 0x3f0);
556
557 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x0);
558 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0xcc);
559 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x148);
560 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x168);
561 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x180);
562 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x1e0);
563 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x200);
564 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x320);
565 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x380);
566 BUILD_BUG_RESERVED_OFFSET(ghcb_save_area, 0x3b0);
567
568 BUILD_BUG_RESERVED_OFFSET(ghcb, 0xff0);
569 }
570
571 struct vmcb {
572 struct vmcb_control_area control;
573 struct vmcb_save_area save;
574 } __packed;
575
576 #define SVM_CPUID_FUNC 0x8000000a
577
578 #define SVM_SELECTOR_S_SHIFT 4
579 #define SVM_SELECTOR_DPL_SHIFT 5
580 #define SVM_SELECTOR_P_SHIFT 7
581 #define SVM_SELECTOR_AVL_SHIFT 8
582 #define SVM_SELECTOR_L_SHIFT 9
583 #define SVM_SELECTOR_DB_SHIFT 10
584 #define SVM_SELECTOR_G_SHIFT 11
585
586 #define SVM_SELECTOR_TYPE_MASK (0xf)
587 #define SVM_SELECTOR_S_MASK (1 << SVM_SELECTOR_S_SHIFT)
588 #define SVM_SELECTOR_DPL_MASK (3 << SVM_SELECTOR_DPL_SHIFT)
589 #define SVM_SELECTOR_P_MASK (1 << SVM_SELECTOR_P_SHIFT)
590 #define SVM_SELECTOR_AVL_MASK (1 << SVM_SELECTOR_AVL_SHIFT)
591 #define SVM_SELECTOR_L_MASK (1 << SVM_SELECTOR_L_SHIFT)
592 #define SVM_SELECTOR_DB_MASK (1 << SVM_SELECTOR_DB_SHIFT)
593 #define SVM_SELECTOR_G_MASK (1 << SVM_SELECTOR_G_SHIFT)
594
595 #define SVM_SELECTOR_WRITE_MASK (1 << 1)
596 #define SVM_SELECTOR_READ_MASK SVM_SELECTOR_WRITE_MASK
597 #define SVM_SELECTOR_CODE_MASK (1 << 3)
598
599 #define SVM_EVTINJ_VEC_MASK 0xff
600
601 #define SVM_EVTINJ_TYPE_SHIFT 8
602 #define SVM_EVTINJ_TYPE_MASK (7 << SVM_EVTINJ_TYPE_SHIFT)
603
604 #define SVM_EVTINJ_TYPE_INTR (0 << SVM_EVTINJ_TYPE_SHIFT)
605 #define SVM_EVTINJ_TYPE_NMI (2 << SVM_EVTINJ_TYPE_SHIFT)
606 #define SVM_EVTINJ_TYPE_EXEPT (3 << SVM_EVTINJ_TYPE_SHIFT)
607 #define SVM_EVTINJ_TYPE_SOFT (4 << SVM_EVTINJ_TYPE_SHIFT)
608
609 #define SVM_EVTINJ_VALID (1 << 31)
610 #define SVM_EVTINJ_VALID_ERR (1 << 11)
611
612 #define SVM_EXITINTINFO_VEC_MASK SVM_EVTINJ_VEC_MASK
613 #define SVM_EXITINTINFO_TYPE_MASK SVM_EVTINJ_TYPE_MASK
614
615 #define SVM_EXITINTINFO_TYPE_INTR SVM_EVTINJ_TYPE_INTR
616 #define SVM_EXITINTINFO_TYPE_NMI SVM_EVTINJ_TYPE_NMI
617 #define SVM_EXITINTINFO_TYPE_EXEPT SVM_EVTINJ_TYPE_EXEPT
618 #define SVM_EXITINTINFO_TYPE_SOFT SVM_EVTINJ_TYPE_SOFT
619
620 #define SVM_EXITINTINFO_VALID SVM_EVTINJ_VALID
621 #define SVM_EXITINTINFO_VALID_ERR SVM_EVTINJ_VALID_ERR
622
623 #define SVM_EXITINFOSHIFT_TS_REASON_IRET 36
624 #define SVM_EXITINFOSHIFT_TS_REASON_JMP 38
625 #define SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE 44
626
627 #define SVM_EXITINFO_REG_MASK 0x0F
628
629 #define SVM_CR0_SELECTIVE_MASK (X86_CR0_TS | X86_CR0_MP)
630
631 /* GHCB Accessor functions */
632
633 #define GHCB_BITMAP_IDX(field) \
634 (offsetof(struct ghcb_save_area, field) / sizeof(u64))
635
636 #define DEFINE_GHCB_ACCESSORS(field) \
637 static __always_inline bool ghcb_##field##_is_valid(const struct ghcb *ghcb) \
638 { \
639 return test_bit(GHCB_BITMAP_IDX(field), \
640 (unsigned long *)&ghcb->save.valid_bitmap); \
641 } \
642 \
643 static __always_inline u64 ghcb_get_##field(struct ghcb *ghcb) \
644 { \
645 return ghcb->save.field; \
646 } \
647 \
648 static __always_inline u64 ghcb_get_##field##_if_valid(struct ghcb *ghcb) \
649 { \
650 return ghcb_##field##_is_valid(ghcb) ? ghcb->save.field : 0; \
651 } \
652 \
653 static __always_inline void ghcb_set_##field(struct ghcb *ghcb, u64 value) \
654 { \
655 __set_bit(GHCB_BITMAP_IDX(field), \
656 (unsigned long *)&ghcb->save.valid_bitmap); \
657 ghcb->save.field = value; \
658 }
659
660 DEFINE_GHCB_ACCESSORS(cpl)
661 DEFINE_GHCB_ACCESSORS(rip)
662 DEFINE_GHCB_ACCESSORS(rsp)
663 DEFINE_GHCB_ACCESSORS(rax)
664 DEFINE_GHCB_ACCESSORS(rcx)
665 DEFINE_GHCB_ACCESSORS(rdx)
666 DEFINE_GHCB_ACCESSORS(rbx)
667 DEFINE_GHCB_ACCESSORS(rbp)
668 DEFINE_GHCB_ACCESSORS(rsi)
669 DEFINE_GHCB_ACCESSORS(rdi)
670 DEFINE_GHCB_ACCESSORS(r8)
671 DEFINE_GHCB_ACCESSORS(r9)
672 DEFINE_GHCB_ACCESSORS(r10)
673 DEFINE_GHCB_ACCESSORS(r11)
674 DEFINE_GHCB_ACCESSORS(r12)
675 DEFINE_GHCB_ACCESSORS(r13)
676 DEFINE_GHCB_ACCESSORS(r14)
677 DEFINE_GHCB_ACCESSORS(r15)
678 DEFINE_GHCB_ACCESSORS(sw_exit_code)
679 DEFINE_GHCB_ACCESSORS(sw_exit_info_1)
680 DEFINE_GHCB_ACCESSORS(sw_exit_info_2)
681 DEFINE_GHCB_ACCESSORS(sw_scratch)
682 DEFINE_GHCB_ACCESSORS(xcr0)
683
684 #endif
685
Linux® is a registered trademark of Linus Torvalds in the United States and other countries.
TOMOYO® is a registered trademark of NTT DATA CORPORATION.