1 // SPDX-License-Identifier: GPL-2.0-only
2 /* cpu_feature_enabled() cannot be used this early */
3 #define USE_EARLY_PGTABLE_L5
4
5 #include <linux/memblock.h>
6 #include <linux/linkage.h>
7 #include <linux/bitops.h>
8 #include <linux/kernel.h>
9 #include <linux/export.h>
10 #include <linux/percpu.h>
11 #include <linux/string.h>
12 #include <linux/ctype.h>
13 #include <linux/delay.h>
14 #include <linux/sched/mm.h>
15 #include <linux/sched/clock.h>
16 #include <linux/sched/task.h>
17 #include <linux/sched/smt.h>
18 #include <linux/init.h>
19 #include <linux/kprobes.h>
20 #include <linux/kgdb.h>
21 #include <linux/mem_encrypt.h>
22 #include <linux/smp.h>
23 #include <linux/cpu.h>
24 #include <linux/io.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/pgtable.h>
27 #include <linux/stackprotector.h>
28 #include <linux/utsname.h>
29
30 #include <asm/alternative.h>
31 #include <asm/cmdline.h>
32 #include <asm/perf_event.h>
33 #include <asm/mmu_context.h>
34 #include <asm/doublefault.h>
35 #include <asm/archrandom.h>
36 #include <asm/hypervisor.h>
37 #include <asm/processor.h>
38 #include <asm/tlbflush.h>
39 #include <asm/debugreg.h>
40 #include <asm/sections.h>
41 #include <asm/vsyscall.h>
42 #include <linux/topology.h>
43 #include <linux/cpumask.h>
44 #include <linux/atomic.h>
45 #include <asm/proto.h>
46 #include <asm/setup.h>
47 #include <asm/apic.h>
48 #include <asm/desc.h>
49 #include <asm/fpu/api.h>
50 #include <asm/mtrr.h>
51 #include <asm/hwcap2.h>
52 #include <linux/numa.h>
53 #include <asm/numa.h>
54 #include <asm/asm.h>
55 #include <asm/bugs.h>
56 #include <asm/cpu.h>
57 #include <asm/mce.h>
58 #include <asm/msr.h>
59 #include <asm/cacheinfo.h>
60 #include <asm/memtype.h>
61 #include <asm/microcode.h>
62 #include <asm/intel-family.h>
63 #include <asm/cpu_device_id.h>
64 #include <asm/fred.h>
65 #include <asm/uv/uv.h>
66 #include <asm/ia32.h>
67 #include <asm/set_memory.h>
68 #include <asm/traps.h>
69 #include <asm/sev.h>
70 #include <asm/tdx.h>
71 #include <asm/posted_intr.h>
72
73 #include "cpu.h"
74
75 DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
76 EXPORT_PER_CPU_SYMBOL(cpu_info);
77
78 u32 elf_hwcap2 __read_mostly;
79
80 /* Number of siblings per CPU package */
81 unsigned int __max_threads_per_core __ro_after_init = 1;
82 EXPORT_SYMBOL(__max_threads_per_core);
83
84 unsigned int __max_dies_per_package __ro_after_init = 1;
85 EXPORT_SYMBOL(__max_dies_per_package);
86
87 unsigned int __max_logical_packages __ro_after_init = 1;
88 EXPORT_SYMBOL(__max_logical_packages);
89
90 unsigned int __num_cores_per_package __ro_after_init = 1;
91 EXPORT_SYMBOL(__num_cores_per_package);
92
93 unsigned int __num_threads_per_package __ro_after_init = 1;
94 EXPORT_SYMBOL(__num_threads_per_package);
95
96 static struct ppin_info {
97 int feature;
98 int msr_ppin_ctl;
99 int msr_ppin;
100 } ppin_info[] = {
101 [X86_VENDOR_INTEL] = {
102 .feature = X86_FEATURE_INTEL_PPIN,
103 .msr_ppin_ctl = MSR_PPIN_CTL,
104 .msr_ppin = MSR_PPIN
105 },
106 [X86_VENDOR_AMD] = {
107 .feature = X86_FEATURE_AMD_PPIN,
108 .msr_ppin_ctl = MSR_AMD_PPIN_CTL,
109 .msr_ppin = MSR_AMD_PPIN
110 },
111 };
112
113 static const struct x86_cpu_id ppin_cpuids[] = {
114 X86_MATCH_FEATURE(X86_FEATURE_AMD_PPIN, &ppin_info[X86_VENDOR_AMD]),
115 X86_MATCH_FEATURE(X86_FEATURE_INTEL_PPIN, &ppin_info[X86_VENDOR_INTEL]),
116
117 /* Legacy models without CPUID enumeration */
118 X86_MATCH_VFM(INTEL_IVYBRIDGE_X, &ppin_info[X86_VENDOR_INTEL]),
119 X86_MATCH_VFM(INTEL_HASWELL_X, &ppin_info[X86_VENDOR_INTEL]),
120 X86_MATCH_VFM(INTEL_BROADWELL_D, &ppin_info[X86_VENDOR_INTEL]),
121 X86_MATCH_VFM(INTEL_BROADWELL_X, &ppin_info[X86_VENDOR_INTEL]),
122 X86_MATCH_VFM(INTEL_SKYLAKE_X, &ppin_info[X86_VENDOR_INTEL]),
123 X86_MATCH_VFM(INTEL_ICELAKE_X, &ppin_info[X86_VENDOR_INTEL]),
124 X86_MATCH_VFM(INTEL_ICELAKE_D, &ppin_info[X86_VENDOR_INTEL]),
125 X86_MATCH_VFM(INTEL_SAPPHIRERAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
126 X86_MATCH_VFM(INTEL_EMERALDRAPIDS_X, &ppin_info[X86_VENDOR_INTEL]),
127 X86_MATCH_VFM(INTEL_XEON_PHI_KNL, &ppin_info[X86_VENDOR_INTEL]),
128 X86_MATCH_VFM(INTEL_XEON_PHI_KNM, &ppin_info[X86_VENDOR_INTEL]),
129
130 {}
131 };
132
133 static void ppin_init(struct cpuinfo_x86 *c)
134 {
135 const struct x86_cpu_id *id;
136 unsigned long long val;
137 struct ppin_info *info;
138
139 id = x86_match_cpu(ppin_cpuids);
140 if (!id)
141 return;
142
143 /*
144 * Testing the presence of the MSR is not enough. Need to check
145 * that the PPIN_CTL allows reading of the PPIN.
146 */
147 info = (struct ppin_info *)id->driver_data;
148
149 if (rdmsrl_safe(info->msr_ppin_ctl, &val))
150 goto clear_ppin;
151
152 if ((val & 3UL) == 1UL) {
153 /* PPIN locked in disabled mode */
154 goto clear_ppin;
155 }
156
157 /* If PPIN is disabled, try to enable */
158 if (!(val & 2UL)) {
159 wrmsrl_safe(info->msr_ppin_ctl, val | 2UL);
160 rdmsrl_safe(info->msr_ppin_ctl, &val);
161 }
162
163 /* Is the enable bit set? */
164 if (val & 2UL) {
165 c->ppin = __rdmsr(info->msr_ppin);
166 set_cpu_cap(c, info->feature);
167 return;
168 }
169
170 clear_ppin:
171 clear_cpu_cap(c, info->feature);
172 }
173
174 static void default_init(struct cpuinfo_x86 *c)
175 {
176 #ifdef CONFIG_X86_64
177 cpu_detect_cache_sizes(c);
178 #else
179 /* Not much we can do here... */
180 /* Check if at least it has cpuid */
181 if (c->cpuid_level == -1) {
182 /* No cpuid. It must be an ancient CPU */
183 if (c->x86 == 4)
184 strcpy(c->x86_model_id, "486");
185 else if (c->x86 == 3)
186 strcpy(c->x86_model_id, "386");
187 }
188 #endif
189 }
190
191 static const struct cpu_dev default_cpu = {
192 .c_init = default_init,
193 .c_vendor = "Unknown",
194 .c_x86_vendor = X86_VENDOR_UNKNOWN,
195 };
196
197 static const struct cpu_dev *this_cpu = &default_cpu;
198
199 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
200 #ifdef CONFIG_X86_64
201 /*
202 * We need valid kernel segments for data and code in long mode too
203 * IRET will check the segment types kkeil 2000/10/28
204 * Also sysret mandates a special GDT layout
205 *
206 * TLS descriptors are currently at a different place compared to i386.
207 * Hopefully nobody expects them at a fixed place (Wine?)
208 */
209 [GDT_ENTRY_KERNEL32_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
210 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE64, 0, 0xfffff),
211 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA64, 0, 0xfffff),
212 [GDT_ENTRY_DEFAULT_USER32_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
213 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA64 | DESC_USER, 0, 0xfffff),
214 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE64 | DESC_USER, 0, 0xfffff),
215 #else
216 [GDT_ENTRY_KERNEL_CS] = GDT_ENTRY_INIT(DESC_CODE32, 0, 0xfffff),
217 [GDT_ENTRY_KERNEL_DS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
218 [GDT_ENTRY_DEFAULT_USER_CS] = GDT_ENTRY_INIT(DESC_CODE32 | DESC_USER, 0, 0xfffff),
219 [GDT_ENTRY_DEFAULT_USER_DS] = GDT_ENTRY_INIT(DESC_DATA32 | DESC_USER, 0, 0xfffff),
220 /*
221 * Segments used for calling PnP BIOS have byte granularity.
222 * They code segments and data segments have fixed 64k limits,
223 * the transfer segment sizes are set at run time.
224 */
225 [GDT_ENTRY_PNPBIOS_CS32] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
226 [GDT_ENTRY_PNPBIOS_CS16] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
227 [GDT_ENTRY_PNPBIOS_DS] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0xffff),
228 [GDT_ENTRY_PNPBIOS_TS1] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
229 [GDT_ENTRY_PNPBIOS_TS2] = GDT_ENTRY_INIT(DESC_DATA16, 0, 0),
230 /*
231 * The APM segments have byte granularity and their bases
232 * are set at run time. All have 64k limits.
233 */
234 [GDT_ENTRY_APMBIOS_BASE] = GDT_ENTRY_INIT(DESC_CODE32_BIOS, 0, 0xffff),
235 [GDT_ENTRY_APMBIOS_BASE+1] = GDT_ENTRY_INIT(DESC_CODE16, 0, 0xffff),
236 [GDT_ENTRY_APMBIOS_BASE+2] = GDT_ENTRY_INIT(DESC_DATA32_BIOS, 0, 0xffff),
237
238 [GDT_ENTRY_ESPFIX_SS] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
239 [GDT_ENTRY_PERCPU] = GDT_ENTRY_INIT(DESC_DATA32, 0, 0xfffff),
240 #endif
241 } };
242 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
243
244 #ifdef CONFIG_X86_64
245 static int __init x86_nopcid_setup(char *s)
246 {
247 /* nopcid doesn't accept parameters */
248 if (s)
249 return -EINVAL;
250
251 /* do not emit a message if the feature is not present */
252 if (!boot_cpu_has(X86_FEATURE_PCID))
253 return 0;
254
255 setup_clear_cpu_cap(X86_FEATURE_PCID);
256 pr_info("nopcid: PCID feature disabled\n");
257 return 0;
258 }
259 early_param("nopcid", x86_nopcid_setup);
260 #endif
261
262 static int __init x86_noinvpcid_setup(char *s)
263 {
264 /* noinvpcid doesn't accept parameters */
265 if (s)
266 return -EINVAL;
267
268 /* do not emit a message if the feature is not present */
269 if (!boot_cpu_has(X86_FEATURE_INVPCID))
270 return 0;
271
272 setup_clear_cpu_cap(X86_FEATURE_INVPCID);
273 pr_info("noinvpcid: INVPCID feature disabled\n");
274 return 0;
275 }
276 early_param("noinvpcid", x86_noinvpcid_setup);
277
278 #ifdef CONFIG_X86_32
279 static int cachesize_override = -1;
280 static int disable_x86_serial_nr = 1;
281
282 static int __init cachesize_setup(char *str)
283 {
284 get_option(&str, &cachesize_override);
285 return 1;
286 }
287 __setup("cachesize=", cachesize_setup);
288
289 /* Standard macro to see if a specific flag is changeable */
290 static inline int flag_is_changeable_p(u32 flag)
291 {
292 u32 f1, f2;
293
294 /*
295 * Cyrix and IDT cpus allow disabling of CPUID
296 * so the code below may return different results
297 * when it is executed before and after enabling
298 * the CPUID. Add "volatile" to not allow gcc to
299 * optimize the subsequent calls to this function.
300 */
301 asm volatile ("pushfl \n\t"
302 "pushfl \n\t"
303 "popl %0 \n\t"
304 "movl %0, %1 \n\t"
305 "xorl %2, %0 \n\t"
306 "pushl %0 \n\t"
307 "popfl \n\t"
308 "pushfl \n\t"
309 "popl %0 \n\t"
310 "popfl \n\t"
311
312 : "=&r" (f1), "=&r" (f2)
313 : "ir" (flag));
314
315 return ((f1^f2) & flag) != 0;
316 }
317
318 /* Probe for the CPUID instruction */
319 int have_cpuid_p(void)
320 {
321 return flag_is_changeable_p(X86_EFLAGS_ID);
322 }
323
324 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
325 {
326 unsigned long lo, hi;
327
328 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
329 return;
330
331 /* Disable processor serial number: */
332
333 rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
334 lo |= 0x200000;
335 wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
336
337 pr_notice("CPU serial number disabled.\n");
338 clear_cpu_cap(c, X86_FEATURE_PN);
339
340 /* Disabling the serial number may affect the cpuid level */
341 c->cpuid_level = cpuid_eax(0);
342 }
343
344 static int __init x86_serial_nr_setup(char *s)
345 {
346 disable_x86_serial_nr = 0;
347 return 1;
348 }
349 __setup("serialnumber", x86_serial_nr_setup);
350 #else
351 static inline int flag_is_changeable_p(u32 flag)
352 {
353 return 1;
354 }
355 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
356 {
357 }
358 #endif
359
360 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
361 {
362 if (cpu_has(c, X86_FEATURE_SMEP))
363 cr4_set_bits(X86_CR4_SMEP);
364 }
365
366 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
367 {
368 unsigned long eflags = native_save_fl();
369
370 /* This should have been cleared long ago */
371 BUG_ON(eflags & X86_EFLAGS_AC);
372
373 if (cpu_has(c, X86_FEATURE_SMAP))
374 cr4_set_bits(X86_CR4_SMAP);
375 }
376
377 static __always_inline void setup_umip(struct cpuinfo_x86 *c)
378 {
379 /* Check the boot processor, plus build option for UMIP. */
380 if (!cpu_feature_enabled(X86_FEATURE_UMIP))
381 goto out;
382
383 /* Check the current processor's cpuid bits. */
384 if (!cpu_has(c, X86_FEATURE_UMIP))
385 goto out;
386
387 cr4_set_bits(X86_CR4_UMIP);
388
389 pr_info_once("x86/cpu: User Mode Instruction Prevention (UMIP) activated\n");
390
391 return;
392
393 out:
394 /*
395 * Make sure UMIP is disabled in case it was enabled in a
396 * previous boot (e.g., via kexec).
397 */
398 cr4_clear_bits(X86_CR4_UMIP);
399 }
400
401 /* These bits should not change their value after CPU init is finished. */
402 static const unsigned long cr4_pinned_mask = X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_UMIP |
403 X86_CR4_FSGSBASE | X86_CR4_CET | X86_CR4_FRED;
404 static DEFINE_STATIC_KEY_FALSE_RO(cr_pinning);
405 static unsigned long cr4_pinned_bits __ro_after_init;
406
407 void native_write_cr0(unsigned long val)
408 {
409 unsigned long bits_missing = 0;
410
411 set_register:
412 asm volatile("mov %0,%%cr0": "+r" (val) : : "memory");
413
414 if (static_branch_likely(&cr_pinning)) {
415 if (unlikely((val & X86_CR0_WP) != X86_CR0_WP)) {
416 bits_missing = X86_CR0_WP;
417 val |= bits_missing;
418 goto set_register;
419 }
420 /* Warn after we've set the missing bits. */
421 WARN_ONCE(bits_missing, "CR0 WP bit went missing!?\n");
422 }
423 }
424 EXPORT_SYMBOL(native_write_cr0);
425
426 void __no_profile native_write_cr4(unsigned long val)
427 {
428 unsigned long bits_changed = 0;
429
430 set_register:
431 asm volatile("mov %0,%%cr4": "+r" (val) : : "memory");
432
433 if (static_branch_likely(&cr_pinning)) {
434 if (unlikely((val & cr4_pinned_mask) != cr4_pinned_bits)) {
435 bits_changed = (val & cr4_pinned_mask) ^ cr4_pinned_bits;
436 val = (val & ~cr4_pinned_mask) | cr4_pinned_bits;
437 goto set_register;
438 }
439 /* Warn after we've corrected the changed bits. */
440 WARN_ONCE(bits_changed, "pinned CR4 bits changed: 0x%lx!?\n",
441 bits_changed);
442 }
443 }
444 #if IS_MODULE(CONFIG_LKDTM)
445 EXPORT_SYMBOL_GPL(native_write_cr4);
446 #endif
447
448 void cr4_update_irqsoff(unsigned long set, unsigned long clear)
449 {
450 unsigned long newval, cr4 = this_cpu_read(cpu_tlbstate.cr4);
451
452 lockdep_assert_irqs_disabled();
453
454 newval = (cr4 & ~clear) | set;
455 if (newval != cr4) {
456 this_cpu_write(cpu_tlbstate.cr4, newval);
457 __write_cr4(newval);
458 }
459 }
460 EXPORT_SYMBOL(cr4_update_irqsoff);
461
462 /* Read the CR4 shadow. */
463 unsigned long cr4_read_shadow(void)
464 {
465 return this_cpu_read(cpu_tlbstate.cr4);
466 }
467 EXPORT_SYMBOL_GPL(cr4_read_shadow);
468
469 void cr4_init(void)
470 {
471 unsigned long cr4 = __read_cr4();
472
473 if (boot_cpu_has(X86_FEATURE_PCID))
474 cr4 |= X86_CR4_PCIDE;
475 if (static_branch_likely(&cr_pinning))
476 cr4 = (cr4 & ~cr4_pinned_mask) | cr4_pinned_bits;
477
478 __write_cr4(cr4);
479
480 /* Initialize cr4 shadow for this CPU. */
481 this_cpu_write(cpu_tlbstate.cr4, cr4);
482 }
483
484 /*
485 * Once CPU feature detection is finished (and boot params have been
486 * parsed), record any of the sensitive CR bits that are set, and
487 * enable CR pinning.
488 */
489 static void __init setup_cr_pinning(void)
490 {
491 cr4_pinned_bits = this_cpu_read(cpu_tlbstate.cr4) & cr4_pinned_mask;
492 static_key_enable(&cr_pinning.key);
493 }
494
495 static __init int x86_nofsgsbase_setup(char *arg)
496 {
497 /* Require an exact match without trailing characters. */
498 if (strlen(arg))
499 return 0;
500
501 /* Do not emit a message if the feature is not present. */
502 if (!boot_cpu_has(X86_FEATURE_FSGSBASE))
503 return 1;
504
505 setup_clear_cpu_cap(X86_FEATURE_FSGSBASE);
506 pr_info("FSGSBASE disabled via kernel command line\n");
507 return 1;
508 }
509 __setup("nofsgsbase", x86_nofsgsbase_setup);
510
511 /*
512 * Protection Keys are not available in 32-bit mode.
513 */
514 static bool pku_disabled;
515
516 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
517 {
518 if (c == &boot_cpu_data) {
519 if (pku_disabled || !cpu_feature_enabled(X86_FEATURE_PKU))
520 return;
521 /*
522 * Setting CR4.PKE will cause the X86_FEATURE_OSPKE cpuid
523 * bit to be set. Enforce it.
524 */
525 setup_force_cpu_cap(X86_FEATURE_OSPKE);
526
527 } else if (!cpu_feature_enabled(X86_FEATURE_OSPKE)) {
528 return;
529 }
530
531 cr4_set_bits(X86_CR4_PKE);
532 /* Load the default PKRU value */
533 pkru_write_default();
534 }
535
536 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
537 static __init int setup_disable_pku(char *arg)
538 {
539 /*
540 * Do not clear the X86_FEATURE_PKU bit. All of the
541 * runtime checks are against OSPKE so clearing the
542 * bit does nothing.
543 *
544 * This way, we will see "pku" in cpuinfo, but not
545 * "ospke", which is exactly what we want. It shows
546 * that the CPU has PKU, but the OS has not enabled it.
547 * This happens to be exactly how a system would look
548 * if we disabled the config option.
549 */
550 pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
551 pku_disabled = true;
552 return 1;
553 }
554 __setup("nopku", setup_disable_pku);
555 #endif
556
557 #ifdef CONFIG_X86_KERNEL_IBT
558
559 __noendbr u64 ibt_save(bool disable)
560 {
561 u64 msr = 0;
562
563 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
564 rdmsrl(MSR_IA32_S_CET, msr);
565 if (disable)
566 wrmsrl(MSR_IA32_S_CET, msr & ~CET_ENDBR_EN);
567 }
568
569 return msr;
570 }
571
572 __noendbr void ibt_restore(u64 save)
573 {
574 u64 msr;
575
576 if (cpu_feature_enabled(X86_FEATURE_IBT)) {
577 rdmsrl(MSR_IA32_S_CET, msr);
578 msr &= ~CET_ENDBR_EN;
579 msr |= (save & CET_ENDBR_EN);
580 wrmsrl(MSR_IA32_S_CET, msr);
581 }
582 }
583
584 #endif
585
586 static __always_inline void setup_cet(struct cpuinfo_x86 *c)
587 {
588 bool user_shstk, kernel_ibt;
589
590 if (!IS_ENABLED(CONFIG_X86_CET))
591 return;
592
593 kernel_ibt = HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT);
594 user_shstk = cpu_feature_enabled(X86_FEATURE_SHSTK) &&
595 IS_ENABLED(CONFIG_X86_USER_SHADOW_STACK);
596
597 if (!kernel_ibt && !user_shstk)
598 return;
599
600 if (user_shstk)
601 set_cpu_cap(c, X86_FEATURE_USER_SHSTK);
602
603 if (kernel_ibt)
604 wrmsrl(MSR_IA32_S_CET, CET_ENDBR_EN);
605 else
606 wrmsrl(MSR_IA32_S_CET, 0);
607
608 cr4_set_bits(X86_CR4_CET);
609
610 if (kernel_ibt && ibt_selftest()) {
611 pr_err("IBT selftest: Failed!\n");
612 wrmsrl(MSR_IA32_S_CET, 0);
613 setup_clear_cpu_cap(X86_FEATURE_IBT);
614 }
615 }
616
617 __noendbr void cet_disable(void)
618 {
619 if (!(cpu_feature_enabled(X86_FEATURE_IBT) ||
620 cpu_feature_enabled(X86_FEATURE_SHSTK)))
621 return;
622
623 wrmsrl(MSR_IA32_S_CET, 0);
624 wrmsrl(MSR_IA32_U_CET, 0);
625 }
626
627 /*
628 * Some CPU features depend on higher CPUID levels, which may not always
629 * be available due to CPUID level capping or broken virtualization
630 * software. Add those features to this table to auto-disable them.
631 */
632 struct cpuid_dependent_feature {
633 u32 feature;
634 u32 level;
635 };
636
637 static const struct cpuid_dependent_feature
638 cpuid_dependent_features[] = {
639 { X86_FEATURE_MWAIT, 0x00000005 },
640 { X86_FEATURE_DCA, 0x00000009 },
641 { X86_FEATURE_XSAVE, 0x0000000d },
642 { 0, 0 }
643 };
644
645 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
646 {
647 const struct cpuid_dependent_feature *df;
648
649 for (df = cpuid_dependent_features; df->feature; df++) {
650
651 if (!cpu_has(c, df->feature))
652 continue;
653 /*
654 * Note: cpuid_level is set to -1 if unavailable, but
655 * extended_extended_level is set to 0 if unavailable
656 * and the legitimate extended levels are all negative
657 * when signed; hence the weird messing around with
658 * signs here...
659 */
660 if (!((s32)df->level < 0 ?
661 (u32)df->level > (u32)c->extended_cpuid_level :
662 (s32)df->level > (s32)c->cpuid_level))
663 continue;
664
665 clear_cpu_cap(c, df->feature);
666 if (!warn)
667 continue;
668
669 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
670 x86_cap_flag(df->feature), df->level);
671 }
672 }
673
674 /*
675 * Naming convention should be: <Name> [(<Codename>)]
676 * This table only is used unless init_<vendor>() below doesn't set it;
677 * in particular, if CPUID levels 0x80000002..4 are supported, this
678 * isn't used
679 */
680
681 /* Look up CPU names by table lookup. */
682 static const char *table_lookup_model(struct cpuinfo_x86 *c)
683 {
684 #ifdef CONFIG_X86_32
685 const struct legacy_cpu_model_info *info;
686
687 if (c->x86_model >= 16)
688 return NULL; /* Range check */
689
690 if (!this_cpu)
691 return NULL;
692
693 info = this_cpu->legacy_models;
694
695 while (info->family) {
696 if (info->family == c->x86)
697 return info->model_names[c->x86_model];
698 info++;
699 }
700 #endif
701 return NULL; /* Not found */
702 }
703
704 /* Aligned to unsigned long to avoid split lock in atomic bitmap ops */
705 __u32 cpu_caps_cleared[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
706 __u32 cpu_caps_set[NCAPINTS + NBUGINTS] __aligned(sizeof(unsigned long));
707
708 #ifdef CONFIG_X86_32
709 /* The 32-bit entry code needs to find cpu_entry_area. */
710 DEFINE_PER_CPU(struct cpu_entry_area *, cpu_entry_area);
711 #endif
712
713 /* Load the original GDT from the per-cpu structure */
714 void load_direct_gdt(int cpu)
715 {
716 struct desc_ptr gdt_descr;
717
718 gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
719 gdt_descr.size = GDT_SIZE - 1;
720 load_gdt(&gdt_descr);
721 }
722 EXPORT_SYMBOL_GPL(load_direct_gdt);
723
724 /* Load a fixmap remapping of the per-cpu GDT */
725 void load_fixmap_gdt(int cpu)
726 {
727 struct desc_ptr gdt_descr;
728
729 gdt_descr.address = (long)get_cpu_gdt_ro(cpu);
730 gdt_descr.size = GDT_SIZE - 1;
731 load_gdt(&gdt_descr);
732 }
733 EXPORT_SYMBOL_GPL(load_fixmap_gdt);
734
735 /**
736 * switch_gdt_and_percpu_base - Switch to direct GDT and runtime per CPU base
737 * @cpu: The CPU number for which this is invoked
738 *
739 * Invoked during early boot to switch from early GDT and early per CPU to
740 * the direct GDT and the runtime per CPU area. On 32-bit the percpu base
741 * switch is implicit by loading the direct GDT. On 64bit this requires
742 * to update GSBASE.
743 */
744 void __init switch_gdt_and_percpu_base(int cpu)
745 {
746 load_direct_gdt(cpu);
747
748 #ifdef CONFIG_X86_64
749 /*
750 * No need to load %gs. It is already correct.
751 *
752 * Writing %gs on 64bit would zero GSBASE which would make any per
753 * CPU operation up to the point of the wrmsrl() fault.
754 *
755 * Set GSBASE to the new offset. Until the wrmsrl() happens the
756 * early mapping is still valid. That means the GSBASE update will
757 * lose any prior per CPU data which was not copied over in
758 * setup_per_cpu_areas().
759 *
760 * This works even with stackprotector enabled because the
761 * per CPU stack canary is 0 in both per CPU areas.
762 */
763 wrmsrl(MSR_GS_BASE, cpu_kernelmode_gs_base(cpu));
764 #else
765 /*
766 * %fs is already set to __KERNEL_PERCPU, but after switching GDT
767 * it is required to load FS again so that the 'hidden' part is
768 * updated from the new GDT. Up to this point the early per CPU
769 * translation is active. Any content of the early per CPU data
770 * which was not copied over in setup_per_cpu_areas() is lost.
771 */
772 loadsegment(fs, __KERNEL_PERCPU);
773 #endif
774 }
775
776 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
777
778 static void get_model_name(struct cpuinfo_x86 *c)
779 {
780 unsigned int *v;
781 char *p, *q, *s;
782
783 if (c->extended_cpuid_level < 0x80000004)
784 return;
785
786 v = (unsigned int *)c->x86_model_id;
787 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
788 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
789 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
790 c->x86_model_id[48] = 0;
791
792 /* Trim whitespace */
793 p = q = s = &c->x86_model_id[0];
794
795 while (*p == ' ')
796 p++;
797
798 while (*p) {
799 /* Note the last non-whitespace index */
800 if (!isspace(*p))
801 s = q;
802
803 *q++ = *p++;
804 }
805
806 *(s + 1) = '\0';
807 }
808
809 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
810 {
811 unsigned int n, dummy, ebx, ecx, edx, l2size;
812
813 n = c->extended_cpuid_level;
814
815 if (n >= 0x80000005) {
816 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
817 c->x86_cache_size = (ecx>>24) + (edx>>24);
818 #ifdef CONFIG_X86_64
819 /* On K8 L1 TLB is inclusive, so don't count it */
820 c->x86_tlbsize = 0;
821 #endif
822 }
823
824 if (n < 0x80000006) /* Some chips just has a large L1. */
825 return;
826
827 cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
828 l2size = ecx >> 16;
829
830 #ifdef CONFIG_X86_64
831 c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
832 #else
833 /* do processor-specific cache resizing */
834 if (this_cpu->legacy_cache_size)
835 l2size = this_cpu->legacy_cache_size(c, l2size);
836
837 /* Allow user to override all this if necessary. */
838 if (cachesize_override != -1)
839 l2size = cachesize_override;
840
841 if (l2size == 0)
842 return; /* Again, no L2 cache is possible */
843 #endif
844
845 c->x86_cache_size = l2size;
846 }
847
848 u16 __read_mostly tlb_lli_4k[NR_INFO];
849 u16 __read_mostly tlb_lli_2m[NR_INFO];
850 u16 __read_mostly tlb_lli_4m[NR_INFO];
851 u16 __read_mostly tlb_lld_4k[NR_INFO];
852 u16 __read_mostly tlb_lld_2m[NR_INFO];
853 u16 __read_mostly tlb_lld_4m[NR_INFO];
854 u16 __read_mostly tlb_lld_1g[NR_INFO];
855
856 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
857 {
858 if (this_cpu->c_detect_tlb)
859 this_cpu->c_detect_tlb(c);
860
861 pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
862 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
863 tlb_lli_4m[ENTRIES]);
864
865 pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
866 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
867 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
868 }
869
870 static void get_cpu_vendor(struct cpuinfo_x86 *c)
871 {
872 char *v = c->x86_vendor_id;
873 int i;
874
875 for (i = 0; i < X86_VENDOR_NUM; i++) {
876 if (!cpu_devs[i])
877 break;
878
879 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
880 (cpu_devs[i]->c_ident[1] &&
881 !strcmp(v, cpu_devs[i]->c_ident[1]))) {
882
883 this_cpu = cpu_devs[i];
884 c->x86_vendor = this_cpu->c_x86_vendor;
885 return;
886 }
887 }
888
889 pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
890 "CPU: Your system may be unstable.\n", v);
891
892 c->x86_vendor = X86_VENDOR_UNKNOWN;
893 this_cpu = &default_cpu;
894 }
895
896 void cpu_detect(struct cpuinfo_x86 *c)
897 {
898 /* Get vendor name */
899 cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
900 (unsigned int *)&c->x86_vendor_id[0],
901 (unsigned int *)&c->x86_vendor_id[8],
902 (unsigned int *)&c->x86_vendor_id[4]);
903
904 c->x86 = 4;
905 /* Intel-defined flags: level 0x00000001 */
906 if (c->cpuid_level >= 0x00000001) {
907 u32 junk, tfms, cap0, misc;
908
909 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
910 c->x86 = x86_family(tfms);
911 c->x86_model = x86_model(tfms);
912 c->x86_stepping = x86_stepping(tfms);
913
914 if (cap0 & (1<<19)) {
915 c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
916 c->x86_cache_alignment = c->x86_clflush_size;
917 }
918 }
919 }
920
921 static void apply_forced_caps(struct cpuinfo_x86 *c)
922 {
923 int i;
924
925 for (i = 0; i < NCAPINTS + NBUGINTS; i++) {
926 c->x86_capability[i] &= ~cpu_caps_cleared[i];
927 c->x86_capability[i] |= cpu_caps_set[i];
928 }
929 }
930
931 static void init_speculation_control(struct cpuinfo_x86 *c)
932 {
933 /*
934 * The Intel SPEC_CTRL CPUID bit implies IBRS and IBPB support,
935 * and they also have a different bit for STIBP support. Also,
936 * a hypervisor might have set the individual AMD bits even on
937 * Intel CPUs, for finer-grained selection of what's available.
938 */
939 if (cpu_has(c, X86_FEATURE_SPEC_CTRL)) {
940 set_cpu_cap(c, X86_FEATURE_IBRS);
941 set_cpu_cap(c, X86_FEATURE_IBPB);
942 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
943 }
944
945 if (cpu_has(c, X86_FEATURE_INTEL_STIBP))
946 set_cpu_cap(c, X86_FEATURE_STIBP);
947
948 if (cpu_has(c, X86_FEATURE_SPEC_CTRL_SSBD) ||
949 cpu_has(c, X86_FEATURE_VIRT_SSBD))
950 set_cpu_cap(c, X86_FEATURE_SSBD);
951
952 if (cpu_has(c, X86_FEATURE_AMD_IBRS)) {
953 set_cpu_cap(c, X86_FEATURE_IBRS);
954 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
955 }
956
957 if (cpu_has(c, X86_FEATURE_AMD_IBPB))
958 set_cpu_cap(c, X86_FEATURE_IBPB);
959
960 if (cpu_has(c, X86_FEATURE_AMD_STIBP)) {
961 set_cpu_cap(c, X86_FEATURE_STIBP);
962 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
963 }
964
965 if (cpu_has(c, X86_FEATURE_AMD_SSBD)) {
966 set_cpu_cap(c, X86_FEATURE_SSBD);
967 set_cpu_cap(c, X86_FEATURE_MSR_SPEC_CTRL);
968 clear_cpu_cap(c, X86_FEATURE_VIRT_SSBD);
969 }
970 }
971
972 void get_cpu_cap(struct cpuinfo_x86 *c)
973 {
974 u32 eax, ebx, ecx, edx;
975
976 /* Intel-defined flags: level 0x00000001 */
977 if (c->cpuid_level >= 0x00000001) {
978 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
979
980 c->x86_capability[CPUID_1_ECX] = ecx;
981 c->x86_capability[CPUID_1_EDX] = edx;
982 }
983
984 /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
985 if (c->cpuid_level >= 0x00000006)
986 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
987
988 /* Additional Intel-defined flags: level 0x00000007 */
989 if (c->cpuid_level >= 0x00000007) {
990 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
991 c->x86_capability[CPUID_7_0_EBX] = ebx;
992 c->x86_capability[CPUID_7_ECX] = ecx;
993 c->x86_capability[CPUID_7_EDX] = edx;
994
995 /* Check valid sub-leaf index before accessing it */
996 if (eax >= 1) {
997 cpuid_count(0x00000007, 1, &eax, &ebx, &ecx, &edx);
998 c->x86_capability[CPUID_7_1_EAX] = eax;
999 }
1000 }
1001
1002 /* Extended state features: level 0x0000000d */
1003 if (c->cpuid_level >= 0x0000000d) {
1004 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
1005
1006 c->x86_capability[CPUID_D_1_EAX] = eax;
1007 }
1008
1009 /* AMD-defined flags: level 0x80000001 */
1010 eax = cpuid_eax(0x80000000);
1011 c->extended_cpuid_level = eax;
1012
1013 if ((eax & 0xffff0000) == 0x80000000) {
1014 if (eax >= 0x80000001) {
1015 cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
1016
1017 c->x86_capability[CPUID_8000_0001_ECX] = ecx;
1018 c->x86_capability[CPUID_8000_0001_EDX] = edx;
1019 }
1020 }
1021
1022 if (c->extended_cpuid_level >= 0x80000007) {
1023 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
1024
1025 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
1026 c->x86_power = edx;
1027 }
1028
1029 if (c->extended_cpuid_level >= 0x80000008) {
1030 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1031 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
1032 }
1033
1034 if (c->extended_cpuid_level >= 0x8000000a)
1035 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
1036
1037 if (c->extended_cpuid_level >= 0x8000001f)
1038 c->x86_capability[CPUID_8000_001F_EAX] = cpuid_eax(0x8000001f);
1039
1040 if (c->extended_cpuid_level >= 0x80000021)
1041 c->x86_capability[CPUID_8000_0021_EAX] = cpuid_eax(0x80000021);
1042
1043 init_scattered_cpuid_features(c);
1044 init_speculation_control(c);
1045
1046 /*
1047 * Clear/Set all flags overridden by options, after probe.
1048 * This needs to happen each time we re-probe, which may happen
1049 * several times during CPU initialization.
1050 */
1051 apply_forced_caps(c);
1052 }
1053
1054 void get_cpu_address_sizes(struct cpuinfo_x86 *c)
1055 {
1056 u32 eax, ebx, ecx, edx;
1057
1058 if (!cpu_has(c, X86_FEATURE_CPUID) ||
1059 (c->extended_cpuid_level < 0x80000008)) {
1060 if (IS_ENABLED(CONFIG_X86_64)) {
1061 c->x86_clflush_size = 64;
1062 c->x86_phys_bits = 36;
1063 c->x86_virt_bits = 48;
1064 } else {
1065 c->x86_clflush_size = 32;
1066 c->x86_virt_bits = 32;
1067 c->x86_phys_bits = 32;
1068
1069 if (cpu_has(c, X86_FEATURE_PAE) ||
1070 cpu_has(c, X86_FEATURE_PSE36))
1071 c->x86_phys_bits = 36;
1072 }
1073 } else {
1074 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
1075
1076 c->x86_virt_bits = (eax >> 8) & 0xff;
1077 c->x86_phys_bits = eax & 0xff;
1078
1079 /* Provide a sane default if not enumerated: */
1080 if (!c->x86_clflush_size)
1081 c->x86_clflush_size = 32;
1082 }
1083
1084 c->x86_cache_bits = c->x86_phys_bits;
1085 c->x86_cache_alignment = c->x86_clflush_size;
1086 }
1087
1088 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
1089 {
1090 #ifdef CONFIG_X86_32
1091 int i;
1092
1093 /*
1094 * First of all, decide if this is a 486 or higher
1095 * It's a 486 if we can modify the AC flag
1096 */
1097 if (flag_is_changeable_p(X86_EFLAGS_AC))
1098 c->x86 = 4;
1099 else
1100 c->x86 = 3;
1101
1102 for (i = 0; i < X86_VENDOR_NUM; i++)
1103 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
1104 c->x86_vendor_id[0] = 0;
1105 cpu_devs[i]->c_identify(c);
1106 if (c->x86_vendor_id[0]) {
1107 get_cpu_vendor(c);
1108 break;
1109 }
1110 }
1111 #endif
1112 }
1113
1114 #define NO_SPECULATION BIT(0)
1115 #define NO_MELTDOWN BIT(1)
1116 #define NO_SSB BIT(2)
1117 #define NO_L1TF BIT(3)
1118 #define NO_MDS BIT(4)
1119 #define MSBDS_ONLY BIT(5)
1120 #define NO_SWAPGS BIT(6)
1121 #define NO_ITLB_MULTIHIT BIT(7)
1122 #define NO_SPECTRE_V2 BIT(8)
1123 #define NO_MMIO BIT(9)
1124 #define NO_EIBRS_PBRSB BIT(10)
1125 #define NO_BHI BIT(11)
1126
1127 #define VULNWL(vendor, family, model, whitelist) \
1128 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist)
1129
1130 #define VULNWL_INTEL(vfm, whitelist) \
1131 X86_MATCH_VFM(vfm, whitelist)
1132
1133 #define VULNWL_AMD(family, whitelist) \
1134 VULNWL(AMD, family, X86_MODEL_ANY, whitelist)
1135
1136 #define VULNWL_HYGON(family, whitelist) \
1137 VULNWL(HYGON, family, X86_MODEL_ANY, whitelist)
1138
1139 static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
1140 VULNWL(ANY, 4, X86_MODEL_ANY, NO_SPECULATION),
1141 VULNWL(CENTAUR, 5, X86_MODEL_ANY, NO_SPECULATION),
1142 VULNWL(INTEL, 5, X86_MODEL_ANY, NO_SPECULATION),
1143 VULNWL(NSC, 5, X86_MODEL_ANY, NO_SPECULATION),
1144 VULNWL(VORTEX, 5, X86_MODEL_ANY, NO_SPECULATION),
1145 VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION),
1146
1147 /* Intel Family 6 */
1148 VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO),
1149 VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO),
1150 VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO),
1151 VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO),
1152
1153 VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1154 VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT),
1155 VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1156 VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT),
1157 VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT),
1158
1159 VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1160 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1161 VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1162 VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1163 VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1164 VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | NO_ITLB_MULTIHIT),
1165
1166 VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB),
1167
1168 VULNWL_INTEL(INTEL_ATOM_AIRMONT_MID, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | MSBDS_ONLY),
1169 VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT),
1170
1171 VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1172 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO),
1173 VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB),
1174
1175 /*
1176 * Technically, swapgs isn't serializing on AMD (despite it previously
1177 * being documented as such in the APM). But according to AMD, %gs is
1178 * updated non-speculatively, and the issuing of %gs-relative memory
1179 * operands will be blocked until the %gs update completes, which is
1180 * good enough for our purposes.
1181 */
1182
1183 VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB),
1184 VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB),
1185 VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB),
1186
1187 /* AMD Family 0xf - 0x12 */
1188 VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1189 VULNWL_AMD(0x10, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1190 VULNWL_AMD(0x11, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1191 VULNWL_AMD(0x12, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_BHI),
1192
1193 /* FAMILY_ANY must be last, otherwise 0x0f - 0x12 matches won't work */
1194 VULNWL_AMD(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1195 VULNWL_HYGON(X86_FAMILY_ANY, NO_MELTDOWN | NO_L1TF | NO_MDS | NO_SWAPGS | NO_ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB | NO_BHI),
1196
1197 /* Zhaoxin Family 7 */
1198 VULNWL(CENTAUR, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1199 VULNWL(ZHAOXIN, 7, X86_MODEL_ANY, NO_SPECTRE_V2 | NO_SWAPGS | NO_MMIO | NO_BHI),
1200 {}
1201 };
1202
1203 #define VULNBL(vendor, family, model, blacklist) \
1204 X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist)
1205
1206 #define VULNBL_INTEL_STEPPINGS(vfm, steppings, issues) \
1207 X86_MATCH_VFM_STEPPINGS(vfm, steppings, issues)
1208
1209 #define VULNBL_AMD(family, blacklist) \
1210 VULNBL(AMD, family, X86_MODEL_ANY, blacklist)
1211
1212 #define VULNBL_HYGON(family, blacklist) \
1213 VULNBL(HYGON, family, X86_MODEL_ANY, blacklist)
1214
1215 #define SRBDS BIT(0)
1216 /* CPU is affected by X86_BUG_MMIO_STALE_DATA */
1217 #define MMIO BIT(1)
1218 /* CPU is affected by Shared Buffers Data Sampling (SBDS), a variant of X86_BUG_MMIO_STALE_DATA */
1219 #define MMIO_SBDS BIT(2)
1220 /* CPU is affected by RETbleed, speculating where you would not expect it */
1221 #define RETBLEED BIT(3)
1222 /* CPU is affected by SMT (cross-thread) return predictions */
1223 #define SMT_RSB BIT(4)
1224 /* CPU is affected by SRSO */
1225 #define SRSO BIT(5)
1226 /* CPU is affected by GDS */
1227 #define GDS BIT(6)
1228 /* CPU is affected by Register File Data Sampling */
1229 #define RFDS BIT(7)
1230
1231 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst = {
1232 VULNBL_INTEL_STEPPINGS(INTEL_IVYBRIDGE, X86_STEPPING_ANY, SRBDS),
1233 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL, X86_STEPPING_ANY, SRBDS),
1234 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_L, X86_STEPPING_ANY, SRBDS),
1235 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_G, X86_STEPPING_ANY, SRBDS),
1236 VULNBL_INTEL_STEPPINGS(INTEL_HASWELL_X, X86_STEPPING_ANY, MMIO),
1237 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_D, X86_STEPPING_ANY, MMIO),
1238 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_G, X86_STEPPING_ANY, SRBDS),
1239 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL_X, X86_STEPPING_ANY, MMIO),
1240 VULNBL_INTEL_STEPPINGS(INTEL_BROADWELL, X86_STEPPING_ANY, SRBDS),
1241 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_X, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1242 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1243 VULNBL_INTEL_STEPPINGS(INTEL_SKYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1244 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE_L, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1245 VULNBL_INTEL_STEPPINGS(INTEL_KABYLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS | SRBDS),
1246 VULNBL_INTEL_STEPPINGS(INTEL_CANNONLAKE_L, X86_STEPPING_ANY, RETBLEED),
1247 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1248 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_D, X86_STEPPING_ANY, MMIO | GDS),
1249 VULNBL_INTEL_STEPPINGS(INTEL_ICELAKE_X, X86_STEPPING_ANY, MMIO | GDS),
1250 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1251 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPINGS(0x0, 0x0), MMIO | RETBLEED),
1252 VULNBL_INTEL_STEPPINGS(INTEL_COMETLAKE_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED | GDS),
1253 VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE_L, X86_STEPPING_ANY, GDS),
1254 VULNBL_INTEL_STEPPINGS(INTEL_TIGERLAKE, X86_STEPPING_ANY, GDS),
1255 VULNBL_INTEL_STEPPINGS(INTEL_LAKEFIELD, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RETBLEED),
1256 VULNBL_INTEL_STEPPINGS(INTEL_ROCKETLAKE, X86_STEPPING_ANY, MMIO | RETBLEED | GDS),
1257 VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE, X86_STEPPING_ANY, RFDS),
1258 VULNBL_INTEL_STEPPINGS(INTEL_ALDERLAKE_L, X86_STEPPING_ANY, RFDS),
1259 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE, X86_STEPPING_ANY, RFDS),
1260 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_P, X86_STEPPING_ANY, RFDS),
1261 VULNBL_INTEL_STEPPINGS(INTEL_RAPTORLAKE_S, X86_STEPPING_ANY, RFDS),
1262 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GRACEMONT, X86_STEPPING_ANY, RFDS),
1263 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1264 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_D, X86_STEPPING_ANY, MMIO | RFDS),
1265 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_TREMONT_L, X86_STEPPING_ANY, MMIO | MMIO_SBDS | RFDS),
1266 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT, X86_STEPPING_ANY, RFDS),
1267 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_D, X86_STEPPING_ANY, RFDS),
1268 VULNBL_INTEL_STEPPINGS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEPPING_ANY, RFDS),
1269
1270 VULNBL_AMD(0x15, RETBLEED),
1271 VULNBL_AMD(0x16, RETBLEED),
1272 VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO),
1273 VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO),
1274 VULNBL_AMD(0x19, SRSO),
1275 {}
1276 };
1277
1278 static bool __init cpu_matches(const struct x86_cpu_id *table, unsigned long which)
1279 {
1280 const struct x86_cpu_id *m = x86_match_cpu(table);
1281
1282 return m && !!(m->driver_data & which);
1283 }
1284
1285 u64 x86_read_arch_cap_msr(void)
1286 {
1287 u64 x86_arch_cap_msr = 0;
1288
1289 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES))
1290 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, x86_arch_cap_msr);
1291
1292 return x86_arch_cap_msr;
1293 }
1294
1295 static bool arch_cap_mmio_immune(u64 x86_arch_cap_msr)
1296 {
1297 return (x86_arch_cap_msr & ARCH_CAP_FBSDP_NO &&
1298 x86_arch_cap_msr & ARCH_CAP_PSDP_NO &&
1299 x86_arch_cap_msr & ARCH_CAP_SBDR_SSDP_NO);
1300 }
1301
1302 static bool __init vulnerable_to_rfds(u64 x86_arch_cap_msr)
1303 {
1304 /* The "immunity" bit trumps everything else: */
1305 if (x86_arch_cap_msr & ARCH_CAP_RFDS_NO)
1306 return false;
1307
1308 /*
1309 * VMMs set ARCH_CAP_RFDS_CLEAR for processors not in the blacklist to
1310 * indicate that mitigation is needed because guest is running on a
1311 * vulnerable hardware or may migrate to such hardware:
1312 */
1313 if (x86_arch_cap_msr & ARCH_CAP_RFDS_CLEAR)
1314 return true;
1315
1316 /* Only consult the blacklist when there is no enumeration: */
1317 return cpu_matches(cpu_vuln_blacklist, RFDS);
1318 }
1319
1320 static void __init cpu_set_bug_bits(struct cpuinfo_x86 *c)
1321 {
1322 u64 x86_arch_cap_msr = x86_read_arch_cap_msr();
1323
1324 /* Set ITLB_MULTIHIT bug if cpu is not in the whitelist and not mitigated */
1325 if (!cpu_matches(cpu_vuln_whitelist, NO_ITLB_MULTIHIT) &&
1326 !(x86_arch_cap_msr & ARCH_CAP_PSCHANGE_MC_NO))
1327 setup_force_cpu_bug(X86_BUG_ITLB_MULTIHIT);
1328
1329 if (cpu_matches(cpu_vuln_whitelist, NO_SPECULATION))
1330 return;
1331
1332 setup_force_cpu_bug(X86_BUG_SPECTRE_V1);
1333
1334 if (!cpu_matches(cpu_vuln_whitelist, NO_SPECTRE_V2))
1335 setup_force_cpu_bug(X86_BUG_SPECTRE_V2);
1336
1337 if (!cpu_matches(cpu_vuln_whitelist, NO_SSB) &&
1338 !(x86_arch_cap_msr & ARCH_CAP_SSB_NO) &&
1339 !cpu_has(c, X86_FEATURE_AMD_SSB_NO))
1340 setup_force_cpu_bug(X86_BUG_SPEC_STORE_BYPASS);
1341
1342 /*
1343 * AMD's AutoIBRS is equivalent to Intel's eIBRS - use the Intel feature
1344 * flag and protect from vendor-specific bugs via the whitelist.
1345 *
1346 * Don't use AutoIBRS when SNP is enabled because it degrades host
1347 * userspace indirect branch performance.
1348 */
1349 if ((x86_arch_cap_msr & ARCH_CAP_IBRS_ALL) ||
1350 (cpu_has(c, X86_FEATURE_AUTOIBRS) &&
1351 !cpu_feature_enabled(X86_FEATURE_SEV_SNP))) {
1352 setup_force_cpu_cap(X86_FEATURE_IBRS_ENHANCED);
1353 if (!cpu_matches(cpu_vuln_whitelist, NO_EIBRS_PBRSB) &&
1354 !(x86_arch_cap_msr & ARCH_CAP_PBRSB_NO))
1355 setup_force_cpu_bug(X86_BUG_EIBRS_PBRSB);
1356 }
1357
1358 if (!cpu_matches(cpu_vuln_whitelist, NO_MDS) &&
1359 !(x86_arch_cap_msr & ARCH_CAP_MDS_NO)) {
1360 setup_force_cpu_bug(X86_BUG_MDS);
1361 if (cpu_matches(cpu_vuln_whitelist, MSBDS_ONLY))
1362 setup_force_cpu_bug(X86_BUG_MSBDS_ONLY);
1363 }
1364
1365 if (!cpu_matches(cpu_vuln_whitelist, NO_SWAPGS))
1366 setup_force_cpu_bug(X86_BUG_SWAPGS);
1367
1368 /*
1369 * When the CPU is not mitigated for TAA (TAA_NO=0) set TAA bug when:
1370 * - TSX is supported or
1371 * - TSX_CTRL is present
1372 *
1373 * TSX_CTRL check is needed for cases when TSX could be disabled before
1374 * the kernel boot e.g. kexec.
1375 * TSX_CTRL check alone is not sufficient for cases when the microcode
1376 * update is not present or running as guest that don't get TSX_CTRL.
1377 */
1378 if (!(x86_arch_cap_msr & ARCH_CAP_TAA_NO) &&
1379 (cpu_has(c, X86_FEATURE_RTM) ||
1380 (x86_arch_cap_msr & ARCH_CAP_TSX_CTRL_MSR)))
1381 setup_force_cpu_bug(X86_BUG_TAA);
1382
1383 /*
1384 * SRBDS affects CPUs which support RDRAND or RDSEED and are listed
1385 * in the vulnerability blacklist.
1386 *
1387 * Some of the implications and mitigation of Shared Buffers Data
1388 * Sampling (SBDS) are similar to SRBDS. Give SBDS same treatment as
1389 * SRBDS.
1390 */
1391 if ((cpu_has(c, X86_FEATURE_RDRAND) ||
1392 cpu_has(c, X86_FEATURE_RDSEED)) &&
1393 cpu_matches(cpu_vuln_blacklist, SRBDS | MMIO_SBDS))
1394 setup_force_cpu_bug(X86_BUG_SRBDS);
1395
1396 /*
1397 * Processor MMIO Stale Data bug enumeration
1398 *
1399 * Affected CPU list is generally enough to enumerate the vulnerability,
1400 * but for virtualization case check for ARCH_CAP MSR bits also, VMM may
1401 * not want the guest to enumerate the bug.
1402 *
1403 * Set X86_BUG_MMIO_UNKNOWN for CPUs that are neither in the blacklist,
1404 * nor in the whitelist and also don't enumerate MSR ARCH_CAP MMIO bits.
1405 */
1406 if (!arch_cap_mmio_immune(x86_arch_cap_msr)) {
1407 if (cpu_matches(cpu_vuln_blacklist, MMIO))
1408 setup_force_cpu_bug(X86_BUG_MMIO_STALE_DATA);
1409 else if (!cpu_matches(cpu_vuln_whitelist, NO_MMIO))
1410 setup_force_cpu_bug(X86_BUG_MMIO_UNKNOWN);
1411 }
1412
1413 if (!cpu_has(c, X86_FEATURE_BTC_NO)) {
1414 if (cpu_matches(cpu_vuln_blacklist, RETBLEED) || (x86_arch_cap_msr & ARCH_CAP_RSBA))
1415 setup_force_cpu_bug(X86_BUG_RETBLEED);
1416 }
1417
1418 if (cpu_matches(cpu_vuln_blacklist, SMT_RSB))
1419 setup_force_cpu_bug(X86_BUG_SMT_RSB);
1420
1421 if (!cpu_has(c, X86_FEATURE_SRSO_NO)) {
1422 if (cpu_matches(cpu_vuln_blacklist, SRSO))
1423 setup_force_cpu_bug(X86_BUG_SRSO);
1424 }
1425
1426 /*
1427 * Check if CPU is vulnerable to GDS. If running in a virtual machine on
1428 * an affected processor, the VMM may have disabled the use of GATHER by
1429 * disabling AVX2. The only way to do this in HW is to clear XCR0[2],
1430 * which means that AVX will be disabled.
1431 */
1432 if (cpu_matches(cpu_vuln_blacklist, GDS) && !(x86_arch_cap_msr & ARCH_CAP_GDS_NO) &&
1433 boot_cpu_has(X86_FEATURE_AVX))
1434 setup_force_cpu_bug(X86_BUG_GDS);
1435
1436 if (vulnerable_to_rfds(x86_arch_cap_msr))
1437 setup_force_cpu_bug(X86_BUG_RFDS);
1438
1439 /* When virtualized, eIBRS could be hidden, assume vulnerable */
1440 if (!(x86_arch_cap_msr & ARCH_CAP_BHI_NO) &&
1441 !cpu_matches(cpu_vuln_whitelist, NO_BHI) &&
1442 (boot_cpu_has(X86_FEATURE_IBRS_ENHANCED) ||
1443 boot_cpu_has(X86_FEATURE_HYPERVISOR)))
1444 setup_force_cpu_bug(X86_BUG_BHI);
1445
1446 if (cpu_has(c, X86_FEATURE_AMD_IBPB) && !cpu_has(c, X86_FEATURE_AMD_IBPB_RET))
1447 setup_force_cpu_bug(X86_BUG_IBPB_NO_RET);
1448
1449 if (cpu_matches(cpu_vuln_whitelist, NO_MELTDOWN))
1450 return;
1451
1452 /* Rogue Data Cache Load? No! */
1453 if (x86_arch_cap_msr & ARCH_CAP_RDCL_NO)
1454 return;
1455
1456 setup_force_cpu_bug(X86_BUG_CPU_MELTDOWN);
1457
1458 if (cpu_matches(cpu_vuln_whitelist, NO_L1TF))
1459 return;
1460
1461 setup_force_cpu_bug(X86_BUG_L1TF);
1462 }
1463
1464 /*
1465 * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
1466 * unfortunately, that's not true in practice because of early VIA
1467 * chips and (more importantly) broken virtualizers that are not easy
1468 * to detect. In the latter case it doesn't even *fail* reliably, so
1469 * probing for it doesn't even work. Disable it completely on 32-bit
1470 * unless we can find a reliable way to detect all the broken cases.
1471 * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
1472 */
1473 static void detect_nopl(void)
1474 {
1475 #ifdef CONFIG_X86_32
1476 setup_clear_cpu_cap(X86_FEATURE_NOPL);
1477 #else
1478 setup_force_cpu_cap(X86_FEATURE_NOPL);
1479 #endif
1480 }
1481
1482 /*
1483 * We parse cpu parameters early because fpu__init_system() is executed
1484 * before parse_early_param().
1485 */
1486 static void __init cpu_parse_early_param(void)
1487 {
1488 char arg[128];
1489 char *argptr = arg, *opt;
1490 int arglen, taint = 0;
1491
1492 #ifdef CONFIG_X86_32
1493 if (cmdline_find_option_bool(boot_command_line, "no387"))
1494 #ifdef CONFIG_MATH_EMULATION
1495 setup_clear_cpu_cap(X86_FEATURE_FPU);
1496 #else
1497 pr_err("Option 'no387' required CONFIG_MATH_EMULATION enabled.\n");
1498 #endif
1499
1500 if (cmdline_find_option_bool(boot_command_line, "nofxsr"))
1501 setup_clear_cpu_cap(X86_FEATURE_FXSR);
1502 #endif
1503
1504 if (cmdline_find_option_bool(boot_command_line, "noxsave"))
1505 setup_clear_cpu_cap(X86_FEATURE_XSAVE);
1506
1507 if (cmdline_find_option_bool(boot_command_line, "noxsaveopt"))
1508 setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
1509
1510 if (cmdline_find_option_bool(boot_command_line, "noxsaves"))
1511 setup_clear_cpu_cap(X86_FEATURE_XSAVES);
1512
1513 if (cmdline_find_option_bool(boot_command_line, "nousershstk"))
1514 setup_clear_cpu_cap(X86_FEATURE_USER_SHSTK);
1515
1516 arglen = cmdline_find_option(boot_command_line, "clearcpuid", arg, sizeof(arg));
1517 if (arglen <= 0)
1518 return;
1519
1520 pr_info("Clearing CPUID bits:");
1521
1522 while (argptr) {
1523 bool found __maybe_unused = false;
1524 unsigned int bit;
1525
1526 opt = strsep(&argptr, ",");
1527
1528 /*
1529 * Handle naked numbers first for feature flags which don't
1530 * have names.
1531 */
1532 if (!kstrtouint(opt, 10, &bit)) {
1533 if (bit < NCAPINTS * 32) {
1534
1535 /* empty-string, i.e., ""-defined feature flags */
1536 if (!x86_cap_flags[bit])
1537 pr_cont(" " X86_CAP_FMT_NUM, x86_cap_flag_num(bit));
1538 else
1539 pr_cont(" " X86_CAP_FMT, x86_cap_flag(bit));
1540
1541 setup_clear_cpu_cap(bit);
1542 taint++;
1543 }
1544 /*
1545 * The assumption is that there are no feature names with only
1546 * numbers in the name thus go to the next argument.
1547 */
1548 continue;
1549 }
1550
1551 for (bit = 0; bit < 32 * NCAPINTS; bit++) {
1552 if (!x86_cap_flag(bit))
1553 continue;
1554
1555 if (strcmp(x86_cap_flag(bit), opt))
1556 continue;
1557
1558 pr_cont(" %s", opt);
1559 setup_clear_cpu_cap(bit);
1560 taint++;
1561 found = true;
1562 break;
1563 }
1564
1565 if (!found)
1566 pr_cont(" (unknown: %s)", opt);
1567 }
1568 pr_cont("\n");
1569
1570 if (taint)
1571 add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
1572 }
1573
1574 /*
1575 * Do minimum CPU detection early.
1576 * Fields really needed: vendor, cpuid_level, family, model, mask,
1577 * cache alignment.
1578 * The others are not touched to avoid unwanted side effects.
1579 *
1580 * WARNING: this function is only called on the boot CPU. Don't add code
1581 * here that is supposed to run on all CPUs.
1582 */
1583 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
1584 {
1585 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1586 c->extended_cpuid_level = 0;
1587
1588 if (!have_cpuid_p())
1589 identify_cpu_without_cpuid(c);
1590
1591 /* cyrix could have cpuid enabled via c_identify()*/
1592 if (have_cpuid_p()) {
1593 cpu_detect(c);
1594 get_cpu_vendor(c);
1595 intel_unlock_cpuid_leafs(c);
1596 get_cpu_cap(c);
1597 setup_force_cpu_cap(X86_FEATURE_CPUID);
1598 get_cpu_address_sizes(c);
1599 cpu_parse_early_param();
1600
1601 cpu_init_topology(c);
1602
1603 if (this_cpu->c_early_init)
1604 this_cpu->c_early_init(c);
1605
1606 c->cpu_index = 0;
1607 filter_cpuid_features(c, false);
1608
1609 if (this_cpu->c_bsp_init)
1610 this_cpu->c_bsp_init(c);
1611 } else {
1612 setup_clear_cpu_cap(X86_FEATURE_CPUID);
1613 get_cpu_address_sizes(c);
1614 cpu_init_topology(c);
1615 }
1616
1617 setup_force_cpu_cap(X86_FEATURE_ALWAYS);
1618
1619 cpu_set_bug_bits(c);
1620
1621 sld_setup(c);
1622
1623 #ifdef CONFIG_X86_32
1624 /*
1625 * Regardless of whether PCID is enumerated, the SDM says
1626 * that it can't be enabled in 32-bit mode.
1627 */
1628 setup_clear_cpu_cap(X86_FEATURE_PCID);
1629 #endif
1630
1631 /*
1632 * Later in the boot process pgtable_l5_enabled() relies on
1633 * cpu_feature_enabled(X86_FEATURE_LA57). If 5-level paging is not
1634 * enabled by this point we need to clear the feature bit to avoid
1635 * false-positives at the later stage.
1636 *
1637 * pgtable_l5_enabled() can be false here for several reasons:
1638 * - 5-level paging is disabled compile-time;
1639 * - it's 32-bit kernel;
1640 * - machine doesn't support 5-level paging;
1641 * - user specified 'no5lvl' in kernel command line.
1642 */
1643 if (!pgtable_l5_enabled())
1644 setup_clear_cpu_cap(X86_FEATURE_LA57);
1645
1646 detect_nopl();
1647 }
1648
1649 void __init early_cpu_init(void)
1650 {
1651 const struct cpu_dev *const *cdev;
1652 int count = 0;
1653
1654 #ifdef CONFIG_PROCESSOR_SELECT
1655 pr_info("KERNEL supported cpus:\n");
1656 #endif
1657
1658 for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
1659 const struct cpu_dev *cpudev = *cdev;
1660
1661 if (count >= X86_VENDOR_NUM)
1662 break;
1663 cpu_devs[count] = cpudev;
1664 count++;
1665
1666 #ifdef CONFIG_PROCESSOR_SELECT
1667 {
1668 unsigned int j;
1669
1670 for (j = 0; j < 2; j++) {
1671 if (!cpudev->c_ident[j])
1672 continue;
1673 pr_info(" %s %s\n", cpudev->c_vendor,
1674 cpudev->c_ident[j]);
1675 }
1676 }
1677 #endif
1678 }
1679 early_identify_cpu(&boot_cpu_data);
1680 }
1681
1682 static bool detect_null_seg_behavior(void)
1683 {
1684 /*
1685 * Empirically, writing zero to a segment selector on AMD does
1686 * not clear the base, whereas writing zero to a segment
1687 * selector on Intel does clear the base. Intel's behavior
1688 * allows slightly faster context switches in the common case
1689 * where GS is unused by the prev and next threads.
1690 *
1691 * Since neither vendor documents this anywhere that I can see,
1692 * detect it directly instead of hard-coding the choice by
1693 * vendor.
1694 *
1695 * I've designated AMD's behavior as the "bug" because it's
1696 * counterintuitive and less friendly.
1697 */
1698
1699 unsigned long old_base, tmp;
1700 rdmsrl(MSR_FS_BASE, old_base);
1701 wrmsrl(MSR_FS_BASE, 1);
1702 loadsegment(fs, 0);
1703 rdmsrl(MSR_FS_BASE, tmp);
1704 wrmsrl(MSR_FS_BASE, old_base);
1705 return tmp == 0;
1706 }
1707
1708 void check_null_seg_clears_base(struct cpuinfo_x86 *c)
1709 {
1710 /* BUG_NULL_SEG is only relevant with 64bit userspace */
1711 if (!IS_ENABLED(CONFIG_X86_64))
1712 return;
1713
1714 if (cpu_has(c, X86_FEATURE_NULL_SEL_CLR_BASE))
1715 return;
1716
1717 /*
1718 * CPUID bit above wasn't set. If this kernel is still running
1719 * as a HV guest, then the HV has decided not to advertize
1720 * that CPUID bit for whatever reason. For example, one
1721 * member of the migration pool might be vulnerable. Which
1722 * means, the bug is present: set the BUG flag and return.
1723 */
1724 if (cpu_has(c, X86_FEATURE_HYPERVISOR)) {
1725 set_cpu_bug(c, X86_BUG_NULL_SEG);
1726 return;
1727 }
1728
1729 /*
1730 * Zen2 CPUs also have this behaviour, but no CPUID bit.
1731 * 0x18 is the respective family for Hygon.
1732 */
1733 if ((c->x86 == 0x17 || c->x86 == 0x18) &&
1734 detect_null_seg_behavior())
1735 return;
1736
1737 /* All the remaining ones are affected */
1738 set_cpu_bug(c, X86_BUG_NULL_SEG);
1739 }
1740
1741 static void generic_identify(struct cpuinfo_x86 *c)
1742 {
1743 c->extended_cpuid_level = 0;
1744
1745 if (!have_cpuid_p())
1746 identify_cpu_without_cpuid(c);
1747
1748 /* cyrix could have cpuid enabled via c_identify()*/
1749 if (!have_cpuid_p())
1750 return;
1751
1752 cpu_detect(c);
1753
1754 get_cpu_vendor(c);
1755 intel_unlock_cpuid_leafs(c);
1756 get_cpu_cap(c);
1757
1758 get_cpu_address_sizes(c);
1759
1760 get_model_name(c); /* Default name */
1761
1762 /*
1763 * ESPFIX is a strange bug. All real CPUs have it. Paravirt
1764 * systems that run Linux at CPL > 0 may or may not have the
1765 * issue, but, even if they have the issue, there's absolutely
1766 * nothing we can do about it because we can't use the real IRET
1767 * instruction.
1768 *
1769 * NB: For the time being, only 32-bit kernels support
1770 * X86_BUG_ESPFIX as such. 64-bit kernels directly choose
1771 * whether to apply espfix using paravirt hooks. If any
1772 * non-paravirt system ever shows up that does *not* have the
1773 * ESPFIX issue, we can change this.
1774 */
1775 #ifdef CONFIG_X86_32
1776 set_cpu_bug(c, X86_BUG_ESPFIX);
1777 #endif
1778 }
1779
1780 /*
1781 * This does the hard work of actually picking apart the CPU stuff...
1782 */
1783 static void identify_cpu(struct cpuinfo_x86 *c)
1784 {
1785 int i;
1786
1787 c->loops_per_jiffy = loops_per_jiffy;
1788 c->x86_cache_size = 0;
1789 c->x86_vendor = X86_VENDOR_UNKNOWN;
1790 c->x86_model = c->x86_stepping = 0; /* So far unknown... */
1791 c->x86_vendor_id[0] = '\0'; /* Unset */
1792 c->x86_model_id[0] = '\0'; /* Unset */
1793 #ifdef CONFIG_X86_64
1794 c->x86_clflush_size = 64;
1795 c->x86_phys_bits = 36;
1796 c->x86_virt_bits = 48;
1797 #else
1798 c->cpuid_level = -1; /* CPUID not detected */
1799 c->x86_clflush_size = 32;
1800 c->x86_phys_bits = 32;
1801 c->x86_virt_bits = 32;
1802 #endif
1803 c->x86_cache_alignment = c->x86_clflush_size;
1804 memset(&c->x86_capability, 0, sizeof(c->x86_capability));
1805 #ifdef CONFIG_X86_VMX_FEATURE_NAMES
1806 memset(&c->vmx_capability, 0, sizeof(c->vmx_capability));
1807 #endif
1808
1809 generic_identify(c);
1810
1811 cpu_parse_topology(c);
1812
1813 if (this_cpu->c_identify)
1814 this_cpu->c_identify(c);
1815
1816 /* Clear/Set all flags overridden by options, after probe */
1817 apply_forced_caps(c);
1818
1819 /*
1820 * Set default APIC and TSC_DEADLINE MSR fencing flag. AMD and
1821 * Hygon will clear it in ->c_init() below.
1822 */
1823 set_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
1824
1825 /*
1826 * Vendor-specific initialization. In this section we
1827 * canonicalize the feature flags, meaning if there are
1828 * features a certain CPU supports which CPUID doesn't
1829 * tell us, CPUID claiming incorrect flags, or other bugs,
1830 * we handle them here.
1831 *
1832 * At the end of this section, c->x86_capability better
1833 * indicate the features this CPU genuinely supports!
1834 */
1835 if (this_cpu->c_init)
1836 this_cpu->c_init(c);
1837
1838 /* Disable the PN if appropriate */
1839 squash_the_stupid_serial_number(c);
1840
1841 /* Set up SMEP/SMAP/UMIP */
1842 setup_smep(c);
1843 setup_smap(c);
1844 setup_umip(c);
1845
1846 /* Enable FSGSBASE instructions if available. */
1847 if (cpu_has(c, X86_FEATURE_FSGSBASE)) {
1848 cr4_set_bits(X86_CR4_FSGSBASE);
1849 elf_hwcap2 |= HWCAP2_FSGSBASE;
1850 }
1851
1852 /*
1853 * The vendor-specific functions might have changed features.
1854 * Now we do "generic changes."
1855 */
1856
1857 /* Filter out anything that depends on CPUID levels we don't have */
1858 filter_cpuid_features(c, true);
1859
1860 /* If the model name is still unset, do table lookup. */
1861 if (!c->x86_model_id[0]) {
1862 const char *p;
1863 p = table_lookup_model(c);
1864 if (p)
1865 strcpy(c->x86_model_id, p);
1866 else
1867 /* Last resort... */
1868 sprintf(c->x86_model_id, "%02x/%02x",
1869 c->x86, c->x86_model);
1870 }
1871
1872 x86_init_rdrand(c);
1873 setup_pku(c);
1874 setup_cet(c);
1875
1876 /*
1877 * Clear/Set all flags overridden by options, need do it
1878 * before following smp all cpus cap AND.
1879 */
1880 apply_forced_caps(c);
1881
1882 /*
1883 * On SMP, boot_cpu_data holds the common feature set between
1884 * all CPUs; so make sure that we indicate which features are
1885 * common between the CPUs. The first time this routine gets
1886 * executed, c == &boot_cpu_data.
1887 */
1888 if (c != &boot_cpu_data) {
1889 /* AND the already accumulated flags with these */
1890 for (i = 0; i < NCAPINTS; i++)
1891 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1892
1893 /* OR, i.e. replicate the bug flags */
1894 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1895 c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1896 }
1897
1898 ppin_init(c);
1899
1900 /* Init Machine Check Exception if available. */
1901 mcheck_cpu_init(c);
1902
1903 #ifdef CONFIG_NUMA
1904 numa_add_cpu(smp_processor_id());
1905 #endif
1906 }
1907
1908 /*
1909 * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1910 * on 32-bit kernels:
1911 */
1912 #ifdef CONFIG_X86_32
1913 void enable_sep_cpu(void)
1914 {
1915 struct tss_struct *tss;
1916 int cpu;
1917
1918 if (!boot_cpu_has(X86_FEATURE_SEP))
1919 return;
1920
1921 cpu = get_cpu();
1922 tss = &per_cpu(cpu_tss_rw, cpu);
1923
1924 /*
1925 * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1926 * see the big comment in struct x86_hw_tss's definition.
1927 */
1928
1929 tss->x86_tss.ss1 = __KERNEL_CS;
1930 wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1931 wrmsr(MSR_IA32_SYSENTER_ESP, (unsigned long)(cpu_entry_stack(cpu) + 1), 0);
1932 wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1933
1934 put_cpu();
1935 }
1936 #endif
1937
1938 static __init void identify_boot_cpu(void)
1939 {
1940 identify_cpu(&boot_cpu_data);
1941 if (HAS_KERNEL_IBT && cpu_feature_enabled(X86_FEATURE_IBT))
1942 pr_info("CET detected: Indirect Branch Tracking enabled\n");
1943 #ifdef CONFIG_X86_32
1944 enable_sep_cpu();
1945 #endif
1946 cpu_detect_tlb(&boot_cpu_data);
1947 setup_cr_pinning();
1948
1949 tsx_init();
1950 tdx_init();
1951 lkgs_init();
1952 }
1953
1954 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1955 {
1956 BUG_ON(c == &boot_cpu_data);
1957 identify_cpu(c);
1958 #ifdef CONFIG_X86_32
1959 enable_sep_cpu();
1960 #endif
1961 x86_spec_ctrl_setup_ap();
1962 update_srbds_msr();
1963 if (boot_cpu_has_bug(X86_BUG_GDS))
1964 update_gds_msr();
1965
1966 tsx_ap_init();
1967 }
1968
1969 void print_cpu_info(struct cpuinfo_x86 *c)
1970 {
1971 const char *vendor = NULL;
1972
1973 if (c->x86_vendor < X86_VENDOR_NUM) {
1974 vendor = this_cpu->c_vendor;
1975 } else {
1976 if (c->cpuid_level >= 0)
1977 vendor = c->x86_vendor_id;
1978 }
1979
1980 if (vendor && !strstr(c->x86_model_id, vendor))
1981 pr_cont("%s ", vendor);
1982
1983 if (c->x86_model_id[0])
1984 pr_cont("%s", c->x86_model_id);
1985 else
1986 pr_cont("%d86", c->x86);
1987
1988 pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1989
1990 if (c->x86_stepping || c->cpuid_level >= 0)
1991 pr_cont(", stepping: 0x%x)\n", c->x86_stepping);
1992 else
1993 pr_cont(")\n");
1994 }
1995
1996 /*
1997 * clearcpuid= was already parsed in cpu_parse_early_param(). This dummy
1998 * function prevents it from becoming an environment variable for init.
1999 */
2000 static __init int setup_clearcpuid(char *arg)
2001 {
2002 return 1;
2003 }
2004 __setup("clearcpuid=", setup_clearcpuid);
2005
2006 DEFINE_PER_CPU_ALIGNED(struct pcpu_hot, pcpu_hot) = {
2007 .current_task = &init_task,
2008 .preempt_count = INIT_PREEMPT_COUNT,
2009 .top_of_stack = TOP_OF_INIT_STACK,
2010 };
2011 EXPORT_PER_CPU_SYMBOL(pcpu_hot);
2012 EXPORT_PER_CPU_SYMBOL(const_pcpu_hot);
2013
2014 #ifdef CONFIG_X86_64
2015 DEFINE_PER_CPU_FIRST(struct fixed_percpu_data,
2016 fixed_percpu_data) __aligned(PAGE_SIZE) __visible;
2017 EXPORT_PER_CPU_SYMBOL_GPL(fixed_percpu_data);
2018
2019 static void wrmsrl_cstar(unsigned long val)
2020 {
2021 /*
2022 * Intel CPUs do not support 32-bit SYSCALL. Writing to MSR_CSTAR
2023 * is so far ignored by the CPU, but raises a #VE trap in a TDX
2024 * guest. Avoid the pointless write on all Intel CPUs.
2025 */
2026 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
2027 wrmsrl(MSR_CSTAR, val);
2028 }
2029
2030 static inline void idt_syscall_init(void)
2031 {
2032 wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
2033
2034 if (ia32_enabled()) {
2035 wrmsrl_cstar((unsigned long)entry_SYSCALL_compat);
2036 /*
2037 * This only works on Intel CPUs.
2038 * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
2039 * This does not cause SYSENTER to jump to the wrong location, because
2040 * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
2041 */
2042 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
2043 wrmsrl_safe(MSR_IA32_SYSENTER_ESP,
2044 (unsigned long)(cpu_entry_stack(smp_processor_id()) + 1));
2045 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
2046 } else {
2047 wrmsrl_cstar((unsigned long)entry_SYSCALL32_ignore);
2048 wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
2049 wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
2050 wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
2051 }
2052
2053 /*
2054 * Flags to clear on syscall; clear as much as possible
2055 * to minimize user space-kernel interference.
2056 */
2057 wrmsrl(MSR_SYSCALL_MASK,
2058 X86_EFLAGS_CF|X86_EFLAGS_PF|X86_EFLAGS_AF|
2059 X86_EFLAGS_ZF|X86_EFLAGS_SF|X86_EFLAGS_TF|
2060 X86_EFLAGS_IF|X86_EFLAGS_DF|X86_EFLAGS_OF|
2061 X86_EFLAGS_IOPL|X86_EFLAGS_NT|X86_EFLAGS_RF|
2062 X86_EFLAGS_AC|X86_EFLAGS_ID);
2063 }
2064
2065 /* May not be marked __init: used by software suspend */
2066 void syscall_init(void)
2067 {
2068 /* The default user and kernel segments */
2069 wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
2070
2071 /*
2072 * Except the IA32_STAR MSR, there is NO need to setup SYSCALL and
2073 * SYSENTER MSRs for FRED, because FRED uses the ring 3 FRED
2074 * entrypoint for SYSCALL and SYSENTER, and ERETU is the only legit
2075 * instruction to return to ring 3 (both sysexit and sysret cause
2076 * #UD when FRED is enabled).
2077 */
2078 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2079 idt_syscall_init();
2080 }
2081
2082 #else /* CONFIG_X86_64 */
2083
2084 #ifdef CONFIG_STACKPROTECTOR
2085 DEFINE_PER_CPU(unsigned long, __stack_chk_guard);
2086 EXPORT_PER_CPU_SYMBOL(__stack_chk_guard);
2087 #endif
2088
2089 #endif /* CONFIG_X86_64 */
2090
2091 /*
2092 * Clear all 6 debug registers:
2093 */
2094 static void clear_all_debug_regs(void)
2095 {
2096 int i;
2097
2098 for (i = 0; i < 8; i++) {
2099 /* Ignore db4, db5 */
2100 if ((i == 4) || (i == 5))
2101 continue;
2102
2103 set_debugreg(0, i);
2104 }
2105 }
2106
2107 #ifdef CONFIG_KGDB
2108 /*
2109 * Restore debug regs if using kgdbwait and you have a kernel debugger
2110 * connection established.
2111 */
2112 static void dbg_restore_debug_regs(void)
2113 {
2114 if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
2115 arch_kgdb_ops.correct_hw_break();
2116 }
2117 #else /* ! CONFIG_KGDB */
2118 #define dbg_restore_debug_regs()
2119 #endif /* ! CONFIG_KGDB */
2120
2121 static inline void setup_getcpu(int cpu)
2122 {
2123 unsigned long cpudata = vdso_encode_cpunode(cpu, early_cpu_to_node(cpu));
2124 struct desc_struct d = { };
2125
2126 if (boot_cpu_has(X86_FEATURE_RDTSCP) || boot_cpu_has(X86_FEATURE_RDPID))
2127 wrmsr(MSR_TSC_AUX, cpudata, 0);
2128
2129 /* Store CPU and node number in limit. */
2130 d.limit0 = cpudata;
2131 d.limit1 = cpudata >> 16;
2132
2133 d.type = 5; /* RO data, expand down, accessed */
2134 d.dpl = 3; /* Visible to user code */
2135 d.s = 1; /* Not a system segment */
2136 d.p = 1; /* Present */
2137 d.d = 1; /* 32-bit */
2138
2139 write_gdt_entry(get_cpu_gdt_rw(cpu), GDT_ENTRY_CPUNODE, &d, DESCTYPE_S);
2140 }
2141
2142 #ifdef CONFIG_X86_64
2143 static inline void tss_setup_ist(struct tss_struct *tss)
2144 {
2145 /* Set up the per-CPU TSS IST stacks */
2146 tss->x86_tss.ist[IST_INDEX_DF] = __this_cpu_ist_top_va(DF);
2147 tss->x86_tss.ist[IST_INDEX_NMI] = __this_cpu_ist_top_va(NMI);
2148 tss->x86_tss.ist[IST_INDEX_DB] = __this_cpu_ist_top_va(DB);
2149 tss->x86_tss.ist[IST_INDEX_MCE] = __this_cpu_ist_top_va(MCE);
2150 /* Only mapped when SEV-ES is active */
2151 tss->x86_tss.ist[IST_INDEX_VC] = __this_cpu_ist_top_va(VC);
2152 }
2153 #else /* CONFIG_X86_64 */
2154 static inline void tss_setup_ist(struct tss_struct *tss) { }
2155 #endif /* !CONFIG_X86_64 */
2156
2157 static inline void tss_setup_io_bitmap(struct tss_struct *tss)
2158 {
2159 tss->x86_tss.io_bitmap_base = IO_BITMAP_OFFSET_INVALID;
2160
2161 #ifdef CONFIG_X86_IOPL_IOPERM
2162 tss->io_bitmap.prev_max = 0;
2163 tss->io_bitmap.prev_sequence = 0;
2164 memset(tss->io_bitmap.bitmap, 0xff, sizeof(tss->io_bitmap.bitmap));
2165 /*
2166 * Invalidate the extra array entry past the end of the all
2167 * permission bitmap as required by the hardware.
2168 */
2169 tss->io_bitmap.mapall[IO_BITMAP_LONGS] = ~0UL;
2170 #endif
2171 }
2172
2173 /*
2174 * Setup everything needed to handle exceptions from the IDT, including the IST
2175 * exceptions which use paranoid_entry().
2176 */
2177 void cpu_init_exception_handling(void)
2178 {
2179 struct tss_struct *tss = this_cpu_ptr(&cpu_tss_rw);
2180 int cpu = raw_smp_processor_id();
2181
2182 /* paranoid_entry() gets the CPU number from the GDT */
2183 setup_getcpu(cpu);
2184
2185 /* For IDT mode, IST vectors need to be set in TSS. */
2186 if (!cpu_feature_enabled(X86_FEATURE_FRED))
2187 tss_setup_ist(tss);
2188 tss_setup_io_bitmap(tss);
2189 set_tss_desc(cpu, &get_cpu_entry_area(cpu)->tss.x86_tss);
2190
2191 load_TR_desc();
2192
2193 /* GHCB needs to be setup to handle #VC. */
2194 setup_ghcb();
2195
2196 if (cpu_feature_enabled(X86_FEATURE_FRED))
2197 cpu_init_fred_exceptions();
2198 else
2199 load_current_idt();
2200 }
2201
2202 /*
2203 * cpu_init() initializes state that is per-CPU. Some data is already
2204 * initialized (naturally) in the bootstrap process, such as the GDT. We
2205 * reload it nevertheless, this function acts as a 'CPU state barrier',
2206 * nothing should get across.
2207 */
2208 void cpu_init(void)
2209 {
2210 struct task_struct *cur = current;
2211 int cpu = raw_smp_processor_id();
2212
2213 #ifdef CONFIG_NUMA
2214 if (this_cpu_read(numa_node) == 0 &&
2215 early_cpu_to_node(cpu) != NUMA_NO_NODE)
2216 set_numa_node(early_cpu_to_node(cpu));
2217 #endif
2218 pr_debug("Initializing CPU#%d\n", cpu);
2219
2220 if (IS_ENABLED(CONFIG_X86_64) || cpu_feature_enabled(X86_FEATURE_VME) ||
2221 boot_cpu_has(X86_FEATURE_TSC) || boot_cpu_has(X86_FEATURE_DE))
2222 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
2223
2224 if (IS_ENABLED(CONFIG_X86_64)) {
2225 loadsegment(fs, 0);
2226 memset(cur->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
2227 syscall_init();
2228
2229 wrmsrl(MSR_FS_BASE, 0);
2230 wrmsrl(MSR_KERNEL_GS_BASE, 0);
2231 barrier();
2232
2233 x2apic_setup();
2234
2235 intel_posted_msi_init();
2236 }
2237
2238 mmgrab(&init_mm);
2239 cur->active_mm = &init_mm;
2240 BUG_ON(cur->mm);
2241 initialize_tlbstate_and_flush();
2242 enter_lazy_tlb(&init_mm, cur);
2243
2244 /*
2245 * sp0 points to the entry trampoline stack regardless of what task
2246 * is running.
2247 */
2248 load_sp0((unsigned long)(cpu_entry_stack(cpu) + 1));
2249
2250 load_mm_ldt(&init_mm);
2251
2252 clear_all_debug_regs();
2253 dbg_restore_debug_regs();
2254
2255 doublefault_init_cpu_tss();
2256
2257 if (is_uv_system())
2258 uv_cpu_init();
2259
2260 load_fixmap_gdt(cpu);
2261 }
2262
2263 #ifdef CONFIG_MICROCODE_LATE_LOADING
2264 /**
2265 * store_cpu_caps() - Store a snapshot of CPU capabilities
2266 * @curr_info: Pointer where to store it
2267 *
2268 * Returns: None
2269 */
2270 void store_cpu_caps(struct cpuinfo_x86 *curr_info)
2271 {
2272 /* Reload CPUID max function as it might've changed. */
2273 curr_info->cpuid_level = cpuid_eax(0);
2274
2275 /* Copy all capability leafs and pick up the synthetic ones. */
2276 memcpy(&curr_info->x86_capability, &boot_cpu_data.x86_capability,
2277 sizeof(curr_info->x86_capability));
2278
2279 /* Get the hardware CPUID leafs */
2280 get_cpu_cap(curr_info);
2281 }
2282
2283 /**
2284 * microcode_check() - Check if any CPU capabilities changed after an update.
2285 * @prev_info: CPU capabilities stored before an update.
2286 *
2287 * The microcode loader calls this upon late microcode load to recheck features,
2288 * only when microcode has been updated. Caller holds and CPU hotplug lock.
2289 *
2290 * Return: None
2291 */
2292 void microcode_check(struct cpuinfo_x86 *prev_info)
2293 {
2294 struct cpuinfo_x86 curr_info;
2295
2296 perf_check_microcode();
2297
2298 amd_check_microcode();
2299
2300 store_cpu_caps(&curr_info);
2301
2302 if (!memcmp(&prev_info->x86_capability, &curr_info.x86_capability,
2303 sizeof(prev_info->x86_capability)))
2304 return;
2305
2306 pr_warn("x86/CPU: CPU features have changed after loading microcode, but might not take effect.\n");
2307 pr_warn("x86/CPU: Please consider either early loading through initrd/built-in or a potential BIOS update.\n");
2308 }
2309 #endif
2310
2311 /*
2312 * Invoked from core CPU hotplug code after hotplug operations
2313 */
2314 void arch_smt_update(void)
2315 {
2316 /* Handle the speculative execution misfeatures */
2317 cpu_bugs_smt_update();
2318 /* Check whether IPI broadcasting can be enabled */
2319 apic_smt_update();
2320 }
2321
2322 void __init arch_cpu_finalize_init(void)
2323 {
2324 struct cpuinfo_x86 *c = this_cpu_ptr(&cpu_info);
2325
2326 identify_boot_cpu();
2327
2328 select_idle_routine();
2329
2330 /*
2331 * identify_boot_cpu() initialized SMT support information, let the
2332 * core code know.
2333 */
2334 cpu_smt_set_num_threads(__max_threads_per_core, __max_threads_per_core);
2335
2336 if (!IS_ENABLED(CONFIG_SMP)) {
2337 pr_info("CPU: ");
2338 print_cpu_info(&boot_cpu_data);
2339 }
2340
2341 cpu_select_mitigations();
2342
2343 arch_smt_update();
2344
2345 if (IS_ENABLED(CONFIG_X86_32)) {
2346 /*
2347 * Check whether this is a real i386 which is not longer
2348 * supported and fixup the utsname.
2349 */
2350 if (boot_cpu_data.x86 < 4)
2351 panic("Kernel requires i486+ for 'invlpg' and other features");
2352
2353 init_utsname()->machine[1] =
2354 '' + (boot_cpu_data.x86 > 6 ? 6 : boot_cpu_data.x86);
2355 }
2356
2357 /*
2358 * Must be before alternatives because it might set or clear
2359 * feature bits.
2360 */
2361 fpu__init_system();
2362 fpu__init_cpu();
2363
2364 /*
2365 * Ensure that access to the per CPU representation has the initial
2366 * boot CPU configuration.
2367 */
2368 *c = boot_cpu_data;
2369 c->initialized = true;
2370
2371 alternative_instructions();
2372
2373 if (IS_ENABLED(CONFIG_X86_64)) {
2374 /*
2375 * Make sure the first 2MB area is not mapped by huge pages
2376 * There are typically fixed size MTRRs in there and overlapping
2377 * MTRRs into large pages causes slow downs.
2378 *
2379 * Right now we don't do that with gbpages because there seems
2380 * very little benefit for that case.
2381 */
2382 if (!direct_gbpages)
2383 set_memory_4k((unsigned long)__va(0), 1);
2384 } else {
2385 fpu__init_check_bugs();
2386 }
2387
2388 /*
2389 * This needs to be called before any devices perform DMA
2390 * operations that might use the SWIOTLB bounce buffers. It will
2391 * mark the bounce buffers as decrypted so that their usage will
2392 * not cause "plain-text" data to be decrypted when accessed. It
2393 * must be called after late_time_init() so that Hyper-V x86/x64
2394 * hypercalls work when the SWIOTLB bounce buffers are decrypted.
2395 */
2396 mem_encrypt_init();
2397 }
2398
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