1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Hygon Processor Support for Linux
4 *
5 * Copyright (C) 2018 Chengdu Haiguang IC Design Co., Ltd.
6 *
7 * Author: Pu Wen <puwen@hygon.cn>
8 */
9 #include <linux/io.h>
10
11 #include <asm/apic.h>
12 #include <asm/cpu.h>
13 #include <asm/smp.h>
14 #include <asm/numa.h>
15 #include <asm/cacheinfo.h>
16 #include <asm/spec-ctrl.h>
17 #include <asm/delay.h>
18
19 #include "cpu.h"
20
21 #ifdef CONFIG_NUMA
22 /*
23 * To workaround broken NUMA config. Read the comment in
24 * srat_detect_node().
25 */
26 static int nearby_node(int apicid)
27 {
28 int i, node;
29
30 for (i = apicid - 1; i >= 0; i--) {
31 node = __apicid_to_node[i];
32 if (node != NUMA_NO_NODE && node_online(node))
33 return node;
34 }
35 for (i = apicid + 1; i < MAX_LOCAL_APIC; i++) {
36 node = __apicid_to_node[i];
37 if (node != NUMA_NO_NODE && node_online(node))
38 return node;
39 }
40 return first_node(node_online_map); /* Shouldn't happen */
41 }
42 #endif
43
44 static void srat_detect_node(struct cpuinfo_x86 *c)
45 {
46 #ifdef CONFIG_NUMA
47 int cpu = smp_processor_id();
48 int node;
49 unsigned int apicid = c->topo.apicid;
50
51 node = numa_cpu_node(cpu);
52 if (node == NUMA_NO_NODE)
53 node = c->topo.llc_id;
54
55 /*
56 * On multi-fabric platform (e.g. Numascale NumaChip) a
57 * platform-specific handler needs to be called to fixup some
58 * IDs of the CPU.
59 */
60 if (x86_cpuinit.fixup_cpu_id)
61 x86_cpuinit.fixup_cpu_id(c, node);
62
63 if (!node_online(node)) {
64 /*
65 * Two possibilities here:
66 *
67 * - The CPU is missing memory and no node was created. In
68 * that case try picking one from a nearby CPU.
69 *
70 * - The APIC IDs differ from the HyperTransport node IDs.
71 * Assume they are all increased by a constant offset, but
72 * in the same order as the HT nodeids. If that doesn't
73 * result in a usable node fall back to the path for the
74 * previous case.
75 *
76 * This workaround operates directly on the mapping between
77 * APIC ID and NUMA node, assuming certain relationship
78 * between APIC ID, HT node ID and NUMA topology. As going
79 * through CPU mapping may alter the outcome, directly
80 * access __apicid_to_node[].
81 */
82 int ht_nodeid = c->topo.initial_apicid;
83
84 if (__apicid_to_node[ht_nodeid] != NUMA_NO_NODE)
85 node = __apicid_to_node[ht_nodeid];
86 /* Pick a nearby node */
87 if (!node_online(node))
88 node = nearby_node(apicid);
89 }
90 numa_set_node(cpu, node);
91 #endif
92 }
93
94 static void bsp_init_hygon(struct cpuinfo_x86 *c)
95 {
96 if (cpu_has(c, X86_FEATURE_CONSTANT_TSC)) {
97 u64 val;
98
99 rdmsrl(MSR_K7_HWCR, val);
100 if (!(val & BIT(24)))
101 pr_warn(FW_BUG "TSC doesn't count with P0 frequency!\n");
102 }
103
104 if (cpu_has(c, X86_FEATURE_MWAITX))
105 use_mwaitx_delay();
106
107 if (!boot_cpu_has(X86_FEATURE_AMD_SSBD) &&
108 !boot_cpu_has(X86_FEATURE_VIRT_SSBD)) {
109 /*
110 * Try to cache the base value so further operations can
111 * avoid RMW. If that faults, do not enable SSBD.
112 */
113 if (!rdmsrl_safe(MSR_AMD64_LS_CFG, &x86_amd_ls_cfg_base)) {
114 setup_force_cpu_cap(X86_FEATURE_LS_CFG_SSBD);
115 setup_force_cpu_cap(X86_FEATURE_SSBD);
116 x86_amd_ls_cfg_ssbd_mask = 1ULL << 10;
117 }
118 }
119 }
120
121 static void early_init_hygon(struct cpuinfo_x86 *c)
122 {
123 u32 dummy;
124
125 set_cpu_cap(c, X86_FEATURE_K8);
126
127 rdmsr_safe(MSR_AMD64_PATCH_LEVEL, &c->microcode, &dummy);
128
129 /*
130 * c->x86_power is 8000_0007 edx. Bit 8 is TSC runs at constant rate
131 * with P/T states and does not stop in deep C-states
132 */
133 if (c->x86_power & (1 << 8)) {
134 set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
135 set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC);
136 }
137
138 /* Bit 12 of 8000_0007 edx is accumulated power mechanism. */
139 if (c->x86_power & BIT(12))
140 set_cpu_cap(c, X86_FEATURE_ACC_POWER);
141
142 /* Bit 14 indicates the Runtime Average Power Limit interface. */
143 if (c->x86_power & BIT(14))
144 set_cpu_cap(c, X86_FEATURE_RAPL);
145
146 #ifdef CONFIG_X86_64
147 set_cpu_cap(c, X86_FEATURE_SYSCALL32);
148 #endif
149
150 #if defined(CONFIG_X86_LOCAL_APIC) && defined(CONFIG_PCI)
151 /*
152 * ApicID can always be treated as an 8-bit value for Hygon APIC So, we
153 * can safely set X86_FEATURE_EXTD_APICID unconditionally.
154 */
155 if (boot_cpu_has(X86_FEATURE_APIC))
156 set_cpu_cap(c, X86_FEATURE_EXTD_APICID);
157 #endif
158
159 /*
160 * This is only needed to tell the kernel whether to use VMCALL
161 * and VMMCALL. VMMCALL is never executed except under virt, so
162 * we can set it unconditionally.
163 */
164 set_cpu_cap(c, X86_FEATURE_VMMCALL);
165 }
166
167 static void init_hygon(struct cpuinfo_x86 *c)
168 {
169 u64 vm_cr;
170
171 early_init_hygon(c);
172
173 /*
174 * Bit 31 in normal CPUID used for nonstandard 3DNow ID;
175 * 3DNow is IDd by bit 31 in extended CPUID (1*32+31) anyway
176 */
177 clear_cpu_cap(c, 0*32+31);
178
179 set_cpu_cap(c, X86_FEATURE_REP_GOOD);
180
181 /*
182 * XXX someone from Hygon needs to confirm this DTRT
183 *
184 init_spectral_chicken(c);
185 */
186
187 set_cpu_cap(c, X86_FEATURE_ZEN);
188 set_cpu_cap(c, X86_FEATURE_CPB);
189
190 cpu_detect_cache_sizes(c);
191
192 srat_detect_node(c);
193
194 init_hygon_cacheinfo(c);
195
196 if (cpu_has(c, X86_FEATURE_SVM)) {
197 rdmsrl(MSR_VM_CR, vm_cr);
198 if (vm_cr & SVM_VM_CR_SVM_DIS_MASK) {
199 pr_notice_once("SVM disabled (by BIOS) in MSR_VM_CR\n");
200 clear_cpu_cap(c, X86_FEATURE_SVM);
201 }
202 }
203
204 if (cpu_has(c, X86_FEATURE_XMM2)) {
205 /*
206 * Use LFENCE for execution serialization. On families which
207 * don't have that MSR, LFENCE is already serializing.
208 * msr_set_bit() uses the safe accessors, too, even if the MSR
209 * is not present.
210 */
211 msr_set_bit(MSR_AMD64_DE_CFG,
212 MSR_AMD64_DE_CFG_LFENCE_SERIALIZE_BIT);
213
214 /* A serializing LFENCE stops RDTSC speculation */
215 set_cpu_cap(c, X86_FEATURE_LFENCE_RDTSC);
216 }
217
218 /*
219 * Hygon processors have APIC timer running in deep C states.
220 */
221 set_cpu_cap(c, X86_FEATURE_ARAT);
222
223 /* Hygon CPUs don't reset SS attributes on SYSRET, Xen does. */
224 if (!cpu_feature_enabled(X86_FEATURE_XENPV))
225 set_cpu_bug(c, X86_BUG_SYSRET_SS_ATTRS);
226
227 check_null_seg_clears_base(c);
228
229 /* Hygon CPUs don't need fencing after x2APIC/TSC_DEADLINE MSR writes. */
230 clear_cpu_cap(c, X86_FEATURE_APIC_MSRS_FENCE);
231 }
232
233 static void cpu_detect_tlb_hygon(struct cpuinfo_x86 *c)
234 {
235 u32 ebx, eax, ecx, edx;
236 u16 mask = 0xfff;
237
238 if (c->extended_cpuid_level < 0x80000006)
239 return;
240
241 cpuid(0x80000006, &eax, &ebx, &ecx, &edx);
242
243 tlb_lld_4k[ENTRIES] = (ebx >> 16) & mask;
244 tlb_lli_4k[ENTRIES] = ebx & mask;
245
246 /* Handle DTLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
247 if (!((eax >> 16) & mask))
248 tlb_lld_2m[ENTRIES] = (cpuid_eax(0x80000005) >> 16) & 0xff;
249 else
250 tlb_lld_2m[ENTRIES] = (eax >> 16) & mask;
251
252 /* a 4M entry uses two 2M entries */
253 tlb_lld_4m[ENTRIES] = tlb_lld_2m[ENTRIES] >> 1;
254
255 /* Handle ITLB 2M and 4M sizes, fall back to L1 if L2 is disabled */
256 if (!(eax & mask)) {
257 cpuid(0x80000005, &eax, &ebx, &ecx, &edx);
258 tlb_lli_2m[ENTRIES] = eax & 0xff;
259 } else
260 tlb_lli_2m[ENTRIES] = eax & mask;
261
262 tlb_lli_4m[ENTRIES] = tlb_lli_2m[ENTRIES] >> 1;
263 }
264
265 static const struct cpu_dev hygon_cpu_dev = {
266 .c_vendor = "Hygon",
267 .c_ident = { "HygonGenuine" },
268 .c_early_init = early_init_hygon,
269 .c_detect_tlb = cpu_detect_tlb_hygon,
270 .c_bsp_init = bsp_init_hygon,
271 .c_init = init_hygon,
272 .c_x86_vendor = X86_VENDOR_HYGON,
273 };
274
275 cpu_dev_register(hygon_cpu_dev);
276
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