1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * linux/arch/x86/kernel/head_64.S -- start in 32bit and switch to 64bit 4 * 5 * Copyright (C) 2000 Andrea Arcangeli <andrea@suse.de> SuSE 6 * Copyright (C) 2000 Pavel Machek <pavel@suse.cz> 7 * Copyright (C) 2000 Karsten Keil <kkeil@suse.de> 8 * Copyright (C) 2001,2002 Andi Kleen <ak@suse.de> 9 * Copyright (C) 2005 Eric Biederman <ebiederm@xmission.com> 10 */ 11 12 #include <linux/export.h> 13 #include <linux/linkage.h> 14 #include <linux/threads.h> 15 #include <linux/init.h> 16 #include <linux/pgtable.h> 17 #include <asm/segment.h> 18 #include <asm/page.h> 19 #include <asm/msr.h> 20 #include <asm/cache.h> 21 #include <asm/processor-flags.h> 22 #include <asm/percpu.h> 23 #include <asm/nops.h> 24 #include "../entry/calling.h" 25 #include <asm/nospec-branch.h> 26 #include <asm/apicdef.h> 27 #include <asm/fixmap.h> 28 #include <asm/smp.h> 29 #include <asm/thread_info.h> 30 31 /* 32 * We are not able to switch in one step to the final KERNEL ADDRESS SPACE 33 * because we need identity-mapped pages. 34 */ 35 36 __HEAD 37 .code64 38 SYM_CODE_START_NOALIGN(startup_64) 39 UNWIND_HINT_END_OF_STACK 40 /* 41 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 42 * and someone has loaded an identity mapped page table 43 * for us. These identity mapped page tables map all of the 44 * kernel pages and possibly all of memory. 45 * 46 * %RSI holds the physical address of the boot_params structure 47 * provided by the bootloader. Preserve it in %R15 so C function calls 48 * will not clobber it. 49 * 50 * We come here either directly from a 64bit bootloader, or from 51 * arch/x86/boot/compressed/head_64.S. 52 * 53 * We only come here initially at boot nothing else comes here. 54 * 55 * Since we may be loaded at an address different from what we were 56 * compiled to run at we first fixup the physical addresses in our page 57 * tables and then reload them. 58 */ 59 mov %rsi, %r15 60 61 /* Set up the stack for verify_cpu() */ 62 leaq __top_init_kernel_stack(%rip), %rsp 63 64 /* Setup GSBASE to allow stack canary access for C code */ 65 movl $MSR_GS_BASE, %ecx 66 leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx 67 movl %edx, %eax 68 shrq $32, %rdx 69 wrmsr 70 71 call startup_64_setup_gdt_idt 72 73 /* Now switch to __KERNEL_CS so IRET works reliably */ 74 pushq $__KERNEL_CS 75 leaq .Lon_kernel_cs(%rip), %rax 76 pushq %rax 77 lretq 78 79 .Lon_kernel_cs: 80 UNWIND_HINT_END_OF_STACK 81 82 #ifdef CONFIG_AMD_MEM_ENCRYPT 83 /* 84 * Activate SEV/SME memory encryption if supported/enabled. This needs to 85 * be done now, since this also includes setup of the SEV-SNP CPUID table, 86 * which needs to be done before any CPUID instructions are executed in 87 * subsequent code. Pass the boot_params pointer as the first argument. 88 */ 89 movq %r15, %rdi 90 call sme_enable 91 #endif 92 93 /* Sanitize CPU configuration */ 94 call verify_cpu 95 96 /* 97 * Perform pagetable fixups. Additionally, if SME is active, encrypt 98 * the kernel and retrieve the modifier (SME encryption mask if SME 99 * is active) to be added to the initial pgdir entry that will be 100 * programmed into CR3. 101 */ 102 leaq _text(%rip), %rdi 103 movq %r15, %rsi 104 call __startup_64 105 106 /* Form the CR3 value being sure to include the CR3 modifier */ 107 leaq early_top_pgt(%rip), %rcx 108 addq %rcx, %rax 109 110 #ifdef CONFIG_AMD_MEM_ENCRYPT 111 mov %rax, %rdi 112 113 /* 114 * For SEV guests: Verify that the C-bit is correct. A malicious 115 * hypervisor could lie about the C-bit position to perform a ROP 116 * attack on the guest by writing to the unencrypted stack and wait for 117 * the next RET instruction. 118 */ 119 call sev_verify_cbit 120 #endif 121 122 /* 123 * Switch to early_top_pgt which still has the identity mappings 124 * present. 125 */ 126 movq %rax, %cr3 127 128 /* Branch to the common startup code at its kernel virtual address */ 129 ANNOTATE_RETPOLINE_SAFE 130 jmp *0f(%rip) 131 SYM_CODE_END(startup_64) 132 133 __INITRODATA 134 0: .quad common_startup_64 135 136 .text 137 SYM_CODE_START(secondary_startup_64) 138 UNWIND_HINT_END_OF_STACK 139 ANNOTATE_NOENDBR 140 /* 141 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0, 142 * and someone has loaded a mapped page table. 143 * 144 * We come here either from startup_64 (using physical addresses) 145 * or from trampoline.S (using virtual addresses). 146 * 147 * Using virtual addresses from trampoline.S removes the need 148 * to have any identity mapped pages in the kernel page table 149 * after the boot processor executes this code. 150 */ 151 152 /* Sanitize CPU configuration */ 153 call verify_cpu 154 155 /* 156 * The secondary_startup_64_no_verify entry point is only used by 157 * SEV-ES guests. In those guests the call to verify_cpu() would cause 158 * #VC exceptions which can not be handled at this stage of secondary 159 * CPU bringup. 160 * 161 * All non SEV-ES systems, especially Intel systems, need to execute 162 * verify_cpu() above to make sure NX is enabled. 163 */ 164 SYM_INNER_LABEL(secondary_startup_64_no_verify, SYM_L_GLOBAL) 165 UNWIND_HINT_END_OF_STACK 166 ANNOTATE_NOENDBR 167 168 /* Clear %R15 which holds the boot_params pointer on the boot CPU */ 169 xorl %r15d, %r15d 170 171 /* Derive the runtime physical address of init_top_pgt[] */ 172 movq phys_base(%rip), %rax 173 addq $(init_top_pgt - __START_KERNEL_map), %rax 174 175 /* 176 * Retrieve the modifier (SME encryption mask if SME is active) to be 177 * added to the initial pgdir entry that will be programmed into CR3. 178 */ 179 #ifdef CONFIG_AMD_MEM_ENCRYPT 180 addq sme_me_mask(%rip), %rax 181 #endif 182 /* 183 * Switch to the init_top_pgt here, away from the trampoline_pgd and 184 * unmap the identity mapped ranges. 185 */ 186 movq %rax, %cr3 187 188 SYM_INNER_LABEL(common_startup_64, SYM_L_LOCAL) 189 UNWIND_HINT_END_OF_STACK 190 ANNOTATE_NOENDBR 191 192 /* 193 * Create a mask of CR4 bits to preserve. Omit PGE in order to flush 194 * global 1:1 translations from the TLBs. 195 * 196 * From the SDM: 197 * "If CR4.PGE is changing from 0 to 1, there were no global TLB 198 * entries before the execution; if CR4.PGE is changing from 1 to 0, 199 * there will be no global TLB entries after the execution." 200 */ 201 movl $(X86_CR4_PAE | X86_CR4_LA57), %edx 202 #ifdef CONFIG_X86_MCE 203 /* 204 * Preserve CR4.MCE if the kernel will enable #MC support. 205 * Clearing MCE may fault in some environments (that also force #MC 206 * support). Any machine check that occurs before #MC support is fully 207 * configured will crash the system regardless of the CR4.MCE value set 208 * here. 209 */ 210 orl $X86_CR4_MCE, %edx 211 #endif 212 movq %cr4, %rcx 213 andl %edx, %ecx 214 215 /* Even if ignored in long mode, set PSE uniformly on all logical CPUs. */ 216 btsl $X86_CR4_PSE_BIT, %ecx 217 movq %rcx, %cr4 218 219 /* 220 * Set CR4.PGE to re-enable global translations. 221 */ 222 btsl $X86_CR4_PGE_BIT, %ecx 223 movq %rcx, %cr4 224 225 #ifdef CONFIG_SMP 226 /* 227 * For parallel boot, the APIC ID is read from the APIC, and then 228 * used to look up the CPU number. For booting a single CPU, the 229 * CPU number is encoded in smpboot_control. 230 * 231 * Bit 31 STARTUP_READ_APICID (Read APICID from APIC) 232 * Bit 0-23 CPU# if STARTUP_xx flags are not set 233 */ 234 movl smpboot_control(%rip), %ecx 235 testl $STARTUP_READ_APICID, %ecx 236 jnz .Lread_apicid 237 /* 238 * No control bit set, single CPU bringup. CPU number is provided 239 * in bit 0-23. This is also the boot CPU case (CPU number 0). 240 */ 241 andl $(~STARTUP_PARALLEL_MASK), %ecx 242 jmp .Lsetup_cpu 243 244 .Lread_apicid: 245 /* Check whether X2APIC mode is already enabled */ 246 mov $MSR_IA32_APICBASE, %ecx 247 rdmsr 248 testl $X2APIC_ENABLE, %eax 249 jnz .Lread_apicid_msr 250 251 #ifdef CONFIG_X86_X2APIC 252 /* 253 * If system is in X2APIC mode then MMIO base might not be 254 * mapped causing the MMIO read below to fault. Faults can't 255 * be handled at that point. 256 */ 257 cmpl $0, x2apic_mode(%rip) 258 jz .Lread_apicid_mmio 259 260 /* Force the AP into X2APIC mode. */ 261 orl $X2APIC_ENABLE, %eax 262 wrmsr 263 jmp .Lread_apicid_msr 264 #endif 265 266 .Lread_apicid_mmio: 267 /* Read the APIC ID from the fix-mapped MMIO space. */ 268 movq apic_mmio_base(%rip), %rcx 269 addq $APIC_ID, %rcx 270 movl (%rcx), %eax 271 shr $24, %eax 272 jmp .Llookup_AP 273 274 .Lread_apicid_msr: 275 mov $APIC_X2APIC_ID_MSR, %ecx 276 rdmsr 277 278 .Llookup_AP: 279 /* EAX contains the APIC ID of the current CPU */ 280 xorl %ecx, %ecx 281 leaq cpuid_to_apicid(%rip), %rbx 282 283 .Lfind_cpunr: 284 cmpl (%rbx,%rcx,4), %eax 285 jz .Lsetup_cpu 286 inc %ecx 287 #ifdef CONFIG_FORCE_NR_CPUS 288 cmpl $NR_CPUS, %ecx 289 #else 290 cmpl nr_cpu_ids(%rip), %ecx 291 #endif 292 jb .Lfind_cpunr 293 294 /* APIC ID not found in the table. Drop the trampoline lock and bail. */ 295 movq trampoline_lock(%rip), %rax 296 movl $0, (%rax) 297 298 1: cli 299 hlt 300 jmp 1b 301 302 .Lsetup_cpu: 303 /* Get the per cpu offset for the given CPU# which is in ECX */ 304 movq __per_cpu_offset(,%rcx,8), %rdx 305 #else 306 xorl %edx, %edx /* zero-extended to clear all of RDX */ 307 #endif /* CONFIG_SMP */ 308 309 /* 310 * Setup a boot time stack - Any secondary CPU will have lost its stack 311 * by now because the cr3-switch above unmaps the real-mode stack. 312 * 313 * RDX contains the per-cpu offset 314 */ 315 movq pcpu_hot + X86_current_task(%rdx), %rax 316 movq TASK_threadsp(%rax), %rsp 317 318 /* 319 * Now that this CPU is running on its own stack, drop the realmode 320 * protection. For the boot CPU the pointer is NULL! 321 */ 322 movq trampoline_lock(%rip), %rax 323 testq %rax, %rax 324 jz .Lsetup_gdt 325 movl $0, (%rax) 326 327 .Lsetup_gdt: 328 /* 329 * We must switch to a new descriptor in kernel space for the GDT 330 * because soon the kernel won't have access anymore to the userspace 331 * addresses where we're currently running on. We have to do that here 332 * because in 32bit we couldn't load a 64bit linear address. 333 */ 334 subq $16, %rsp 335 movw $(GDT_SIZE-1), (%rsp) 336 leaq gdt_page(%rdx), %rax 337 movq %rax, 2(%rsp) 338 lgdt (%rsp) 339 addq $16, %rsp 340 341 /* set up data segments */ 342 xorl %eax,%eax 343 movl %eax,%ds 344 movl %eax,%ss 345 movl %eax,%es 346 347 /* 348 * We don't really need to load %fs or %gs, but load them anyway 349 * to kill any stale realmode selectors. This allows execution 350 * under VT hardware. 351 */ 352 movl %eax,%fs 353 movl %eax,%gs 354 355 /* Set up %gs. 356 * 357 * The base of %gs always points to fixed_percpu_data. If the 358 * stack protector canary is enabled, it is located at %gs:40. 359 * Note that, on SMP, the boot cpu uses init data section until 360 * the per cpu areas are set up. 361 */ 362 movl $MSR_GS_BASE,%ecx 363 #ifndef CONFIG_SMP 364 leaq INIT_PER_CPU_VAR(fixed_percpu_data)(%rip), %rdx 365 #endif 366 movl %edx, %eax 367 shrq $32, %rdx 368 wrmsr 369 370 /* Setup and Load IDT */ 371 call early_setup_idt 372 373 /* Check if nx is implemented */ 374 movl $0x80000001, %eax 375 cpuid 376 movl %edx,%edi 377 378 /* Setup EFER (Extended Feature Enable Register) */ 379 movl $MSR_EFER, %ecx 380 rdmsr 381 /* 382 * Preserve current value of EFER for comparison and to skip 383 * EFER writes if no change was made (for TDX guest) 384 */ 385 movl %eax, %edx 386 btsl $_EFER_SCE, %eax /* Enable System Call */ 387 btl $20,%edi /* No Execute supported? */ 388 jnc 1f 389 btsl $_EFER_NX, %eax 390 btsq $_PAGE_BIT_NX,early_pmd_flags(%rip) 391 392 /* Avoid writing EFER if no change was made (for TDX guest) */ 393 1: cmpl %edx, %eax 394 je 1f 395 xor %edx, %edx 396 wrmsr /* Make changes effective */ 397 1: 398 /* Setup cr0 */ 399 movl $CR0_STATE, %eax 400 /* Make changes effective */ 401 movq %rax, %cr0 402 403 /* zero EFLAGS after setting rsp */ 404 pushq $0 405 popfq 406 407 /* Pass the boot_params pointer as first argument */ 408 movq %r15, %rdi 409 410 .Ljump_to_C_code: 411 xorl %ebp, %ebp # clear frame pointer 412 ANNOTATE_RETPOLINE_SAFE 413 callq *initial_code(%rip) 414 ud2 415 SYM_CODE_END(secondary_startup_64) 416 417 #include "verify_cpu.S" 418 #include "sev_verify_cbit.S" 419 420 #if defined(CONFIG_HOTPLUG_CPU) && defined(CONFIG_AMD_MEM_ENCRYPT) 421 /* 422 * Entry point for soft restart of a CPU. Invoked from xxx_play_dead() for 423 * restarting the boot CPU or for restarting SEV guest CPUs after CPU hot 424 * unplug. Everything is set up already except the stack. 425 */ 426 SYM_CODE_START(soft_restart_cpu) 427 ANNOTATE_NOENDBR 428 UNWIND_HINT_END_OF_STACK 429 430 /* Find the idle task stack */ 431 movq PER_CPU_VAR(pcpu_hot + X86_current_task), %rcx 432 movq TASK_threadsp(%rcx), %rsp 433 434 jmp .Ljump_to_C_code 435 SYM_CODE_END(soft_restart_cpu) 436 #endif 437 438 #ifdef CONFIG_AMD_MEM_ENCRYPT 439 /* 440 * VC Exception handler used during early boot when running on kernel 441 * addresses, but before the switch to the idt_table can be made. 442 * The early_idt_handler_array can't be used here because it calls into a lot 443 * of __init code and this handler is also used during CPU offlining/onlining. 444 * Therefore this handler ends up in the .text section so that it stays around 445 * when .init.text is freed. 446 */ 447 SYM_CODE_START_NOALIGN(vc_boot_ghcb) 448 UNWIND_HINT_IRET_REGS offset=8 449 ENDBR 450 451 /* Build pt_regs */ 452 PUSH_AND_CLEAR_REGS 453 454 /* Call C handler */ 455 movq %rsp, %rdi 456 movq ORIG_RAX(%rsp), %rsi 457 movq initial_vc_handler(%rip), %rax 458 ANNOTATE_RETPOLINE_SAFE 459 call *%rax 460 461 /* Unwind pt_regs */ 462 POP_REGS 463 464 /* Remove Error Code */ 465 addq $8, %rsp 466 467 iretq 468 SYM_CODE_END(vc_boot_ghcb) 469 #endif 470 471 /* Both SMP bootup and ACPI suspend change these variables */ 472 __REFDATA 473 .balign 8 474 SYM_DATA(initial_code, .quad x86_64_start_kernel) 475 #ifdef CONFIG_AMD_MEM_ENCRYPT 476 SYM_DATA(initial_vc_handler, .quad handle_vc_boot_ghcb) 477 #endif 478 479 SYM_DATA(trampoline_lock, .quad 0); 480 __FINITDATA 481 482 __INIT 483 SYM_CODE_START(early_idt_handler_array) 484 i = 0 485 .rept NUM_EXCEPTION_VECTORS 486 .if ((EXCEPTION_ERRCODE_MASK >> i) & 1) == 0 487 UNWIND_HINT_IRET_REGS 488 ENDBR 489 pushq $0 # Dummy error code, to make stack frame uniform 490 .else 491 UNWIND_HINT_IRET_REGS offset=8 492 ENDBR 493 .endif 494 pushq $i # 72(%rsp) Vector number 495 jmp early_idt_handler_common 496 UNWIND_HINT_IRET_REGS 497 i = i + 1 498 .fill early_idt_handler_array + i*EARLY_IDT_HANDLER_SIZE - ., 1, 0xcc 499 .endr 500 SYM_CODE_END(early_idt_handler_array) 501 ANNOTATE_NOENDBR // early_idt_handler_array[NUM_EXCEPTION_VECTORS] 502 503 SYM_CODE_START_LOCAL(early_idt_handler_common) 504 UNWIND_HINT_IRET_REGS offset=16 505 /* 506 * The stack is the hardware frame, an error code or zero, and the 507 * vector number. 508 */ 509 cld 510 511 incl early_recursion_flag(%rip) 512 513 /* The vector number is currently in the pt_regs->di slot. */ 514 pushq %rsi /* pt_regs->si */ 515 movq 8(%rsp), %rsi /* RSI = vector number */ 516 movq %rdi, 8(%rsp) /* pt_regs->di = RDI */ 517 pushq %rdx /* pt_regs->dx */ 518 pushq %rcx /* pt_regs->cx */ 519 pushq %rax /* pt_regs->ax */ 520 pushq %r8 /* pt_regs->r8 */ 521 pushq %r9 /* pt_regs->r9 */ 522 pushq %r10 /* pt_regs->r10 */ 523 pushq %r11 /* pt_regs->r11 */ 524 pushq %rbx /* pt_regs->bx */ 525 pushq %rbp /* pt_regs->bp */ 526 pushq %r12 /* pt_regs->r12 */ 527 pushq %r13 /* pt_regs->r13 */ 528 pushq %r14 /* pt_regs->r14 */ 529 pushq %r15 /* pt_regs->r15 */ 530 UNWIND_HINT_REGS 531 532 movq %rsp,%rdi /* RDI = pt_regs; RSI is already trapnr */ 533 call do_early_exception 534 535 decl early_recursion_flag(%rip) 536 jmp restore_regs_and_return_to_kernel 537 SYM_CODE_END(early_idt_handler_common) 538 539 #ifdef CONFIG_AMD_MEM_ENCRYPT 540 /* 541 * VC Exception handler used during very early boot. The 542 * early_idt_handler_array can't be used because it returns via the 543 * paravirtualized INTERRUPT_RETURN and pv-ops don't work that early. 544 * 545 * XXX it does, fix this. 546 * 547 * This handler will end up in the .init.text section and not be 548 * available to boot secondary CPUs. 549 */ 550 SYM_CODE_START_NOALIGN(vc_no_ghcb) 551 UNWIND_HINT_IRET_REGS offset=8 552 ENDBR 553 554 /* Build pt_regs */ 555 PUSH_AND_CLEAR_REGS 556 557 /* Call C handler */ 558 movq %rsp, %rdi 559 movq ORIG_RAX(%rsp), %rsi 560 call do_vc_no_ghcb 561 562 /* Unwind pt_regs */ 563 POP_REGS 564 565 /* Remove Error Code */ 566 addq $8, %rsp 567 568 /* Pure iret required here - don't use INTERRUPT_RETURN */ 569 iretq 570 SYM_CODE_END(vc_no_ghcb) 571 #endif 572 573 #ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION 574 /* 575 * Each PGD needs to be 8k long and 8k aligned. We do not 576 * ever go out to userspace with these, so we do not 577 * strictly *need* the second page, but this allows us to 578 * have a single set_pgd() implementation that does not 579 * need to worry about whether it has 4k or 8k to work 580 * with. 581 * 582 * This ensures PGDs are 8k long: 583 */ 584 #define PTI_USER_PGD_FILL 512 585 /* This ensures they are 8k-aligned: */ 586 #define SYM_DATA_START_PTI_ALIGNED(name) \ 587 SYM_START(name, SYM_L_GLOBAL, .balign 2 * PAGE_SIZE) 588 #else 589 #define SYM_DATA_START_PTI_ALIGNED(name) \ 590 SYM_DATA_START_PAGE_ALIGNED(name) 591 #define PTI_USER_PGD_FILL 0 592 #endif 593 594 __INITDATA 595 .balign 4 596 597 SYM_DATA_START_PTI_ALIGNED(early_top_pgt) 598 .fill 511,8,0 599 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 600 .fill PTI_USER_PGD_FILL,8,0 601 SYM_DATA_END(early_top_pgt) 602 603 SYM_DATA_START_PAGE_ALIGNED(early_dynamic_pgts) 604 .fill 512*EARLY_DYNAMIC_PAGE_TABLES,8,0 605 SYM_DATA_END(early_dynamic_pgts) 606 607 SYM_DATA(early_recursion_flag, .long 0) 608 609 .data 610 611 #if defined(CONFIG_XEN_PV) || defined(CONFIG_PVH) 612 SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 613 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 614 .org init_top_pgt + L4_PAGE_OFFSET*8, 0 615 .quad level3_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 616 .org init_top_pgt + L4_START_KERNEL*8, 0 617 /* (2^48-(2*1024*1024*1024))/(2^39) = 511 */ 618 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 619 .fill PTI_USER_PGD_FILL,8,0 620 SYM_DATA_END(init_top_pgt) 621 622 SYM_DATA_START_PAGE_ALIGNED(level3_ident_pgt) 623 .quad level2_ident_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 624 .fill 511, 8, 0 625 SYM_DATA_END(level3_ident_pgt) 626 SYM_DATA_START_PAGE_ALIGNED(level2_ident_pgt) 627 /* 628 * Since I easily can, map the first 1G. 629 * Don't set NX because code runs from these pages. 630 * 631 * Note: This sets _PAGE_GLOBAL despite whether 632 * the CPU supports it or it is enabled. But, 633 * the CPU should ignore the bit. 634 */ 635 PMDS(0, __PAGE_KERNEL_IDENT_LARGE_EXEC, PTRS_PER_PMD) 636 SYM_DATA_END(level2_ident_pgt) 637 #else 638 SYM_DATA_START_PTI_ALIGNED(init_top_pgt) 639 .fill 512,8,0 640 .fill PTI_USER_PGD_FILL,8,0 641 SYM_DATA_END(init_top_pgt) 642 #endif 643 644 #ifdef CONFIG_X86_5LEVEL 645 SYM_DATA_START_PAGE_ALIGNED(level4_kernel_pgt) 646 .fill 511,8,0 647 .quad level3_kernel_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 648 SYM_DATA_END(level4_kernel_pgt) 649 #endif 650 651 SYM_DATA_START_PAGE_ALIGNED(level3_kernel_pgt) 652 .fill L3_START_KERNEL,8,0 653 /* (2^48-(2*1024*1024*1024)-((2^39)*511))/(2^30) = 510 */ 654 .quad level2_kernel_pgt - __START_KERNEL_map + _KERNPG_TABLE_NOENC 655 .quad level2_fixmap_pgt - __START_KERNEL_map + _PAGE_TABLE_NOENC 656 SYM_DATA_END(level3_kernel_pgt) 657 658 SYM_DATA_START_PAGE_ALIGNED(level2_kernel_pgt) 659 /* 660 * Kernel high mapping. 661 * 662 * The kernel code+data+bss must be located below KERNEL_IMAGE_SIZE in 663 * virtual address space, which is 1 GiB if RANDOMIZE_BASE is enabled, 664 * 512 MiB otherwise. 665 * 666 * (NOTE: after that starts the module area, see MODULES_VADDR.) 667 * 668 * This table is eventually used by the kernel during normal runtime. 669 * Care must be taken to clear out undesired bits later, like _PAGE_RW 670 * or _PAGE_GLOBAL in some cases. 671 */ 672 PMDS(0, __PAGE_KERNEL_LARGE_EXEC, KERNEL_IMAGE_SIZE/PMD_SIZE) 673 SYM_DATA_END(level2_kernel_pgt) 674 675 SYM_DATA_START_PAGE_ALIGNED(level2_fixmap_pgt) 676 .fill (512 - 4 - FIXMAP_PMD_NUM),8,0 677 pgtno = 0 678 .rept (FIXMAP_PMD_NUM) 679 .quad level1_fixmap_pgt + (pgtno << PAGE_SHIFT) - __START_KERNEL_map \ 680 + _PAGE_TABLE_NOENC; 681 pgtno = pgtno + 1 682 .endr 683 /* 6 MB reserved space + a 2MB hole */ 684 .fill 4,8,0 685 SYM_DATA_END(level2_fixmap_pgt) 686 687 SYM_DATA_START_PAGE_ALIGNED(level1_fixmap_pgt) 688 .rept (FIXMAP_PMD_NUM) 689 .fill 512,8,0 690 .endr 691 SYM_DATA_END(level1_fixmap_pgt) 692 693 .data 694 .align 16 695 696 SYM_DATA(smpboot_control, .long 0) 697 698 .align 16 699 /* This must match the first entry in level2_kernel_pgt */ 700 SYM_DATA(phys_base, .quad 0x0) 701 EXPORT_SYMBOL(phys_base) 702 703 #include "../xen/xen-head.S" 704 705 __PAGE_ALIGNED_BSS 706 SYM_DATA_START_PAGE_ALIGNED(empty_zero_page) 707 .skip PAGE_SIZE 708 SYM_DATA_END(empty_zero_page) 709 EXPORT_SYMBOL(empty_zero_page) 710
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