1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * AMD Family 10h mmconfig enablement
4 */
5
6 #include <linux/types.h>
7 #include <linux/mm.h>
8 #include <linux/string.h>
9 #include <linux/pci.h>
10 #include <linux/dmi.h>
11 #include <linux/range.h>
12 #include <linux/acpi.h>
13
14 #include <asm/pci-direct.h>
15 #include <linux/sort.h>
16 #include <asm/io.h>
17 #include <asm/msr.h>
18 #include <asm/acpi.h>
19 #include <asm/mmconfig.h>
20 #include <asm/pci_x86.h>
21
22 struct pci_hostbridge_probe {
23 u32 bus;
24 u32 slot;
25 u32 vendor;
26 u32 device;
27 };
28
29 static u64 fam10h_pci_mmconf_base;
30
31 static struct pci_hostbridge_probe pci_probes[] = {
32 { 0, 0x18, PCI_VENDOR_ID_AMD, 0x1200 },
33 { 0xff, 0, PCI_VENDOR_ID_AMD, 0x1200 },
34 };
35
36 static int cmp_range(const void *x1, const void *x2)
37 {
38 const struct range *r1 = x1;
39 const struct range *r2 = x2;
40 int start1, start2;
41
42 start1 = r1->start >> 32;
43 start2 = r2->start >> 32;
44
45 return start1 - start2;
46 }
47
48 #define MMCONF_UNIT (1ULL << FAM10H_MMIO_CONF_BASE_SHIFT)
49 #define MMCONF_MASK (~(MMCONF_UNIT - 1))
50 #define MMCONF_SIZE (MMCONF_UNIT << 8)
51 /* need to avoid (0xfd<<32), (0xfe<<32), and (0xff<<32), ht used space */
52 #define FAM10H_PCI_MMCONF_BASE (0xfcULL<<32)
53 #define BASE_VALID(b) ((b) + MMCONF_SIZE <= (0xfdULL<<32) || (b) >= (1ULL<<40))
54 static void get_fam10h_pci_mmconf_base(void)
55 {
56 int i;
57 unsigned bus;
58 unsigned slot;
59 int found;
60
61 u64 val;
62 u32 address;
63 u64 tom2;
64 u64 base = FAM10H_PCI_MMCONF_BASE;
65
66 int hi_mmio_num;
67 struct range range[8];
68
69 /* only try to get setting from BSP */
70 if (fam10h_pci_mmconf_base)
71 return;
72
73 if (!early_pci_allowed())
74 return;
75
76 found = 0;
77 for (i = 0; i < ARRAY_SIZE(pci_probes); i++) {
78 u32 id;
79 u16 device;
80 u16 vendor;
81
82 bus = pci_probes[i].bus;
83 slot = pci_probes[i].slot;
84 id = read_pci_config(bus, slot, 0, PCI_VENDOR_ID);
85
86 vendor = id & 0xffff;
87 device = (id>>16) & 0xffff;
88 if (pci_probes[i].vendor == vendor &&
89 pci_probes[i].device == device) {
90 found = 1;
91 break;
92 }
93 }
94
95 if (!found)
96 return;
97
98 /* SYS_CFG */
99 address = MSR_AMD64_SYSCFG;
100 rdmsrl(address, val);
101
102 /* TOP_MEM2 is not enabled? */
103 if (!(val & (1<<21))) {
104 tom2 = 1ULL << 32;
105 } else {
106 /* TOP_MEM2 */
107 address = MSR_K8_TOP_MEM2;
108 rdmsrl(address, val);
109 tom2 = max(val & 0xffffff800000ULL, 1ULL << 32);
110 }
111
112 if (base <= tom2)
113 base = (tom2 + 2 * MMCONF_UNIT - 1) & MMCONF_MASK;
114
115 /*
116 * need to check if the range is in the high mmio range that is
117 * above 4G
118 */
119 hi_mmio_num = 0;
120 for (i = 0; i < 8; i++) {
121 u32 reg;
122 u64 start;
123 u64 end;
124 reg = read_pci_config(bus, slot, 1, 0x80 + (i << 3));
125 if (!(reg & 3))
126 continue;
127
128 start = (u64)(reg & 0xffffff00) << 8; /* 39:16 on 31:8*/
129 reg = read_pci_config(bus, slot, 1, 0x84 + (i << 3));
130 end = ((u64)(reg & 0xffffff00) << 8) | 0xffff; /* 39:16 on 31:8*/
131
132 if (end < tom2)
133 continue;
134
135 range[hi_mmio_num].start = start;
136 range[hi_mmio_num].end = end;
137 hi_mmio_num++;
138 }
139
140 if (!hi_mmio_num)
141 goto out;
142
143 /* sort the range */
144 sort(range, hi_mmio_num, sizeof(struct range), cmp_range, NULL);
145
146 if (range[hi_mmio_num - 1].end < base)
147 goto out;
148 if (range[0].start > base + MMCONF_SIZE)
149 goto out;
150
151 /* need to find one window */
152 base = (range[0].start & MMCONF_MASK) - MMCONF_UNIT;
153 if ((base > tom2) && BASE_VALID(base))
154 goto out;
155 base = (range[hi_mmio_num - 1].end + MMCONF_UNIT) & MMCONF_MASK;
156 if (BASE_VALID(base))
157 goto out;
158 /* need to find window between ranges */
159 for (i = 1; i < hi_mmio_num; i++) {
160 base = (range[i - 1].end + MMCONF_UNIT) & MMCONF_MASK;
161 val = range[i].start & MMCONF_MASK;
162 if (val >= base + MMCONF_SIZE && BASE_VALID(base))
163 goto out;
164 }
165 return;
166
167 out:
168 fam10h_pci_mmconf_base = base;
169 }
170
171 void fam10h_check_enable_mmcfg(void)
172 {
173 u64 val;
174 u32 address;
175
176 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
177 return;
178
179 address = MSR_FAM10H_MMIO_CONF_BASE;
180 rdmsrl(address, val);
181
182 /* try to make sure that AP's setting is identical to BSP setting */
183 if (val & FAM10H_MMIO_CONF_ENABLE) {
184 unsigned busnbits;
185 busnbits = (val >> FAM10H_MMIO_CONF_BUSRANGE_SHIFT) &
186 FAM10H_MMIO_CONF_BUSRANGE_MASK;
187
188 /* only trust the one handle 256 buses, if acpi=off */
189 if (!acpi_pci_disabled || busnbits >= 8) {
190 u64 base = val & MMCONF_MASK;
191
192 if (!fam10h_pci_mmconf_base) {
193 fam10h_pci_mmconf_base = base;
194 return;
195 } else if (fam10h_pci_mmconf_base == base)
196 return;
197 }
198 }
199
200 /*
201 * if it is not enabled, try to enable it and assume only one segment
202 * with 256 buses
203 */
204 get_fam10h_pci_mmconf_base();
205 if (!fam10h_pci_mmconf_base) {
206 pci_probe &= ~PCI_CHECK_ENABLE_AMD_MMCONF;
207 return;
208 }
209
210 printk(KERN_INFO "Enable MMCONFIG on AMD Family 10h\n");
211 val &= ~((FAM10H_MMIO_CONF_BASE_MASK<<FAM10H_MMIO_CONF_BASE_SHIFT) |
212 (FAM10H_MMIO_CONF_BUSRANGE_MASK<<FAM10H_MMIO_CONF_BUSRANGE_SHIFT));
213 val |= fam10h_pci_mmconf_base | (8 << FAM10H_MMIO_CONF_BUSRANGE_SHIFT) |
214 FAM10H_MMIO_CONF_ENABLE;
215 wrmsrl(address, val);
216 }
217
218 static int __init set_check_enable_amd_mmconf(const struct dmi_system_id *d)
219 {
220 pci_probe |= PCI_CHECK_ENABLE_AMD_MMCONF;
221 return 0;
222 }
223
224 static const struct dmi_system_id __initconst mmconf_dmi_table[] = {
225 {
226 .callback = set_check_enable_amd_mmconf,
227 .ident = "Sun Microsystems Machine",
228 .matches = {
229 DMI_MATCH(DMI_SYS_VENDOR, "Sun Microsystems"),
230 },
231 },
232 {}
233 };
234
235 /* Called from a non __init function, but only on the BSP. */
236 void __ref check_enable_amd_mmconf_dmi(void)
237 {
238 dmi_check_system(mmconf_dmi_table);
239 }
240
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