1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Kernel-based Virtual Machine driver for Linux
4 *
5 * AMD SVM support
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
9 *
10 * Authors:
11 * Yaniv Kamay <yaniv@qumranet.com>
12 * Avi Kivity <avi@qumranet.com>
13 */
14
15 #ifndef __SVM_SVM_H
16 #define __SVM_SVM_H
17
18 #include <linux/kvm_types.h>
19 #include <linux/kvm_host.h>
20 #include <linux/bits.h>
21
22 #include <asm/svm.h>
23 #include <asm/sev-common.h>
24
25 #include "cpuid.h"
26 #include "kvm_cache_regs.h"
27
28 #define __sme_page_pa(x) __sme_set(page_to_pfn(x) << PAGE_SHIFT)
29
30 #define IOPM_SIZE PAGE_SIZE * 3
31 #define MSRPM_SIZE PAGE_SIZE * 2
32
33 #define MAX_DIRECT_ACCESS_MSRS 48
34 #define MSRPM_OFFSETS 32
35 extern u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
36 extern bool npt_enabled;
37 extern int nrips;
38 extern int vgif;
39 extern bool intercept_smi;
40 extern bool x2avic_enabled;
41 extern bool vnmi;
42 extern int lbrv;
43
44 /*
45 * Clean bits in VMCB.
46 * VMCB_ALL_CLEAN_MASK might also need to
47 * be updated if this enum is modified.
48 */
49 enum {
50 VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
51 pause filter count */
52 VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
53 VMCB_ASID, /* ASID */
54 VMCB_INTR, /* int_ctl, int_vector */
55 VMCB_NPT, /* npt_en, nCR3, gPAT */
56 VMCB_CR, /* CR0, CR3, CR4, EFER */
57 VMCB_DR, /* DR6, DR7 */
58 VMCB_DT, /* GDT, IDT */
59 VMCB_SEG, /* CS, DS, SS, ES, CPL */
60 VMCB_CR2, /* CR2 only */
61 VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
62 VMCB_AVIC, /* AVIC APIC_BAR, AVIC APIC_BACKING_PAGE,
63 * AVIC PHYSICAL_TABLE pointer,
64 * AVIC LOGICAL_TABLE pointer
65 */
66 VMCB_SW = 31, /* Reserved for hypervisor/software use */
67 };
68
69 #define VMCB_ALL_CLEAN_MASK ( \
70 (1U << VMCB_INTERCEPTS) | (1U << VMCB_PERM_MAP) | \
71 (1U << VMCB_ASID) | (1U << VMCB_INTR) | \
72 (1U << VMCB_NPT) | (1U << VMCB_CR) | (1U << VMCB_DR) | \
73 (1U << VMCB_DT) | (1U << VMCB_SEG) | (1U << VMCB_CR2) | \
74 (1U << VMCB_LBR) | (1U << VMCB_AVIC) | \
75 (1U << VMCB_SW))
76
77 /* TPR and CR2 are always written before VMRUN */
78 #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
79
80 struct kvm_sev_info {
81 bool active; /* SEV enabled guest */
82 bool es_active; /* SEV-ES enabled guest */
83 bool need_init; /* waiting for SEV_INIT2 */
84 unsigned int asid; /* ASID used for this guest */
85 unsigned int handle; /* SEV firmware handle */
86 int fd; /* SEV device fd */
87 unsigned long pages_locked; /* Number of pages locked */
88 struct list_head regions_list; /* List of registered regions */
89 u64 ap_jump_table; /* SEV-ES AP Jump Table address */
90 u64 vmsa_features;
91 u16 ghcb_version; /* Highest guest GHCB protocol version allowed */
92 struct kvm *enc_context_owner; /* Owner of copied encryption context */
93 struct list_head mirror_vms; /* List of VMs mirroring */
94 struct list_head mirror_entry; /* Use as a list entry of mirrors */
95 struct misc_cg *misc_cg; /* For misc cgroup accounting */
96 atomic_t migration_in_progress;
97 void *snp_context; /* SNP guest context page */
98 void *guest_req_buf; /* Bounce buffer for SNP Guest Request input */
99 void *guest_resp_buf; /* Bounce buffer for SNP Guest Request output */
100 struct mutex guest_req_mutex; /* Must acquire before using bounce buffers */
101 };
102
103 struct kvm_svm {
104 struct kvm kvm;
105
106 /* Struct members for AVIC */
107 u32 avic_vm_id;
108 struct page *avic_logical_id_table_page;
109 struct page *avic_physical_id_table_page;
110 struct hlist_node hnode;
111
112 struct kvm_sev_info sev_info;
113 };
114
115 struct kvm_vcpu;
116
117 struct kvm_vmcb_info {
118 struct vmcb *ptr;
119 unsigned long pa;
120 int cpu;
121 uint64_t asid_generation;
122 };
123
124 struct vmcb_save_area_cached {
125 u64 efer;
126 u64 cr4;
127 u64 cr3;
128 u64 cr0;
129 u64 dr7;
130 u64 dr6;
131 };
132
133 struct vmcb_ctrl_area_cached {
134 u32 intercepts[MAX_INTERCEPT];
135 u16 pause_filter_thresh;
136 u16 pause_filter_count;
137 u64 iopm_base_pa;
138 u64 msrpm_base_pa;
139 u64 tsc_offset;
140 u32 asid;
141 u8 tlb_ctl;
142 u32 int_ctl;
143 u32 int_vector;
144 u32 int_state;
145 u32 exit_code;
146 u32 exit_code_hi;
147 u64 exit_info_1;
148 u64 exit_info_2;
149 u32 exit_int_info;
150 u32 exit_int_info_err;
151 u64 nested_ctl;
152 u32 event_inj;
153 u32 event_inj_err;
154 u64 next_rip;
155 u64 nested_cr3;
156 u64 virt_ext;
157 u32 clean;
158 union {
159 #if IS_ENABLED(CONFIG_HYPERV) || IS_ENABLED(CONFIG_KVM_HYPERV)
160 struct hv_vmcb_enlightenments hv_enlightenments;
161 #endif
162 u8 reserved_sw[32];
163 };
164 };
165
166 struct svm_nested_state {
167 struct kvm_vmcb_info vmcb02;
168 u64 hsave_msr;
169 u64 vm_cr_msr;
170 u64 vmcb12_gpa;
171 u64 last_vmcb12_gpa;
172
173 /* These are the merged vectors */
174 u32 *msrpm;
175
176 /* A VMRUN has started but has not yet been performed, so
177 * we cannot inject a nested vmexit yet. */
178 bool nested_run_pending;
179
180 /* cache for control fields of the guest */
181 struct vmcb_ctrl_area_cached ctl;
182
183 /*
184 * Note: this struct is not kept up-to-date while L2 runs; it is only
185 * valid within nested_svm_vmrun.
186 */
187 struct vmcb_save_area_cached save;
188
189 bool initialized;
190
191 /*
192 * Indicates whether MSR bitmap for L2 needs to be rebuilt due to
193 * changes in MSR bitmap for L1 or switching to a different L2. Note,
194 * this flag can only be used reliably in conjunction with a paravirt L1
195 * which informs L0 whether any changes to MSR bitmap for L2 were done
196 * on its side.
197 */
198 bool force_msr_bitmap_recalc;
199 };
200
201 struct vcpu_sev_es_state {
202 /* SEV-ES support */
203 struct sev_es_save_area *vmsa;
204 struct ghcb *ghcb;
205 u8 valid_bitmap[16];
206 struct kvm_host_map ghcb_map;
207 bool received_first_sipi;
208 unsigned int ap_reset_hold_type;
209
210 /* SEV-ES scratch area support */
211 u64 sw_scratch;
212 void *ghcb_sa;
213 u32 ghcb_sa_len;
214 bool ghcb_sa_sync;
215 bool ghcb_sa_free;
216
217 /* SNP Page-State-Change buffer entries currently being processed */
218 u16 psc_idx;
219 u16 psc_inflight;
220 bool psc_2m;
221
222 u64 ghcb_registered_gpa;
223
224 struct mutex snp_vmsa_mutex; /* Used to handle concurrent updates of VMSA. */
225 gpa_t snp_vmsa_gpa;
226 bool snp_ap_waiting_for_reset;
227 bool snp_has_guest_vmsa;
228 };
229
230 struct vcpu_svm {
231 struct kvm_vcpu vcpu;
232 /* vmcb always points at current_vmcb->ptr, it's purely a shorthand. */
233 struct vmcb *vmcb;
234 struct kvm_vmcb_info vmcb01;
235 struct kvm_vmcb_info *current_vmcb;
236 u32 asid;
237 u32 sysenter_esp_hi;
238 u32 sysenter_eip_hi;
239 uint64_t tsc_aux;
240
241 u64 msr_decfg;
242
243 u64 next_rip;
244
245 u64 spec_ctrl;
246
247 u64 tsc_ratio_msr;
248 /*
249 * Contains guest-controlled bits of VIRT_SPEC_CTRL, which will be
250 * translated into the appropriate L2_CFG bits on the host to
251 * perform speculative control.
252 */
253 u64 virt_spec_ctrl;
254
255 u32 *msrpm;
256
257 ulong nmi_iret_rip;
258
259 struct svm_nested_state nested;
260
261 /* NMI mask value, used when vNMI is not enabled */
262 bool nmi_masked;
263
264 /*
265 * True when NMIs are still masked but guest IRET was just intercepted
266 * and KVM is waiting for RIP to change, which will signal that the
267 * intercepted IRET was retired and thus NMI can be unmasked.
268 */
269 bool awaiting_iret_completion;
270
271 /*
272 * Set when KVM is awaiting IRET completion and needs to inject NMIs as
273 * soon as the IRET completes (e.g. NMI is pending injection). KVM
274 * temporarily steals RFLAGS.TF to single-step the guest in this case
275 * in order to regain control as soon as the NMI-blocking condition
276 * goes away.
277 */
278 bool nmi_singlestep;
279 u64 nmi_singlestep_guest_rflags;
280
281 bool nmi_l1_to_l2;
282
283 unsigned long soft_int_csbase;
284 unsigned long soft_int_old_rip;
285 unsigned long soft_int_next_rip;
286 bool soft_int_injected;
287
288 u32 ldr_reg;
289 u32 dfr_reg;
290 struct page *avic_backing_page;
291 u64 *avic_physical_id_cache;
292
293 /*
294 * Per-vcpu list of struct amd_svm_iommu_ir:
295 * This is used mainly to store interrupt remapping information used
296 * when update the vcpu affinity. This avoids the need to scan for
297 * IRTE and try to match ga_tag in the IOMMU driver.
298 */
299 struct list_head ir_list;
300 spinlock_t ir_list_lock;
301
302 /* Save desired MSR intercept (read: pass-through) state */
303 struct {
304 DECLARE_BITMAP(read, MAX_DIRECT_ACCESS_MSRS);
305 DECLARE_BITMAP(write, MAX_DIRECT_ACCESS_MSRS);
306 } shadow_msr_intercept;
307
308 struct vcpu_sev_es_state sev_es;
309
310 bool guest_state_loaded;
311
312 bool x2avic_msrs_intercepted;
313
314 /* Guest GIF value, used when vGIF is not enabled */
315 bool guest_gif;
316 };
317
318 struct svm_cpu_data {
319 u64 asid_generation;
320 u32 max_asid;
321 u32 next_asid;
322 u32 min_asid;
323
324 struct page *save_area;
325 unsigned long save_area_pa;
326
327 struct vmcb *current_vmcb;
328
329 /* index = sev_asid, value = vmcb pointer */
330 struct vmcb **sev_vmcbs;
331 };
332
333 DECLARE_PER_CPU(struct svm_cpu_data, svm_data);
334
335 void recalc_intercepts(struct vcpu_svm *svm);
336
337 static __always_inline struct kvm_svm *to_kvm_svm(struct kvm *kvm)
338 {
339 return container_of(kvm, struct kvm_svm, kvm);
340 }
341
342 static __always_inline struct kvm_sev_info *to_kvm_sev_info(struct kvm *kvm)
343 {
344 return &to_kvm_svm(kvm)->sev_info;
345 }
346
347 static __always_inline bool sev_guest(struct kvm *kvm)
348 {
349 #ifdef CONFIG_KVM_AMD_SEV
350 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
351
352 return sev->active;
353 #else
354 return false;
355 #endif
356 }
357
358 static __always_inline bool sev_es_guest(struct kvm *kvm)
359 {
360 #ifdef CONFIG_KVM_AMD_SEV
361 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
362
363 return sev->es_active && !WARN_ON_ONCE(!sev->active);
364 #else
365 return false;
366 #endif
367 }
368
369 static __always_inline bool sev_snp_guest(struct kvm *kvm)
370 {
371 #ifdef CONFIG_KVM_AMD_SEV
372 struct kvm_sev_info *sev = &to_kvm_svm(kvm)->sev_info;
373
374 return (sev->vmsa_features & SVM_SEV_FEAT_SNP_ACTIVE) &&
375 !WARN_ON_ONCE(!sev_es_guest(kvm));
376 #else
377 return false;
378 #endif
379 }
380
381 static inline bool ghcb_gpa_is_registered(struct vcpu_svm *svm, u64 val)
382 {
383 return svm->sev_es.ghcb_registered_gpa == val;
384 }
385
386 static inline void vmcb_mark_all_dirty(struct vmcb *vmcb)
387 {
388 vmcb->control.clean = 0;
389 }
390
391 static inline void vmcb_mark_all_clean(struct vmcb *vmcb)
392 {
393 vmcb->control.clean = VMCB_ALL_CLEAN_MASK
394 & ~VMCB_ALWAYS_DIRTY_MASK;
395 }
396
397 static inline void vmcb_mark_dirty(struct vmcb *vmcb, int bit)
398 {
399 vmcb->control.clean &= ~(1 << bit);
400 }
401
402 static inline bool vmcb_is_dirty(struct vmcb *vmcb, int bit)
403 {
404 return !test_bit(bit, (unsigned long *)&vmcb->control.clean);
405 }
406
407 static __always_inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
408 {
409 return container_of(vcpu, struct vcpu_svm, vcpu);
410 }
411
412 /*
413 * Only the PDPTRs are loaded on demand into the shadow MMU. All other
414 * fields are synchronized on VM-Exit, because accessing the VMCB is cheap.
415 *
416 * CR3 might be out of date in the VMCB but it is not marked dirty; instead,
417 * KVM_REQ_LOAD_MMU_PGD is always requested when the cached vcpu->arch.cr3
418 * is changed. svm_load_mmu_pgd() then syncs the new CR3 value into the VMCB.
419 */
420 #define SVM_REGS_LAZY_LOAD_SET (1 << VCPU_EXREG_PDPTR)
421
422 static inline void vmcb_set_intercept(struct vmcb_control_area *control, u32 bit)
423 {
424 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
425 __set_bit(bit, (unsigned long *)&control->intercepts);
426 }
427
428 static inline void vmcb_clr_intercept(struct vmcb_control_area *control, u32 bit)
429 {
430 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
431 __clear_bit(bit, (unsigned long *)&control->intercepts);
432 }
433
434 static inline bool vmcb_is_intercept(struct vmcb_control_area *control, u32 bit)
435 {
436 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
437 return test_bit(bit, (unsigned long *)&control->intercepts);
438 }
439
440 static inline bool vmcb12_is_intercept(struct vmcb_ctrl_area_cached *control, u32 bit)
441 {
442 WARN_ON_ONCE(bit >= 32 * MAX_INTERCEPT);
443 return test_bit(bit, (unsigned long *)&control->intercepts);
444 }
445
446 static inline void set_exception_intercept(struct vcpu_svm *svm, u32 bit)
447 {
448 struct vmcb *vmcb = svm->vmcb01.ptr;
449
450 WARN_ON_ONCE(bit >= 32);
451 vmcb_set_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
452
453 recalc_intercepts(svm);
454 }
455
456 static inline void clr_exception_intercept(struct vcpu_svm *svm, u32 bit)
457 {
458 struct vmcb *vmcb = svm->vmcb01.ptr;
459
460 WARN_ON_ONCE(bit >= 32);
461 vmcb_clr_intercept(&vmcb->control, INTERCEPT_EXCEPTION_OFFSET + bit);
462
463 recalc_intercepts(svm);
464 }
465
466 static inline void svm_set_intercept(struct vcpu_svm *svm, int bit)
467 {
468 struct vmcb *vmcb = svm->vmcb01.ptr;
469
470 vmcb_set_intercept(&vmcb->control, bit);
471
472 recalc_intercepts(svm);
473 }
474
475 static inline void svm_clr_intercept(struct vcpu_svm *svm, int bit)
476 {
477 struct vmcb *vmcb = svm->vmcb01.ptr;
478
479 vmcb_clr_intercept(&vmcb->control, bit);
480
481 recalc_intercepts(svm);
482 }
483
484 static inline bool svm_is_intercept(struct vcpu_svm *svm, int bit)
485 {
486 return vmcb_is_intercept(&svm->vmcb->control, bit);
487 }
488
489 static inline bool nested_vgif_enabled(struct vcpu_svm *svm)
490 {
491 return guest_can_use(&svm->vcpu, X86_FEATURE_VGIF) &&
492 (svm->nested.ctl.int_ctl & V_GIF_ENABLE_MASK);
493 }
494
495 static inline struct vmcb *get_vgif_vmcb(struct vcpu_svm *svm)
496 {
497 if (!vgif)
498 return NULL;
499
500 if (is_guest_mode(&svm->vcpu) && !nested_vgif_enabled(svm))
501 return svm->nested.vmcb02.ptr;
502 else
503 return svm->vmcb01.ptr;
504 }
505
506 static inline void enable_gif(struct vcpu_svm *svm)
507 {
508 struct vmcb *vmcb = get_vgif_vmcb(svm);
509
510 if (vmcb)
511 vmcb->control.int_ctl |= V_GIF_MASK;
512 else
513 svm->guest_gif = true;
514 }
515
516 static inline void disable_gif(struct vcpu_svm *svm)
517 {
518 struct vmcb *vmcb = get_vgif_vmcb(svm);
519
520 if (vmcb)
521 vmcb->control.int_ctl &= ~V_GIF_MASK;
522 else
523 svm->guest_gif = false;
524 }
525
526 static inline bool gif_set(struct vcpu_svm *svm)
527 {
528 struct vmcb *vmcb = get_vgif_vmcb(svm);
529
530 if (vmcb)
531 return !!(vmcb->control.int_ctl & V_GIF_MASK);
532 else
533 return svm->guest_gif;
534 }
535
536 static inline bool nested_npt_enabled(struct vcpu_svm *svm)
537 {
538 return svm->nested.ctl.nested_ctl & SVM_NESTED_CTL_NP_ENABLE;
539 }
540
541 static inline bool nested_vnmi_enabled(struct vcpu_svm *svm)
542 {
543 return guest_can_use(&svm->vcpu, X86_FEATURE_VNMI) &&
544 (svm->nested.ctl.int_ctl & V_NMI_ENABLE_MASK);
545 }
546
547 static inline bool is_x2apic_msrpm_offset(u32 offset)
548 {
549 /* 4 msrs per u8, and 4 u8 in u32 */
550 u32 msr = offset * 16;
551
552 return (msr >= APIC_BASE_MSR) &&
553 (msr < (APIC_BASE_MSR + 0x100));
554 }
555
556 static inline struct vmcb *get_vnmi_vmcb_l1(struct vcpu_svm *svm)
557 {
558 if (!vnmi)
559 return NULL;
560
561 if (is_guest_mode(&svm->vcpu))
562 return NULL;
563 else
564 return svm->vmcb01.ptr;
565 }
566
567 static inline bool is_vnmi_enabled(struct vcpu_svm *svm)
568 {
569 struct vmcb *vmcb = get_vnmi_vmcb_l1(svm);
570
571 if (vmcb)
572 return !!(vmcb->control.int_ctl & V_NMI_ENABLE_MASK);
573 else
574 return false;
575 }
576
577 /* svm.c */
578 #define MSR_INVALID 0xffffffffU
579
580 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
581
582 extern bool dump_invalid_vmcb;
583
584 u32 svm_msrpm_offset(u32 msr);
585 u32 *svm_vcpu_alloc_msrpm(void);
586 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm);
587 void svm_vcpu_free_msrpm(u32 *msrpm);
588 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb);
589 void svm_enable_lbrv(struct kvm_vcpu *vcpu);
590 void svm_update_lbrv(struct kvm_vcpu *vcpu);
591
592 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer);
593 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0);
594 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
595 void disable_nmi_singlestep(struct vcpu_svm *svm);
596 bool svm_smi_blocked(struct kvm_vcpu *vcpu);
597 bool svm_nmi_blocked(struct kvm_vcpu *vcpu);
598 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu);
599 void svm_set_gif(struct vcpu_svm *svm, bool value);
600 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code);
601 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
602 int read, int write);
603 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool disable);
604 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
605 int trig_mode, int vec);
606
607 /* nested.c */
608
609 #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
610 #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
611 #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
612
613 static inline bool nested_svm_virtualize_tpr(struct kvm_vcpu *vcpu)
614 {
615 struct vcpu_svm *svm = to_svm(vcpu);
616
617 return is_guest_mode(vcpu) && (svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK);
618 }
619
620 static inline bool nested_exit_on_smi(struct vcpu_svm *svm)
621 {
622 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SMI);
623 }
624
625 static inline bool nested_exit_on_intr(struct vcpu_svm *svm)
626 {
627 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_INTR);
628 }
629
630 static inline bool nested_exit_on_nmi(struct vcpu_svm *svm)
631 {
632 return vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_NMI);
633 }
634
635 int enter_svm_guest_mode(struct kvm_vcpu *vcpu,
636 u64 vmcb_gpa, struct vmcb *vmcb12, bool from_vmrun);
637 void svm_leave_nested(struct kvm_vcpu *vcpu);
638 void svm_free_nested(struct vcpu_svm *svm);
639 int svm_allocate_nested(struct vcpu_svm *svm);
640 int nested_svm_vmrun(struct kvm_vcpu *vcpu);
641 void svm_copy_vmrun_state(struct vmcb_save_area *to_save,
642 struct vmcb_save_area *from_save);
643 void svm_copy_vmloadsave_state(struct vmcb *to_vmcb, struct vmcb *from_vmcb);
644 int nested_svm_vmexit(struct vcpu_svm *svm);
645
646 static inline int nested_svm_simple_vmexit(struct vcpu_svm *svm, u32 exit_code)
647 {
648 svm->vmcb->control.exit_code = exit_code;
649 svm->vmcb->control.exit_info_1 = 0;
650 svm->vmcb->control.exit_info_2 = 0;
651 return nested_svm_vmexit(svm);
652 }
653
654 int nested_svm_exit_handled(struct vcpu_svm *svm);
655 int nested_svm_check_permissions(struct kvm_vcpu *vcpu);
656 int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
657 bool has_error_code, u32 error_code);
658 int nested_svm_exit_special(struct vcpu_svm *svm);
659 void nested_svm_update_tsc_ratio_msr(struct kvm_vcpu *vcpu);
660 void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu);
661 void nested_copy_vmcb_control_to_cache(struct vcpu_svm *svm,
662 struct vmcb_control_area *control);
663 void nested_copy_vmcb_save_to_cache(struct vcpu_svm *svm,
664 struct vmcb_save_area *save);
665 void nested_sync_control_from_vmcb02(struct vcpu_svm *svm);
666 void nested_vmcb02_compute_g_pat(struct vcpu_svm *svm);
667 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb);
668
669 extern struct kvm_x86_nested_ops svm_nested_ops;
670
671 /* avic.c */
672 #define AVIC_REQUIRED_APICV_INHIBITS \
673 ( \
674 BIT(APICV_INHIBIT_REASON_DISABLED) | \
675 BIT(APICV_INHIBIT_REASON_ABSENT) | \
676 BIT(APICV_INHIBIT_REASON_HYPERV) | \
677 BIT(APICV_INHIBIT_REASON_NESTED) | \
678 BIT(APICV_INHIBIT_REASON_IRQWIN) | \
679 BIT(APICV_INHIBIT_REASON_PIT_REINJ) | \
680 BIT(APICV_INHIBIT_REASON_BLOCKIRQ) | \
681 BIT(APICV_INHIBIT_REASON_SEV) | \
682 BIT(APICV_INHIBIT_REASON_PHYSICAL_ID_ALIASED) | \
683 BIT(APICV_INHIBIT_REASON_APIC_ID_MODIFIED) | \
684 BIT(APICV_INHIBIT_REASON_APIC_BASE_MODIFIED) | \
685 BIT(APICV_INHIBIT_REASON_LOGICAL_ID_ALIASED) \
686 )
687
688 bool avic_hardware_setup(void);
689 int avic_ga_log_notifier(u32 ga_tag);
690 void avic_vm_destroy(struct kvm *kvm);
691 int avic_vm_init(struct kvm *kvm);
692 void avic_init_vmcb(struct vcpu_svm *svm, struct vmcb *vmcb);
693 int avic_incomplete_ipi_interception(struct kvm_vcpu *vcpu);
694 int avic_unaccelerated_access_interception(struct kvm_vcpu *vcpu);
695 int avic_init_vcpu(struct vcpu_svm *svm);
696 void avic_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
697 void avic_vcpu_put(struct kvm_vcpu *vcpu);
698 void avic_apicv_post_state_restore(struct kvm_vcpu *vcpu);
699 void avic_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu);
700 int avic_pi_update_irte(struct kvm *kvm, unsigned int host_irq,
701 uint32_t guest_irq, bool set);
702 void avic_vcpu_blocking(struct kvm_vcpu *vcpu);
703 void avic_vcpu_unblocking(struct kvm_vcpu *vcpu);
704 void avic_ring_doorbell(struct kvm_vcpu *vcpu);
705 unsigned long avic_vcpu_get_apicv_inhibit_reasons(struct kvm_vcpu *vcpu);
706 void avic_refresh_virtual_apic_mode(struct kvm_vcpu *vcpu);
707
708
709 /* sev.c */
710
711 void pre_sev_run(struct vcpu_svm *svm, int cpu);
712 void sev_init_vmcb(struct vcpu_svm *svm);
713 void sev_vcpu_after_set_cpuid(struct vcpu_svm *svm);
714 int sev_es_string_io(struct vcpu_svm *svm, int size, unsigned int port, int in);
715 void sev_es_vcpu_reset(struct vcpu_svm *svm);
716 void sev_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector);
717 void sev_es_prepare_switch_to_guest(struct vcpu_svm *svm, struct sev_es_save_area *hostsa);
718 void sev_es_unmap_ghcb(struct vcpu_svm *svm);
719
720 #ifdef CONFIG_KVM_AMD_SEV
721 int sev_mem_enc_ioctl(struct kvm *kvm, void __user *argp);
722 int sev_mem_enc_register_region(struct kvm *kvm,
723 struct kvm_enc_region *range);
724 int sev_mem_enc_unregister_region(struct kvm *kvm,
725 struct kvm_enc_region *range);
726 int sev_vm_copy_enc_context_from(struct kvm *kvm, unsigned int source_fd);
727 int sev_vm_move_enc_context_from(struct kvm *kvm, unsigned int source_fd);
728 void sev_guest_memory_reclaimed(struct kvm *kvm);
729 int sev_handle_vmgexit(struct kvm_vcpu *vcpu);
730
731 /* These symbols are used in common code and are stubbed below. */
732
733 struct page *snp_safe_alloc_page_node(int node, gfp_t gfp);
734 static inline struct page *snp_safe_alloc_page(void)
735 {
736 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT);
737 }
738
739 void sev_free_vcpu(struct kvm_vcpu *vcpu);
740 void sev_vm_destroy(struct kvm *kvm);
741 void __init sev_set_cpu_caps(void);
742 void __init sev_hardware_setup(void);
743 void sev_hardware_unsetup(void);
744 int sev_cpu_init(struct svm_cpu_data *sd);
745 int sev_dev_get_attr(u32 group, u64 attr, u64 *val);
746 extern unsigned int max_sev_asid;
747 void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code);
748 void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu);
749 int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order);
750 void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end);
751 int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn);
752 #else
753 static inline struct page *snp_safe_alloc_page_node(int node, gfp_t gfp)
754 {
755 return alloc_pages_node(node, gfp | __GFP_ZERO, 0);
756 }
757
758 static inline struct page *snp_safe_alloc_page(void)
759 {
760 return snp_safe_alloc_page_node(numa_node_id(), GFP_KERNEL_ACCOUNT);
761 }
762
763 static inline void sev_free_vcpu(struct kvm_vcpu *vcpu) {}
764 static inline void sev_vm_destroy(struct kvm *kvm) {}
765 static inline void __init sev_set_cpu_caps(void) {}
766 static inline void __init sev_hardware_setup(void) {}
767 static inline void sev_hardware_unsetup(void) {}
768 static inline int sev_cpu_init(struct svm_cpu_data *sd) { return 0; }
769 static inline int sev_dev_get_attr(u32 group, u64 attr, u64 *val) { return -ENXIO; }
770 #define max_sev_asid 0
771 static inline void sev_handle_rmp_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u64 error_code) {}
772 static inline void sev_snp_init_protected_guest_state(struct kvm_vcpu *vcpu) {}
773 static inline int sev_gmem_prepare(struct kvm *kvm, kvm_pfn_t pfn, gfn_t gfn, int max_order)
774 {
775 return 0;
776 }
777 static inline void sev_gmem_invalidate(kvm_pfn_t start, kvm_pfn_t end) {}
778 static inline int sev_private_max_mapping_level(struct kvm *kvm, kvm_pfn_t pfn)
779 {
780 return 0;
781 }
782
783 #endif
784
785 /* vmenter.S */
786
787 void __svm_sev_es_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted,
788 struct sev_es_save_area *hostsa);
789 void __svm_vcpu_run(struct vcpu_svm *svm, bool spec_ctrl_intercepted);
790
791 #define DEFINE_KVM_GHCB_ACCESSORS(field) \
792 static __always_inline bool kvm_ghcb_##field##_is_valid(const struct vcpu_svm *svm) \
793 { \
794 return test_bit(GHCB_BITMAP_IDX(field), \
795 (unsigned long *)&svm->sev_es.valid_bitmap); \
796 } \
797 \
798 static __always_inline u64 kvm_ghcb_get_##field##_if_valid(struct vcpu_svm *svm, struct ghcb *ghcb) \
799 { \
800 return kvm_ghcb_##field##_is_valid(svm) ? ghcb->save.field : 0; \
801 } \
802
803 DEFINE_KVM_GHCB_ACCESSORS(cpl)
804 DEFINE_KVM_GHCB_ACCESSORS(rax)
805 DEFINE_KVM_GHCB_ACCESSORS(rcx)
806 DEFINE_KVM_GHCB_ACCESSORS(rdx)
807 DEFINE_KVM_GHCB_ACCESSORS(rbx)
808 DEFINE_KVM_GHCB_ACCESSORS(rsi)
809 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_code)
810 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_1)
811 DEFINE_KVM_GHCB_ACCESSORS(sw_exit_info_2)
812 DEFINE_KVM_GHCB_ACCESSORS(sw_scratch)
813 DEFINE_KVM_GHCB_ACCESSORS(xcr0)
814
815 #endif
816
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