1 # SPDX-License-Identifier: GPL-2.0 2 config XTENSA 3 def_bool y 4 select ARCH_32BIT_OFF_T 5 select ARCH_HAS_CPU_CACHE_ALIASING 6 select ARCH_HAS_BINFMT_FLAT if !MMU 7 select ARCH_HAS_CURRENT_STACK_POINTER 8 select ARCH_HAS_DEBUG_VM_PGTABLE 9 select ARCH_HAS_DMA_PREP_COHERENT if MMU 10 select ARCH_HAS_GCOV_PROFILE_ALL 11 select ARCH_HAS_KCOV 12 select ARCH_HAS_SYNC_DMA_FOR_CPU if MMU 13 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if MMU 14 select ARCH_HAS_DMA_SET_UNCACHED if MMU 15 select ARCH_HAS_STRNCPY_FROM_USER if !KASAN 16 select ARCH_HAS_STRNLEN_USER 17 select ARCH_NEED_CMPXCHG_1_EMU 18 select ARCH_USE_MEMTEST 19 select ARCH_USE_QUEUED_RWLOCKS 20 select ARCH_USE_QUEUED_SPINLOCKS 21 select ARCH_WANT_IPC_PARSE_VERSION 22 select BUILDTIME_TABLE_SORT 23 select CLONE_BACKWARDS 24 select COMMON_CLK 25 select DMA_NONCOHERENT_MMAP if MMU 26 select GENERIC_ATOMIC64 27 select GENERIC_IRQ_SHOW 28 select GENERIC_LIB_CMPDI2 29 select GENERIC_LIB_MULDI3 30 select GENERIC_LIB_UCMPDI2 31 select GENERIC_PCI_IOMAP 32 select GENERIC_SCHED_CLOCK 33 select GENERIC_IOREMAP if MMU 34 select HAVE_ARCH_AUDITSYSCALL 35 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL 36 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL 37 select HAVE_ARCH_KCSAN 38 select HAVE_ARCH_SECCOMP_FILTER 39 select HAVE_ARCH_TRACEHOOK 40 select HAVE_ASM_MODVERSIONS 41 select HAVE_CONTEXT_TRACKING_USER 42 select HAVE_DEBUG_KMEMLEAK 43 select HAVE_DMA_CONTIGUOUS 44 select HAVE_EXIT_THREAD 45 select HAVE_FUNCTION_TRACER 46 select HAVE_GCC_PLUGINS if GCC_VERSION >= 120000 47 select HAVE_HW_BREAKPOINT if PERF_EVENTS 48 select HAVE_IRQ_TIME_ACCOUNTING 49 select HAVE_PAGE_SIZE_4KB 50 select HAVE_PCI 51 select HAVE_PERF_EVENTS 52 select HAVE_STACKPROTECTOR 53 select HAVE_SYSCALL_TRACEPOINTS 54 select HAVE_VIRT_CPU_ACCOUNTING_GEN 55 select IRQ_DOMAIN 56 select LOCK_MM_AND_FIND_VMA 57 select MODULES_USE_ELF_RELA 58 select PERF_USE_VMALLOC 59 select TRACE_IRQFLAGS_SUPPORT 60 help 61 Xtensa processors are 32-bit RISC machines designed by Tensilica 62 primarily for embedded systems. These processors are both 63 configurable and extensible. The Linux port to the Xtensa 64 architecture supports all processor configurations and extensions, 65 with reasonable minimum requirements. The Xtensa Linux project has 66 a home page at <http://www.linux-xtensa.org/>. 67 68 config GENERIC_HWEIGHT 69 def_bool y 70 71 config ARCH_HAS_ILOG2_U32 72 def_bool n 73 74 config ARCH_HAS_ILOG2_U64 75 def_bool n 76 77 config ARCH_MTD_XIP 78 def_bool y 79 80 config NO_IOPORT_MAP 81 def_bool n 82 83 config HZ 84 int 85 default 100 86 87 config LOCKDEP_SUPPORT 88 def_bool y 89 90 config STACKTRACE_SUPPORT 91 def_bool y 92 93 config MMU 94 def_bool n 95 select PFAULT 96 97 config HAVE_XTENSA_GPIO32 98 def_bool n 99 100 config KASAN_SHADOW_OFFSET 101 hex 102 default 0x6e400000 103 104 config CPU_BIG_ENDIAN 105 def_bool $(success,test "$(shell,echo __XTENSA_EB__ | $(CC) -E -P -)" = 1) 106 107 config CPU_LITTLE_ENDIAN 108 def_bool !CPU_BIG_ENDIAN 109 110 config CC_HAVE_CALL0_ABI 111 def_bool $(success,test "$(shell,echo __XTENSA_CALL0_ABI__ | $(CC) -mabi=call0 -E -P - 2>/dev/null)" = 1) 112 113 menu "Processor type and features" 114 115 choice 116 prompt "Xtensa Processor Configuration" 117 default XTENSA_VARIANT_FSF 118 119 config XTENSA_VARIANT_FSF 120 bool "fsf - default (not generic) configuration" 121 select MMU 122 123 config XTENSA_VARIANT_DC232B 124 bool "dc232b - Diamond 232L Standard Core Rev.B (LE)" 125 select MMU 126 select HAVE_XTENSA_GPIO32 127 help 128 This variant refers to Tensilica's Diamond 232L Standard core Rev.B (LE). 129 130 config XTENSA_VARIANT_DC233C 131 bool "dc233c - Diamond 233L Standard Core Rev.C (LE)" 132 select MMU 133 select HAVE_XTENSA_GPIO32 134 help 135 This variant refers to Tensilica's Diamond 233L Standard core Rev.C (LE). 136 137 config XTENSA_VARIANT_CUSTOM 138 bool "Custom Xtensa processor configuration" 139 select HAVE_XTENSA_GPIO32 140 help 141 Select this variant to use a custom Xtensa processor configuration. 142 You will be prompted for a processor variant CORENAME. 143 endchoice 144 145 config XTENSA_VARIANT_CUSTOM_NAME 146 string "Xtensa Processor Custom Core Variant Name" 147 depends on XTENSA_VARIANT_CUSTOM 148 help 149 Provide the name of a custom Xtensa processor variant. 150 This CORENAME selects arch/xtensa/variants/CORENAME. 151 Don't forget you have to select MMU if you have one. 152 153 config XTENSA_VARIANT_NAME 154 string 155 default "dc232b" if XTENSA_VARIANT_DC232B 156 default "dc233c" if XTENSA_VARIANT_DC233C 157 default "fsf" if XTENSA_VARIANT_FSF 158 default XTENSA_VARIANT_CUSTOM_NAME if XTENSA_VARIANT_CUSTOM 159 160 config XTENSA_VARIANT_MMU 161 bool "Core variant has a Full MMU (TLB, Pages, Protection, etc)" 162 depends on XTENSA_VARIANT_CUSTOM 163 default y 164 select MMU 165 help 166 Build a Conventional Kernel with full MMU support, 167 ie: it supports a TLB with auto-loading, page protection. 168 169 config XTENSA_VARIANT_HAVE_PERF_EVENTS 170 bool "Core variant has Performance Monitor Module" 171 depends on XTENSA_VARIANT_CUSTOM 172 default n 173 help 174 Enable if core variant has Performance Monitor Module with 175 External Registers Interface. 176 177 If unsure, say N. 178 179 config XTENSA_FAKE_NMI 180 bool "Treat PMM IRQ as NMI" 181 depends on XTENSA_VARIANT_HAVE_PERF_EVENTS 182 default n 183 help 184 If PMM IRQ is the only IRQ at EXCM level it is safe to 185 treat it as NMI, which improves accuracy of profiling. 186 187 If there are other interrupts at or above PMM IRQ priority level 188 but not above the EXCM level, PMM IRQ still may be treated as NMI, 189 but only if these IRQs are not used. There will be a build warning 190 saying that this is not safe, and a bugcheck if one of these IRQs 191 actually fire. 192 193 If unsure, say N. 194 195 config PFAULT 196 bool "Handle protection faults" if EXPERT && !MMU 197 default y 198 help 199 Handle protection faults. MMU configurations must enable it. 200 noMMU configurations may disable it if used memory map never 201 generates protection faults or faults are always fatal. 202 203 If unsure, say Y. 204 205 config XTENSA_UNALIGNED_USER 206 bool "Unaligned memory access in user space" 207 help 208 The Xtensa architecture currently does not handle unaligned 209 memory accesses in hardware but through an exception handler. 210 Per default, unaligned memory accesses are disabled in user space. 211 212 Say Y here to enable unaligned memory access in user space. 213 214 config XTENSA_LOAD_STORE 215 bool "Load/store exception handler for memory only readable with l32" 216 help 217 The Xtensa architecture only allows reading memory attached to its 218 instruction bus with l32r and l32i instructions, all other 219 instructions raise an exception with the LoadStoreErrorCause code. 220 This makes it hard to use some configurations, e.g. store string 221 literals in FLASH memory attached to the instruction bus. 222 223 Say Y here to enable exception handler that allows transparent 224 byte and 2-byte access to memory attached to instruction bus. 225 226 config HAVE_SMP 227 bool "System Supports SMP (MX)" 228 depends on XTENSA_VARIANT_CUSTOM 229 select XTENSA_MX 230 help 231 This option is used to indicate that the system-on-a-chip (SOC) 232 supports Multiprocessing. Multiprocessor support implemented above 233 the CPU core definition and currently needs to be selected manually. 234 235 Multiprocessor support is implemented with external cache and 236 interrupt controllers. 237 238 The MX interrupt distributer adds Interprocessor Interrupts 239 and causes the IRQ numbers to be increased by 4 for devices 240 like the open cores ethernet driver and the serial interface. 241 242 You still have to select "Enable SMP" to enable SMP on this SOC. 243 244 config SMP 245 bool "Enable Symmetric multi-processing support" 246 depends on HAVE_SMP 247 select GENERIC_SMP_IDLE_THREAD 248 help 249 Enabled SMP Software; allows more than one CPU/CORE 250 to be activated during startup. 251 252 config NR_CPUS 253 depends on SMP 254 int "Maximum number of CPUs (2-32)" 255 range 2 32 256 default "4" 257 258 config HOTPLUG_CPU 259 bool "Enable CPU hotplug support" 260 depends on SMP 261 help 262 Say Y here to allow turning CPUs off and on. CPUs can be 263 controlled through /sys/devices/system/cpu. 264 265 Say N if you want to disable CPU hotplug. 266 267 config SECONDARY_RESET_VECTOR 268 bool "Secondary cores use alternative reset vector" 269 default y 270 depends on HAVE_SMP 271 help 272 Secondary cores may be configured to use alternative reset vector, 273 or all cores may use primary reset vector. 274 Say Y here to supply handler for the alternative reset location. 275 276 config FAST_SYSCALL_XTENSA 277 bool "Enable fast atomic syscalls" 278 default n 279 help 280 fast_syscall_xtensa is a syscall that can make atomic operations 281 on UP kernel when processor has no s32c1i support. 282 283 This syscall is deprecated. It may have issues when called with 284 invalid arguments. It is provided only for backwards compatibility. 285 Only enable it if your userspace software requires it. 286 287 If unsure, say N. 288 289 config FAST_SYSCALL_SPILL_REGISTERS 290 bool "Enable spill registers syscall" 291 default n 292 help 293 fast_syscall_spill_registers is a syscall that spills all active 294 register windows of a calling userspace task onto its stack. 295 296 This syscall is deprecated. It may have issues when called with 297 invalid arguments. It is provided only for backwards compatibility. 298 Only enable it if your userspace software requires it. 299 300 If unsure, say N. 301 302 choice 303 prompt "Kernel ABI" 304 default KERNEL_ABI_DEFAULT 305 help 306 Select ABI for the kernel code. This ABI is independent of the 307 supported userspace ABI and any combination of the 308 kernel/userspace ABI is possible and should work. 309 310 In case both kernel and userspace support only call0 ABI 311 all register windows support code will be omitted from the 312 build. 313 314 If unsure, choose the default ABI. 315 316 config KERNEL_ABI_DEFAULT 317 bool "Default ABI" 318 help 319 Select this option to compile kernel code with the default ABI 320 selected for the toolchain. 321 Normally cores with windowed registers option use windowed ABI and 322 cores without it use call0 ABI. 323 324 config KERNEL_ABI_CALL0 325 bool "Call0 ABI" if CC_HAVE_CALL0_ABI 326 help 327 Select this option to compile kernel code with call0 ABI even with 328 toolchain that defaults to windowed ABI. 329 When this option is not selected the default toolchain ABI will 330 be used for the kernel code. 331 332 endchoice 333 334 config USER_ABI_CALL0 335 bool 336 337 choice 338 prompt "Userspace ABI" 339 default USER_ABI_DEFAULT 340 help 341 Select supported userspace ABI. 342 343 If unsure, choose the default ABI. 344 345 config USER_ABI_DEFAULT 346 bool "Default ABI only" 347 help 348 Assume default userspace ABI. For XEA2 cores it is windowed ABI. 349 call0 ABI binaries may be run on such kernel, but signal delivery 350 will not work correctly for them. 351 352 config USER_ABI_CALL0_ONLY 353 bool "Call0 ABI only" 354 select USER_ABI_CALL0 355 help 356 Select this option to support only call0 ABI in userspace. 357 Windowed ABI binaries will crash with a segfault caused by 358 an illegal instruction exception on the first 'entry' opcode. 359 360 Choose this option if you're planning to run only user code 361 built with call0 ABI. 362 363 config USER_ABI_CALL0_PROBE 364 bool "Support both windowed and call0 ABI by probing" 365 select USER_ABI_CALL0 366 help 367 Select this option to support both windowed and call0 userspace 368 ABIs. When enabled all processes are started with PS.WOE disabled 369 and a fast user exception handler for an illegal instruction is 370 used to turn on PS.WOE bit on the first 'entry' opcode executed by 371 the userspace. 372 373 This option should be enabled for the kernel that must support 374 both call0 and windowed ABIs in userspace at the same time. 375 376 Note that Xtensa ISA does not guarantee that entry opcode will 377 raise an illegal instruction exception on cores with XEA2 when 378 PS.WOE is disabled, check whether the target core supports it. 379 380 endchoice 381 382 endmenu 383 384 config XTENSA_CALIBRATE_CCOUNT 385 def_bool n 386 help 387 On some platforms (XT2000, for example), the CPU clock rate can 388 vary. The frequency can be determined, however, by measuring 389 against a well known, fixed frequency, such as an UART oscillator. 390 391 config SERIAL_CONSOLE 392 def_bool n 393 394 config PLATFORM_HAVE_XIP 395 def_bool n 396 397 menu "Platform options" 398 399 choice 400 prompt "Xtensa System Type" 401 default XTENSA_PLATFORM_ISS 402 403 config XTENSA_PLATFORM_ISS 404 bool "ISS" 405 select XTENSA_CALIBRATE_CCOUNT 406 select SERIAL_CONSOLE 407 help 408 ISS is an acronym for Tensilica's Instruction Set Simulator. 409 410 config XTENSA_PLATFORM_XT2000 411 bool "XT2000" 412 help 413 XT2000 is the name of Tensilica's feature-rich emulation platform. 414 This hardware is capable of running a full Linux distribution. 415 416 config XTENSA_PLATFORM_XTFPGA 417 bool "XTFPGA" 418 select ETHOC if ETHERNET 419 select PLATFORM_WANT_DEFAULT_MEM if !MMU 420 select SERIAL_CONSOLE 421 select XTENSA_CALIBRATE_CCOUNT 422 select PLATFORM_HAVE_XIP 423 help 424 XTFPGA is the name of Tensilica board family (LX60, LX110, LX200, ML605). 425 This hardware is capable of running a full Linux distribution. 426 427 endchoice 428 429 config PLATFORM_NR_IRQS 430 int 431 default 3 if XTENSA_PLATFORM_XT2000 432 default 0 433 434 config XTENSA_CPU_CLOCK 435 int "CPU clock rate [MHz]" 436 depends on !XTENSA_CALIBRATE_CCOUNT 437 default 16 438 439 config GENERIC_CALIBRATE_DELAY 440 bool "Auto calibration of the BogoMIPS value" 441 help 442 The BogoMIPS value can easily be derived from the CPU frequency. 443 444 config CMDLINE_BOOL 445 bool "Default bootloader kernel arguments" 446 447 config CMDLINE 448 string "Initial kernel command string" 449 depends on CMDLINE_BOOL 450 default "console=ttyS0,38400 root=/dev/ram" 451 help 452 On some architectures (EBSA110 and CATS), there is currently no way 453 for the boot loader to pass arguments to the kernel. For these 454 architectures, you should supply some command-line options at build 455 time by entering them here. As a minimum, you should specify the 456 memory size and the root device (e.g., mem=64M root=/dev/nfs). 457 458 config USE_OF 459 bool "Flattened Device Tree support" 460 select OF 461 select OF_EARLY_FLATTREE 462 help 463 Include support for flattened device tree machine descriptions. 464 465 config BUILTIN_DTB_SOURCE 466 string "DTB to build into the kernel image" 467 depends on OF 468 469 config PARSE_BOOTPARAM 470 bool "Parse bootparam block" 471 default y 472 help 473 Parse parameters passed to the kernel from the bootloader. It may 474 be disabled if the kernel is known to run without the bootloader. 475 476 If unsure, say Y. 477 478 choice 479 prompt "Semihosting interface" 480 default XTENSA_SIMCALL_ISS 481 depends on XTENSA_PLATFORM_ISS 482 help 483 Choose semihosting interface that will be used for serial port, 484 block device and networking. 485 486 config XTENSA_SIMCALL_ISS 487 bool "simcall" 488 help 489 Use simcall instruction. simcall is only available on simulators, 490 it does nothing on hardware. 491 492 config XTENSA_SIMCALL_GDBIO 493 bool "GDBIO" 494 help 495 Use break instruction. It is available on real hardware when GDB 496 is attached to it via JTAG. 497 498 endchoice 499 500 config BLK_DEV_SIMDISK 501 tristate "Host file-based simulated block device support" 502 default n 503 depends on XTENSA_PLATFORM_ISS && BLOCK 504 help 505 Create block devices that map to files in the host file system. 506 Device binding to host file may be changed at runtime via proc 507 interface provided the device is not in use. 508 509 config BLK_DEV_SIMDISK_COUNT 510 int "Number of host file-based simulated block devices" 511 range 1 10 512 depends on BLK_DEV_SIMDISK 513 default 2 514 help 515 This is the default minimal number of created block devices. 516 Kernel/module parameter 'simdisk_count' may be used to change this 517 value at runtime. More file names (but no more than 10) may be 518 specified as parameters, simdisk_count grows accordingly. 519 520 config SIMDISK0_FILENAME 521 string "Host filename for the first simulated device" 522 depends on BLK_DEV_SIMDISK = y 523 default "" 524 help 525 Attach a first simdisk to a host file. Conventionally, this file 526 contains a root file system. 527 528 config SIMDISK1_FILENAME 529 string "Host filename for the second simulated device" 530 depends on BLK_DEV_SIMDISK = y && BLK_DEV_SIMDISK_COUNT != 1 531 default "" 532 help 533 Another simulated disk in a host file for a buildroot-independent 534 storage. 535 536 config XTFPGA_LCD 537 bool "Enable XTFPGA LCD driver" 538 depends on XTENSA_PLATFORM_XTFPGA 539 default n 540 help 541 There's a 2x16 LCD on most of XTFPGA boards, kernel may output 542 progress messages there during bootup/shutdown. It may be useful 543 during board bringup. 544 545 If unsure, say N. 546 547 config XTFPGA_LCD_BASE_ADDR 548 hex "XTFPGA LCD base address" 549 depends on XTFPGA_LCD 550 default "0x0d0c0000" 551 help 552 Base address of the LCD controller inside KIO region. 553 Different boards from XTFPGA family have LCD controller at different 554 addresses. Please consult prototyping user guide for your board for 555 the correct address. Wrong address here may lead to hardware lockup. 556 557 config XTFPGA_LCD_8BIT_ACCESS 558 bool "Use 8-bit access to XTFPGA LCD" 559 depends on XTFPGA_LCD 560 default n 561 help 562 LCD may be connected with 4- or 8-bit interface, 8-bit access may 563 only be used with 8-bit interface. Please consult prototyping user 564 guide for your board for the correct interface width. 565 566 comment "Kernel memory layout" 567 568 config INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 569 bool "Initialize Xtensa MMU inside the Linux kernel code" 570 depends on !XTENSA_VARIANT_FSF && !XTENSA_VARIANT_DC232B 571 default y if XTENSA_VARIANT_DC233C || XTENSA_VARIANT_CUSTOM 572 help 573 Earlier version initialized the MMU in the exception vector 574 before jumping to _startup in head.S and had an advantage that 575 it was possible to place a software breakpoint at 'reset' and 576 then enter your normal kernel breakpoints once the MMU was mapped 577 to the kernel mappings (0XC0000000). 578 579 This unfortunately won't work for U-Boot and likely also won't 580 work for using KEXEC to have a hot kernel ready for doing a 581 KDUMP. 582 583 So now the MMU is initialized in head.S but it's necessary to 584 use hardware breakpoints (gdb 'hbreak' cmd) to break at _startup. 585 xt-gdb can't place a Software Breakpoint in the 0XD region prior 586 to mapping the MMU and after mapping even if the area of low memory 587 was mapped gdb wouldn't remove the breakpoint on hitting it as the 588 PC wouldn't match. Since Hardware Breakpoints are recommended for 589 Linux configurations it seems reasonable to just assume they exist 590 and leave this older mechanism for unfortunate souls that choose 591 not to follow Tensilica's recommendation. 592 593 Selecting this will cause U-Boot to set the KERNEL Load and Entry 594 address at 0x00003000 instead of the mapped std of 0xD0003000. 595 596 If in doubt, say Y. 597 598 config XIP_KERNEL 599 bool "Kernel Execute-In-Place from ROM" 600 depends on PLATFORM_HAVE_XIP 601 help 602 Execute-In-Place allows the kernel to run from non-volatile storage 603 directly addressable by the CPU, such as NOR flash. This saves RAM 604 space since the text section of the kernel is not loaded from flash 605 to RAM. Read-write sections, such as the data section and stack, 606 are still copied to RAM. The XIP kernel is not compressed since 607 it has to run directly from flash, so it will take more space to 608 store it. The flash address used to link the kernel object files, 609 and for storing it, is configuration dependent. Therefore, if you 610 say Y here, you must know the proper physical address where to 611 store the kernel image depending on your own flash memory usage. 612 613 Also note that the make target becomes "make xipImage" rather than 614 "make Image" or "make uImage". The final kernel binary to put in 615 ROM memory will be arch/xtensa/boot/xipImage. 616 617 If unsure, say N. 618 619 config MEMMAP_CACHEATTR 620 hex "Cache attributes for the memory address space" 621 depends on !MMU 622 default 0x22222222 623 help 624 These cache attributes are set up for noMMU systems. Each hex digit 625 specifies cache attributes for the corresponding 512MB memory 626 region: bits 0..3 -- for addresses 0x00000000..0x1fffffff, 627 bits 4..7 -- for addresses 0x20000000..0x3fffffff, and so on. 628 629 Cache attribute values are specific for the MMU type. 630 For region protection MMUs: 631 1: WT cached, 632 2: cache bypass, 633 4: WB cached, 634 f: illegal. 635 For full MMU: 636 bit 0: executable, 637 bit 1: writable, 638 bits 2..3: 639 0: cache bypass, 640 1: WB cache, 641 2: WT cache, 642 3: special (c and e are illegal, f is reserved). 643 For MPU: 644 0: illegal, 645 1: WB cache, 646 2: WB, no-write-allocate cache, 647 3: WT cache, 648 4: cache bypass. 649 650 config KSEG_PADDR 651 hex "Physical address of the KSEG mapping" 652 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX && MMU 653 default 0x00000000 654 help 655 This is the physical address where KSEG is mapped. Please refer to 656 the chosen KSEG layout help for the required address alignment. 657 Unpacked kernel image (including vectors) must be located completely 658 within KSEG. 659 Physical memory below this address is not available to linux. 660 661 If unsure, leave the default value here. 662 663 config KERNEL_VIRTUAL_ADDRESS 664 hex "Kernel virtual address" 665 depends on MMU && XIP_KERNEL 666 default 0xd0003000 667 help 668 This is the virtual address where the XIP kernel is mapped. 669 XIP kernel may be mapped into KSEG or KIO region, virtual address 670 provided here must match kernel load address provided in 671 KERNEL_LOAD_ADDRESS. 672 673 config KERNEL_LOAD_ADDRESS 674 hex "Kernel load address" 675 default 0x60003000 if !MMU 676 default 0x00003000 if MMU && INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 677 default 0xd0003000 if MMU && !INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 678 help 679 This is the address where the kernel is loaded. 680 It is virtual address for MMUv2 configurations and physical address 681 for all other configurations. 682 683 If unsure, leave the default value here. 684 685 choice 686 prompt "Relocatable vectors location" 687 default XTENSA_VECTORS_IN_TEXT 688 help 689 Choose whether relocatable vectors are merged into the kernel .text 690 or placed separately at runtime. This option does not affect 691 configurations without VECBASE register where vectors are always 692 placed at their hardware-defined locations. 693 694 config XTENSA_VECTORS_IN_TEXT 695 bool "Merge relocatable vectors into kernel text" 696 depends on !MTD_XIP 697 help 698 This option puts relocatable vectors into the kernel .text section 699 with proper alignment. 700 This is a safe choice for most configurations. 701 702 config XTENSA_VECTORS_SEPARATE 703 bool "Put relocatable vectors at fixed address" 704 help 705 This option puts relocatable vectors at specific virtual address. 706 Vectors are merged with the .init data in the kernel image and 707 are copied into their designated location during kernel startup. 708 Use it to put vectors into IRAM or out of FLASH on kernels with 709 XIP-aware MTD support. 710 711 endchoice 712 713 config VECTORS_ADDR 714 hex "Kernel vectors virtual address" 715 default 0x00000000 716 depends on XTENSA_VECTORS_SEPARATE 717 help 718 This is the virtual address of the (relocatable) vectors base. 719 It must be within KSEG if MMU is used. 720 721 config XIP_DATA_ADDR 722 hex "XIP kernel data virtual address" 723 depends on XIP_KERNEL 724 default 0x00000000 725 help 726 This is the virtual address where XIP kernel data is copied. 727 It must be within KSEG if MMU is used. 728 729 config PLATFORM_WANT_DEFAULT_MEM 730 def_bool n 731 732 config DEFAULT_MEM_START 733 hex 734 prompt "PAGE_OFFSET/PHYS_OFFSET" if !MMU && PLATFORM_WANT_DEFAULT_MEM 735 default 0x60000000 if PLATFORM_WANT_DEFAULT_MEM 736 default 0x00000000 737 help 738 This is the base address used for both PAGE_OFFSET and PHYS_OFFSET 739 in noMMU configurations. 740 741 If unsure, leave the default value here. 742 743 choice 744 prompt "KSEG layout" 745 depends on MMU 746 default XTENSA_KSEG_MMU_V2 747 748 config XTENSA_KSEG_MMU_V2 749 bool "MMUv2: 128MB cached + 128MB uncached" 750 help 751 MMUv2 compatible kernel memory map: TLB way 5 maps 128MB starting 752 at KSEG_PADDR to 0xd0000000 with cache and to 0xd8000000 753 without cache. 754 KSEG_PADDR must be aligned to 128MB. 755 756 config XTENSA_KSEG_256M 757 bool "256MB cached + 256MB uncached" 758 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 759 help 760 TLB way 6 maps 256MB starting at KSEG_PADDR to 0xb0000000 761 with cache and to 0xc0000000 without cache. 762 KSEG_PADDR must be aligned to 256MB. 763 764 config XTENSA_KSEG_512M 765 bool "512MB cached + 512MB uncached" 766 depends on INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX 767 help 768 TLB way 6 maps 512MB starting at KSEG_PADDR to 0xa0000000 769 with cache and to 0xc0000000 without cache. 770 KSEG_PADDR must be aligned to 256MB. 771 772 endchoice 773 774 config HIGHMEM 775 bool "High Memory Support" 776 depends on MMU 777 select KMAP_LOCAL 778 help 779 Linux can use the full amount of RAM in the system by 780 default. However, the default MMUv2 setup only maps the 781 lowermost 128 MB of memory linearly to the areas starting 782 at 0xd0000000 (cached) and 0xd8000000 (uncached). 783 When there are more than 128 MB memory in the system not 784 all of it can be "permanently mapped" by the kernel. 785 The physical memory that's not permanently mapped is called 786 "high memory". 787 788 If you are compiling a kernel which will never run on a 789 machine with more than 128 MB total physical RAM, answer 790 N here. 791 792 If unsure, say Y. 793 794 config ARCH_FORCE_MAX_ORDER 795 int "Order of maximal physically contiguous allocations" 796 default "10" 797 help 798 The kernel page allocator limits the size of maximal physically 799 contiguous allocations. The limit is called MAX_PAGE_ORDER and it 800 defines the maximal power of two of number of pages that can be 801 allocated as a single contiguous block. This option allows 802 overriding the default setting when ability to allocate very 803 large blocks of physically contiguous memory is required. 804 805 Don't change if unsure. 806 807 endmenu 808 809 menu "Power management options" 810 811 config ARCH_HIBERNATION_POSSIBLE 812 def_bool y 813 814 source "kernel/power/Kconfig" 815 816 endmenu
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