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Linux/arch/xtensa/include/asm/pgtable.h

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  1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*
  3  * include/asm-xtensa/pgtable.h
  4  *
  5  * Copyright (C) 2001 - 2013 Tensilica Inc.
  6  */
  7 
  8 #ifndef _XTENSA_PGTABLE_H
  9 #define _XTENSA_PGTABLE_H
 10 
 11 #include <asm/page.h>
 12 #include <asm/kmem_layout.h>
 13 #include <asm-generic/pgtable-nopmd.h>
 14 
 15 /*
 16  * We only use two ring levels, user and kernel space.
 17  */
 18 
 19 #ifdef CONFIG_MMU
 20 #define USER_RING               1       /* user ring level */
 21 #else
 22 #define USER_RING               0
 23 #endif
 24 #define KERNEL_RING             0       /* kernel ring level */
 25 
 26 /*
 27  * The Xtensa architecture port of Linux has a two-level page table system,
 28  * i.e. the logical three-level Linux page table layout is folded.
 29  * Each task has the following memory page tables:
 30  *
 31  *   PGD table (page directory), ie. 3rd-level page table:
 32  *      One page (4 kB) of 1024 (PTRS_PER_PGD) pointers to PTE tables
 33  *      (Architectures that don't have the PMD folded point to the PMD tables)
 34  *
 35  *      The pointer to the PGD table for a given task can be retrieved from
 36  *      the task structure (struct task_struct*) t, e.g. current():
 37  *        (t->mm ? t->mm : t->active_mm)->pgd
 38  *
 39  *   PMD tables (page middle-directory), ie. 2nd-level page tables:
 40  *      Absent for the Xtensa architecture (folded, PTRS_PER_PMD == 1).
 41  *
 42  *   PTE tables (page table entry), ie. 1st-level page tables:
 43  *      One page (4 kB) of 1024 (PTRS_PER_PTE) PTEs with a special PTE
 44  *      invalid_pte_table for absent mappings.
 45  *
 46  * The individual pages are 4 kB big with special pages for the empty_zero_page.
 47  */
 48 
 49 #define PGDIR_SHIFT     22
 50 #define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
 51 #define PGDIR_MASK      (~(PGDIR_SIZE-1))
 52 
 53 /*
 54  * Entries per page directory level: we use two-level, so
 55  * we don't really have any PMD directory physically.
 56  */
 57 #define PTRS_PER_PTE            1024
 58 #define PTRS_PER_PTE_SHIFT      10
 59 #define PTRS_PER_PGD            1024
 60 #define USER_PTRS_PER_PGD       (TASK_SIZE/PGDIR_SIZE)
 61 #define FIRST_USER_PGD_NR       (FIRST_USER_ADDRESS >> PGDIR_SHIFT)
 62 
 63 #ifdef CONFIG_MMU
 64 /*
 65  * Virtual memory area. We keep a distance to other memory regions to be
 66  * on the safe side. We also use this area for cache aliasing.
 67  */
 68 #define VMALLOC_START           (XCHAL_KSEG_CACHED_VADDR - 0x10000000)
 69 #define VMALLOC_END             (VMALLOC_START + 0x07FEFFFF)
 70 #define TLBTEMP_BASE_1          (VMALLOC_START + 0x08000000)
 71 #define TLBTEMP_BASE_2          (TLBTEMP_BASE_1 + DCACHE_WAY_SIZE)
 72 #if 2 * DCACHE_WAY_SIZE > ICACHE_WAY_SIZE
 73 #define TLBTEMP_SIZE            (2 * DCACHE_WAY_SIZE)
 74 #else
 75 #define TLBTEMP_SIZE            ICACHE_WAY_SIZE
 76 #endif
 77 
 78 #else
 79 
 80 #define VMALLOC_START           __XTENSA_UL_CONST(0)
 81 #define VMALLOC_END             __XTENSA_UL_CONST(0xffffffff)
 82 
 83 #endif
 84 
 85 /*
 86  * For the Xtensa architecture, the PTE layout is as follows:
 87  *
 88  *              31------12  11  10-9   8-6  5-4  3-2  1-0
 89  *              +-----------------------------------------+
 90  *              |           |   Software   |   HARDWARE   |
 91  *              |    PPN    |          ADW | RI |Attribute|
 92  *              +-----------------------------------------+
 93  *   pte_none   |             MBZ          | 01 | 11 | 00 |
 94  *              +-----------------------------------------+
 95  *   present    |    PPN    | 0 | 00 | ADW | RI | CA | wx |
 96  *              +- - - - - - - - - - - - - - - - - - - - -+
 97  *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 11 | 11 |
 98  *              +-----------------------------------------+
 99  *   swap       |     index     |   type   | 01 | 11 | e0 |
100  *              +-----------------------------------------+
101  *
102  * For T1050 hardware and earlier the layout differs for present and (PAGE_NONE)
103  *              +-----------------------------------------+
104  *   present    |    PPN    | 0 | 00 | ADW | RI | CA | w1 |
105  *              +-----------------------------------------+
106  *   (PAGE_NONE)|    PPN    | 0 | 00 | ADW | 01 | 01 | 00 |
107  *              +-----------------------------------------+
108  *
109  *  Legend:
110  *   PPN        Physical Page Number
111  *   ADW        software: accessed (young) / dirty / writable
112  *   RI         ring (0=privileged, 1=user, 2 and 3 are unused)
113  *   CA         cache attribute: 00 bypass, 01 writeback, 10 writethrough
114  *              (11 is invalid and used to mark pages that are not present)
115  *   e          exclusive marker in swap PTEs
116  *   w          page is writable (hw)
117  *   x          page is executable (hw)
118  *   index      swap offset / PAGE_SIZE (bit 11-31: 21 bits -> 8 GB)
119  *              (note that the index is always non-zero)
120  *   type       swap type (5 bits -> 32 types)
121  *
122  *  Notes:
123  *   - (PROT_NONE) is a special case of 'present' but causes an exception for
124  *     any access (read, write, and execute).
125  *   - 'multihit-exception' has the highest priority of all MMU exceptions,
126  *     so the ring must be set to 'RING_USER' even for 'non-present' pages.
127  *   - on older hardware, the exectuable flag was not supported and
128  *     used as a 'valid' flag, so it needs to be always set.
129  *   - we need to keep track of certain flags in software (dirty and young)
130  *     to do this, we use write exceptions and have a separate software w-flag.
131  *   - attribute value 1101 (and 1111 on T1050 and earlier) is reserved
132  */
133 
134 #define _PAGE_ATTRIB_MASK       0xf
135 
136 #define _PAGE_HW_EXEC           (1<<0)  /* hardware: page is executable */
137 #define _PAGE_HW_WRITE          (1<<1)  /* hardware: page is writable */
138 
139 #define _PAGE_CA_BYPASS         (0<<2)  /* bypass, non-speculative */
140 #define _PAGE_CA_WB             (1<<2)  /* write-back */
141 #define _PAGE_CA_WT             (2<<2)  /* write-through */
142 #define _PAGE_CA_MASK           (3<<2)
143 #define _PAGE_CA_INVALID        (3<<2)
144 
145 /* We use invalid attribute values to distinguish special pte entries */
146 #if XCHAL_HW_VERSION_MAJOR < 2000
147 #define _PAGE_HW_VALID          0x01    /* older HW needed this bit set */
148 #define _PAGE_NONE              0x04
149 #else
150 #define _PAGE_HW_VALID          0x00
151 #define _PAGE_NONE              0x0f
152 #endif
153 
154 #define _PAGE_USER              (1<<4)  /* user access (ring=1) */
155 
156 /* Software */
157 #define _PAGE_WRITABLE_BIT      6
158 #define _PAGE_WRITABLE          (1<<6)  /* software: page writable */
159 #define _PAGE_DIRTY             (1<<7)  /* software: page dirty */
160 #define _PAGE_ACCESSED          (1<<8)  /* software: page accessed (read) */
161 
162 /* We borrow bit 1 to store the exclusive marker in swap PTEs. */
163 #define _PAGE_SWP_EXCLUSIVE     (1<<1)
164 
165 #ifdef CONFIG_MMU
166 
167 #define _PAGE_CHG_MASK     (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
168 #define _PAGE_PRESENT      (_PAGE_HW_VALID | _PAGE_CA_WB | _PAGE_ACCESSED)
169 
170 #define PAGE_NONE          __pgprot(_PAGE_NONE | _PAGE_USER)
171 #define PAGE_COPY          __pgprot(_PAGE_PRESENT | _PAGE_USER)
172 #define PAGE_COPY_EXEC     __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
173 #define PAGE_READONLY      __pgprot(_PAGE_PRESENT | _PAGE_USER)
174 #define PAGE_READONLY_EXEC __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_HW_EXEC)
175 #define PAGE_SHARED        __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE)
176 #define PAGE_SHARED_EXEC \
177         __pgprot(_PAGE_PRESENT | _PAGE_USER | _PAGE_WRITABLE | _PAGE_HW_EXEC)
178 #define PAGE_KERNEL        __pgprot(_PAGE_PRESENT | _PAGE_HW_WRITE)
179 #define PAGE_KERNEL_RO     __pgprot(_PAGE_PRESENT)
180 #define PAGE_KERNEL_EXEC   __pgprot(_PAGE_PRESENT|_PAGE_HW_WRITE|_PAGE_HW_EXEC)
181 
182 #if (DCACHE_WAY_SIZE > PAGE_SIZE)
183 # define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_BYPASS)
184 #else
185 # define _PAGE_DIRECTORY   (_PAGE_HW_VALID | _PAGE_ACCESSED | _PAGE_CA_WB)
186 #endif
187 
188 #else /* no mmu */
189 
190 # define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
191 # define PAGE_NONE       __pgprot(0)
192 # define PAGE_SHARED     __pgprot(0)
193 # define PAGE_COPY       __pgprot(0)
194 # define PAGE_READONLY   __pgprot(0)
195 # define PAGE_KERNEL     __pgprot(0)
196 
197 #endif
198 
199 /*
200  * On certain configurations of Xtensa MMUs (eg. the initial Linux config),
201  * the MMU can't do page protection for execute, and considers that the same as
202  * read.  Also, write permissions may imply read permissions.
203  * What follows is the closest we can get by reasonable means..
204  * See linux/mm/mmap.c for protection_map[] array that uses these definitions.
205  */
206 #ifndef __ASSEMBLY__
207 
208 #define pte_ERROR(e) \
209         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
210 #define pgd_ERROR(e) \
211         printk("%s:%d: bad pgd entry %08lx.\n", __FILE__, __LINE__, pgd_val(e))
212 
213 extern unsigned long empty_zero_page[1024];
214 
215 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
216 
217 #ifdef CONFIG_MMU
218 extern pgd_t swapper_pg_dir[PAGE_SIZE/sizeof(pgd_t)];
219 extern void paging_init(void);
220 #else
221 # define swapper_pg_dir NULL
222 static inline void paging_init(void) { }
223 #endif
224 
225 /*
226  * The pmd contains the kernel virtual address of the pte page.
227  */
228 #define pmd_page_vaddr(pmd) ((unsigned long)(pmd_val(pmd) & PAGE_MASK))
229 #define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
230 #define pmd_page(pmd) virt_to_page(pmd_val(pmd))
231 
232 /*
233  * pte status.
234  */
235 # define pte_none(pte)   (pte_val(pte) == (_PAGE_CA_INVALID | _PAGE_USER))
236 #if XCHAL_HW_VERSION_MAJOR < 2000
237 # define pte_present(pte) ((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)
238 #else
239 # define pte_present(pte)                                               \
240         (((pte_val(pte) & _PAGE_CA_MASK) != _PAGE_CA_INVALID)           \
241          || ((pte_val(pte) & _PAGE_ATTRIB_MASK) == _PAGE_NONE))
242 #endif
243 #define pte_clear(mm,addr,ptep)                                         \
244         do { update_pte(ptep, __pte(_PAGE_CA_INVALID | _PAGE_USER)); } while (0)
245 
246 #define pmd_none(pmd)    (!pmd_val(pmd))
247 #define pmd_present(pmd) (pmd_val(pmd) & PAGE_MASK)
248 #define pmd_bad(pmd)     (pmd_val(pmd) & ~PAGE_MASK)
249 #define pmd_clear(pmdp)  do { set_pmd(pmdp, __pmd(0)); } while (0)
250 
251 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITABLE; }
252 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
253 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
254 
255 static inline pte_t pte_wrprotect(pte_t pte)
256         { pte_val(pte) &= ~(_PAGE_WRITABLE | _PAGE_HW_WRITE); return pte; }
257 static inline pte_t pte_mkclean(pte_t pte)
258         { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HW_WRITE); return pte; }
259 static inline pte_t pte_mkold(pte_t pte)
260         { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
261 static inline pte_t pte_mkdirty(pte_t pte)
262         { pte_val(pte) |= _PAGE_DIRTY; return pte; }
263 static inline pte_t pte_mkyoung(pte_t pte)
264         { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
265 static inline pte_t pte_mkwrite_novma(pte_t pte)
266         { pte_val(pte) |= _PAGE_WRITABLE; return pte; }
267 
268 #define pgprot_noncached(prot) \
269                 ((__pgprot((pgprot_val(prot) & ~_PAGE_CA_MASK) | \
270                            _PAGE_CA_BYPASS)))
271 
272 /*
273  * Conversion functions: convert a page and protection to a page entry,
274  * and a page entry and page directory to the page they refer to.
275  */
276 
277 #define PFN_PTE_SHIFT           PAGE_SHIFT
278 #define pte_pfn(pte)            (pte_val(pte) >> PAGE_SHIFT)
279 #define pte_same(a,b)           (pte_val(a) == pte_val(b))
280 #define pte_page(x)             pfn_to_page(pte_pfn(x))
281 #define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
282 #define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
283 
284 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
285 {
286         return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
287 }
288 
289 /*
290  * Certain architectures need to do special things when pte's
291  * within a page table are directly modified.  Thus, the following
292  * hook is made available.
293  */
294 static inline void update_pte(pte_t *ptep, pte_t pteval)
295 {
296         *ptep = pteval;
297 #if (DCACHE_WAY_SIZE > PAGE_SIZE) && XCHAL_DCACHE_IS_WRITEBACK
298         __asm__ __volatile__ ("dhwb %0, 0" :: "a" (ptep));
299 #endif
300 
301 }
302 
303 struct mm_struct;
304 
305 static inline void set_pte(pte_t *ptep, pte_t pte)
306 {
307         update_pte(ptep, pte);
308 }
309 
310 static inline void
311 set_pmd(pmd_t *pmdp, pmd_t pmdval)
312 {
313         *pmdp = pmdval;
314 }
315 
316 struct vm_area_struct;
317 
318 static inline int
319 ptep_test_and_clear_young(struct vm_area_struct *vma, unsigned long addr,
320                           pte_t *ptep)
321 {
322         pte_t pte = *ptep;
323         if (!pte_young(pte))
324                 return 0;
325         update_pte(ptep, pte_mkold(pte));
326         return 1;
327 }
328 
329 static inline pte_t
330 ptep_get_and_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
331 {
332         pte_t pte = *ptep;
333         pte_clear(mm, addr, ptep);
334         return pte;
335 }
336 
337 static inline void
338 ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
339 {
340         pte_t pte = *ptep;
341         update_pte(ptep, pte_wrprotect(pte));
342 }
343 
344 /*
345  * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
346  * are !pte_none() && !pte_present().
347  */
348 #define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > 5)
349 
350 #define __swp_type(entry)       (((entry).val >> 6) & 0x1f)
351 #define __swp_offset(entry)     ((entry).val >> 11)
352 #define __swp_entry(type,offs)  \
353         ((swp_entry_t){(((type) & 0x1f) << 6) | ((offs) << 11) | \
354          _PAGE_CA_INVALID | _PAGE_USER})
355 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
356 #define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
357 
358 static inline int pte_swp_exclusive(pte_t pte)
359 {
360         return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
361 }
362 
363 static inline pte_t pte_swp_mkexclusive(pte_t pte)
364 {
365         pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
366         return pte;
367 }
368 
369 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
370 {
371         pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
372         return pte;
373 }
374 
375 #endif /*  !defined (__ASSEMBLY__) */
376 
377 
378 #ifdef __ASSEMBLY__
379 
380 /* Assembly macro _PGD_INDEX is the same as C pgd_index(unsigned long),
381  *                _PGD_OFFSET as C pgd_offset(struct mm_struct*, unsigned long),
382  *                _PMD_OFFSET as C pmd_offset(pgd_t*, unsigned long)
383  *                _PTE_OFFSET as C pte_offset(pmd_t*, unsigned long)
384  *
385  * Note: We require an additional temporary register which can be the same as
386  *       the register that holds the address.
387  *
388  * ((pte_t*) ((unsigned long)(pmd_val(*pmd) & PAGE_MASK)) + pte_index(addr))
389  *
390  */
391 #define _PGD_INDEX(rt,rs)       extui   rt, rs, PGDIR_SHIFT, 32-PGDIR_SHIFT
392 #define _PTE_INDEX(rt,rs)       extui   rt, rs, PAGE_SHIFT, PTRS_PER_PTE_SHIFT
393 
394 #define _PGD_OFFSET(mm,adr,tmp)         l32i    mm, mm, MM_PGD;         \
395                                         _PGD_INDEX(tmp, adr);           \
396                                         addx4   mm, tmp, mm
397 
398 #define _PTE_OFFSET(pmd,adr,tmp)        _PTE_INDEX(tmp, adr);           \
399                                         srli    pmd, pmd, PAGE_SHIFT;   \
400                                         slli    pmd, pmd, PAGE_SHIFT;   \
401                                         addx4   pmd, tmp, pmd
402 
403 #else
404 
405 struct vm_fault;
406 void update_mmu_cache_range(struct vm_fault *vmf, struct vm_area_struct *vma,
407                 unsigned long address, pte_t *ptep, unsigned int nr);
408 #define update_mmu_cache(vma, address, ptep) \
409         update_mmu_cache_range(NULL, vma, address, ptep, 1)
410 
411 typedef pte_t *pte_addr_t;
412 
413 void update_mmu_tlb_range(struct vm_area_struct *vma,
414                 unsigned long address, pte_t *ptep, unsigned int nr);
415 #define update_mmu_tlb_range update_mmu_tlb_range
416 
417 #endif /* !defined (__ASSEMBLY__) */
418 
419 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
420 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
421 #define __HAVE_ARCH_PTEP_SET_WRPROTECT
422 #define __HAVE_ARCH_PTEP_MKDIRTY
423 #define __HAVE_ARCH_PTE_SAME
424 /* We provide our own get_unmapped_area to cope with
425  * SHM area cache aliasing for userland.
426  */
427 #define HAVE_ARCH_UNMAPPED_AREA
428 
429 #endif /* _XTENSA_PGTABLE_H */
430 

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