1 /* 2 * This header file contains assembly-language definitions (assembly 3 * macros, etc.) for this specific Xtensa processor's TIE extensions 4 * and options. It is customized to this Xtensa processor configuration. 5 * 6 * This file is subject to the terms and conditions of the GNU General Public 7 * License. See the file "COPYING" in the main directory of this archive 8 * for more details. 9 * 10 * Copyright (C) 1999-2008 Tensilica Inc. 11 */ 12 13 #ifndef _XTENSA_CORE_TIE_ASM_H 14 #define _XTENSA_CORE_TIE_ASM_H 15 16 /* Selection parameter values for save-area save/restore macros: */ 17 /* Option vs. TIE: */ 18 #define XTHAL_SAS_TIE 0x0001 /* custom extension or coprocessor */ 19 #define XTHAL_SAS_OPT 0x0002 /* optional (and not a coprocessor) */ 20 /* Whether used automatically by compiler: */ 21 #define XTHAL_SAS_NOCC 0x0004 /* not used by compiler w/o special opts/code */ 22 #define XTHAL_SAS_CC 0x0008 /* used by compiler without special opts/code */ 23 /* ABI handling across function calls: */ 24 #define XTHAL_SAS_CALR 0x0010 /* caller-saved */ 25 #define XTHAL_SAS_CALE 0x0020 /* callee-saved */ 26 #define XTHAL_SAS_GLOB 0x0040 /* global across function calls (in thread) */ 27 /* Misc */ 28 #define XTHAL_SAS_ALL 0xFFFF /* include all default NCP contents */ 29 30 31 32 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 33 * (not including zero-overhead loop registers). 34 * Save area ptr (clobbered): ptr (1 byte aligned) 35 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 36 */ 37 .macro xchal_ncp_store ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 38 xchal_sa_start \continue, \ofs 39 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 40 xchal_sa_align \ptr, 0, 1024-4, 4, 4 41 rur \at1, THREADPTR // threadptr option 42 s32i \at1, \ptr, .Lxchal_ofs_ + 0 43 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 44 .endif 45 .endm // xchal_ncp_store 46 47 /* Macro to save all non-coprocessor (extra) custom TIE and optional state 48 * (not including zero-overhead loop registers). 49 * Save area ptr (clobbered): ptr (1 byte aligned) 50 * Scratch regs (clobbered): at1..at4 (only first XCHAL_NCP_NUM_ATMPS needed) 51 */ 52 .macro xchal_ncp_load ptr at1 at2 at3 at4 continue=0 ofs=-1 select=XTHAL_SAS_ALL 53 xchal_sa_start \continue, \ofs 54 .ifeq (XTHAL_SAS_OPT | XTHAL_SAS_CC | XTHAL_SAS_GLOB) & ~\select 55 xchal_sa_align \ptr, 0, 1024-4, 4, 4 56 l32i \at1, \ptr, .Lxchal_ofs_ + 0 57 wur \at1, THREADPTR // threadptr option 58 .set .Lxchal_ofs_, .Lxchal_ofs_ + 4 59 .endif 60 .endm // xchal_ncp_load 61 62 63 64 #define XCHAL_NCP_NUM_ATMPS 1 65 66 67 #define XCHAL_SA_NUM_ATMPS 1 68 69 #endif /*_XTENSA_CORE_TIE_ASM_H*/ 70 71
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