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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/bcm-ns2.h

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  1 /*
  2  *  BSD LICENSE
  3  *
  4  *  Copyright(c) 2015 Broadcom Corporation.  All rights reserved.
  5  *
  6  *  Redistribution and use in source and binary forms, with or without
  7  *  modification, are permitted provided that the following conditions
  8  *  are met:
  9  *
 10  *    * Redistributions of source code must retain the above copyright
 11  *      notice, this list of conditions and the following disclaimer.
 12  *    * Redistributions in binary form must reproduce the above copyright
 13  *      notice, this list of conditions and the following disclaimer in
 14  *      the documentation and/or other materials provided with the
 15  *      distribution.
 16  *    * Neither the name of Broadcom Corporation nor the names of its
 17  *      contributors may be used to endorse or promote products derived
 18  *      from this software without specific prior written permission.
 19  *
 20  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 21  *  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 22  *  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 23  *  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 24  *  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
 25  *  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 26  *  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 27  *  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 28  *  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 29  *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 30  *  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 31  */
 32 
 33 #ifndef _CLOCK_BCM_NS2_H
 34 #define _CLOCK_BCM_NS2_H
 35 
 36 /* GENPLL SCR clock channel ID */
 37 #define BCM_NS2_GENPLL_SCR              0
 38 #define BCM_NS2_GENPLL_SCR_SCR_CLK      1
 39 #define BCM_NS2_GENPLL_SCR_FS_CLK       2
 40 #define BCM_NS2_GENPLL_SCR_AUDIO_CLK    3
 41 #define BCM_NS2_GENPLL_SCR_CH3_UNUSED   4
 42 #define BCM_NS2_GENPLL_SCR_CH4_UNUSED   5
 43 #define BCM_NS2_GENPLL_SCR_CH5_UNUSED   6
 44 
 45 /* GENPLL SW clock channel ID */
 46 #define BCM_NS2_GENPLL_SW               0
 47 #define BCM_NS2_GENPLL_SW_RPE_CLK       1
 48 #define BCM_NS2_GENPLL_SW_250_CLK       2
 49 #define BCM_NS2_GENPLL_SW_NIC_CLK       3
 50 #define BCM_NS2_GENPLL_SW_CHIMP_CLK     4
 51 #define BCM_NS2_GENPLL_SW_PORT_CLK      5
 52 #define BCM_NS2_GENPLL_SW_SDIO_CLK      6
 53 
 54 /* LCPLL DDR clock channel ID */
 55 #define BCM_NS2_LCPLL_DDR               0
 56 #define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK     1
 57 #define BCM_NS2_LCPLL_DDR_DDR_CLK       2
 58 #define BCM_NS2_LCPLL_DDR_CH2_UNUSED    3
 59 #define BCM_NS2_LCPLL_DDR_CH3_UNUSED    4
 60 #define BCM_NS2_LCPLL_DDR_CH4_UNUSED    5
 61 #define BCM_NS2_LCPLL_DDR_CH5_UNUSED    6
 62 
 63 /* LCPLL PORTS clock channel ID */
 64 #define BCM_NS2_LCPLL_PORTS             0
 65 #define BCM_NS2_LCPLL_PORTS_WAN_CLK     1
 66 #define BCM_NS2_LCPLL_PORTS_RGMII_CLK   2
 67 #define BCM_NS2_LCPLL_PORTS_CH2_UNUSED  3
 68 #define BCM_NS2_LCPLL_PORTS_CH3_UNUSED  4
 69 #define BCM_NS2_LCPLL_PORTS_CH4_UNUSED  5
 70 #define BCM_NS2_LCPLL_PORTS_CH5_UNUSED  6
 71 
 72 #endif /* _CLOCK_BCM_NS2_H */
 73 

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