1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright 2018 NXP 4 * Dong Aisheng <aisheng.dong@nxp.com> 5 */ 6 7 #ifndef __DT_BINDINGS_CLOCK_IMX_H 8 #define __DT_BINDINGS_CLOCK_IMX_H 9 10 /* LPCG clocks */ 11 12 /* LSIO SS LPCG */ 13 #define IMX_LSIO_LPCG_PWM0_IPG_CLK 0 14 #define IMX_LSIO_LPCG_PWM0_IPG_S_CLK 1 15 #define IMX_LSIO_LPCG_PWM0_IPG_HF_CLK 2 16 #define IMX_LSIO_LPCG_PWM0_IPG_SLV_CLK 3 17 #define IMX_LSIO_LPCG_PWM0_IPG_MSTR_CLK 4 18 #define IMX_LSIO_LPCG_PWM1_IPG_CLK 5 19 #define IMX_LSIO_LPCG_PWM1_IPG_S_CLK 6 20 #define IMX_LSIO_LPCG_PWM1_IPG_HF_CLK 7 21 #define IMX_LSIO_LPCG_PWM1_IPG_SLV_CLK 8 22 #define IMX_LSIO_LPCG_PWM1_IPG_MSTR_CLK 9 23 #define IMX_LSIO_LPCG_PWM2_IPG_CLK 10 24 #define IMX_LSIO_LPCG_PWM2_IPG_S_CLK 11 25 #define IMX_LSIO_LPCG_PWM2_IPG_HF_CLK 12 26 #define IMX_LSIO_LPCG_PWM2_IPG_SLV_CLK 13 27 #define IMX_LSIO_LPCG_PWM2_IPG_MSTR_CLK 14 28 #define IMX_LSIO_LPCG_PWM3_IPG_CLK 15 29 #define IMX_LSIO_LPCG_PWM3_IPG_S_CLK 16 30 #define IMX_LSIO_LPCG_PWM3_IPG_HF_CLK 17 31 #define IMX_LSIO_LPCG_PWM3_IPG_SLV_CLK 18 32 #define IMX_LSIO_LPCG_PWM3_IPG_MSTR_CLK 19 33 #define IMX_LSIO_LPCG_PWM4_IPG_CLK 20 34 #define IMX_LSIO_LPCG_PWM4_IPG_S_CLK 21 35 #define IMX_LSIO_LPCG_PWM4_IPG_HF_CLK 22 36 #define IMX_LSIO_LPCG_PWM4_IPG_SLV_CLK 23 37 #define IMX_LSIO_LPCG_PWM4_IPG_MSTR_CLK 24 38 #define IMX_LSIO_LPCG_PWM5_IPG_CLK 25 39 #define IMX_LSIO_LPCG_PWM5_IPG_S_CLK 26 40 #define IMX_LSIO_LPCG_PWM5_IPG_HF_CLK 27 41 #define IMX_LSIO_LPCG_PWM5_IPG_SLV_CLK 28 42 #define IMX_LSIO_LPCG_PWM5_IPG_MSTR_CLK 29 43 #define IMX_LSIO_LPCG_PWM6_IPG_CLK 30 44 #define IMX_LSIO_LPCG_PWM6_IPG_S_CLK 31 45 #define IMX_LSIO_LPCG_PWM6_IPG_HF_CLK 32 46 #define IMX_LSIO_LPCG_PWM6_IPG_SLV_CLK 33 47 #define IMX_LSIO_LPCG_PWM6_IPG_MSTR_CLK 34 48 #define IMX_LSIO_LPCG_PWM7_IPG_CLK 35 49 #define IMX_LSIO_LPCG_PWM7_IPG_S_CLK 36 50 #define IMX_LSIO_LPCG_PWM7_IPG_HF_CLK 37 51 #define IMX_LSIO_LPCG_PWM7_IPG_SLV_CLK 38 52 #define IMX_LSIO_LPCG_PWM7_IPG_MSTR_CLK 39 53 #define IMX_LSIO_LPCG_GPT0_IPG_CLK 40 54 #define IMX_LSIO_LPCG_GPT0_IPG_S_CLK 41 55 #define IMX_LSIO_LPCG_GPT0_IPG_HF_CLK 42 56 #define IMX_LSIO_LPCG_GPT0_IPG_SLV_CLK 43 57 #define IMX_LSIO_LPCG_GPT0_IPG_MSTR_CLK 44 58 #define IMX_LSIO_LPCG_GPT1_IPG_CLK 45 59 #define IMX_LSIO_LPCG_GPT1_IPG_S_CLK 46 60 #define IMX_LSIO_LPCG_GPT1_IPG_HF_CLK 47 61 #define IMX_LSIO_LPCG_GPT1_IPG_SLV_CLK 48 62 #define IMX_LSIO_LPCG_GPT1_IPG_MSTR_CLK 49 63 #define IMX_LSIO_LPCG_GPT2_IPG_CLK 50 64 #define IMX_LSIO_LPCG_GPT2_IPG_S_CLK 51 65 #define IMX_LSIO_LPCG_GPT2_IPG_HF_CLK 52 66 #define IMX_LSIO_LPCG_GPT2_IPG_SLV_CLK 53 67 #define IMX_LSIO_LPCG_GPT2_IPG_MSTR_CLK 54 68 #define IMX_LSIO_LPCG_GPT3_IPG_CLK 55 69 #define IMX_LSIO_LPCG_GPT3_IPG_S_CLK 56 70 #define IMX_LSIO_LPCG_GPT3_IPG_HF_CLK 57 71 #define IMX_LSIO_LPCG_GPT3_IPG_SLV_CLK 58 72 #define IMX_LSIO_LPCG_GPT3_IPG_MSTR_CLK 59 73 #define IMX_LSIO_LPCG_GPT4_IPG_CLK 60 74 #define IMX_LSIO_LPCG_GPT4_IPG_S_CLK 61 75 #define IMX_LSIO_LPCG_GPT4_IPG_HF_CLK 62 76 #define IMX_LSIO_LPCG_GPT4_IPG_SLV_CLK 63 77 #define IMX_LSIO_LPCG_GPT4_IPG_MSTR_CLK 64 78 #define IMX_LSIO_LPCG_FSPI0_HCLK 65 79 #define IMX_LSIO_LPCG_FSPI0_IPG_CLK 66 80 #define IMX_LSIO_LPCG_FSPI0_IPG_S_CLK 67 81 #define IMX_LSIO_LPCG_FSPI0_IPG_SFCK 68 82 #define IMX_LSIO_LPCG_FSPI1_HCLK 69 83 #define IMX_LSIO_LPCG_FSPI1_IPG_CLK 70 84 #define IMX_LSIO_LPCG_FSPI1_IPG_S_CLK 71 85 #define IMX_LSIO_LPCG_FSPI1_IPG_SFCK 72 86 87 #define IMX_LSIO_LPCG_CLK_END 73 88 89 /* Connectivity SS LPCG */ 90 #define IMX_CONN_LPCG_SDHC0_IPG_CLK 0 91 #define IMX_CONN_LPCG_SDHC0_PER_CLK 1 92 #define IMX_CONN_LPCG_SDHC0_HCLK 2 93 #define IMX_CONN_LPCG_SDHC1_IPG_CLK 3 94 #define IMX_CONN_LPCG_SDHC1_PER_CLK 4 95 #define IMX_CONN_LPCG_SDHC1_HCLK 5 96 #define IMX_CONN_LPCG_SDHC2_IPG_CLK 6 97 #define IMX_CONN_LPCG_SDHC2_PER_CLK 7 98 #define IMX_CONN_LPCG_SDHC2_HCLK 8 99 #define IMX_CONN_LPCG_GPMI_APB_CLK 9 100 #define IMX_CONN_LPCG_GPMI_BCH_APB_CLK 10 101 #define IMX_CONN_LPCG_GPMI_BCH_IO_CLK 11 102 #define IMX_CONN_LPCG_GPMI_BCH_CLK 12 103 #define IMX_CONN_LPCG_APBHDMA_CLK 13 104 #define IMX_CONN_LPCG_ENET0_ROOT_CLK 14 105 #define IMX_CONN_LPCG_ENET0_TX_CLK 15 106 #define IMX_CONN_LPCG_ENET0_AHB_CLK 16 107 #define IMX_CONN_LPCG_ENET0_IPG_S_CLK 17 108 #define IMX_CONN_LPCG_ENET0_IPG_CLK 18 109 110 #define IMX_CONN_LPCG_ENET1_ROOT_CLK 19 111 #define IMX_CONN_LPCG_ENET1_TX_CLK 20 112 #define IMX_CONN_LPCG_ENET1_AHB_CLK 21 113 #define IMX_CONN_LPCG_ENET1_IPG_S_CLK 22 114 #define IMX_CONN_LPCG_ENET1_IPG_CLK 23 115 116 #define IMX_CONN_LPCG_CLK_END 24 117 118 /* ADMA SS LPCG */ 119 #define IMX_ADMA_LPCG_UART0_IPG_CLK 0 120 #define IMX_ADMA_LPCG_UART0_BAUD_CLK 1 121 #define IMX_ADMA_LPCG_UART1_IPG_CLK 2 122 #define IMX_ADMA_LPCG_UART1_BAUD_CLK 3 123 #define IMX_ADMA_LPCG_UART2_IPG_CLK 4 124 #define IMX_ADMA_LPCG_UART2_BAUD_CLK 5 125 #define IMX_ADMA_LPCG_UART3_IPG_CLK 6 126 #define IMX_ADMA_LPCG_UART3_BAUD_CLK 7 127 #define IMX_ADMA_LPCG_SPI0_IPG_CLK 8 128 #define IMX_ADMA_LPCG_SPI1_IPG_CLK 9 129 #define IMX_ADMA_LPCG_SPI2_IPG_CLK 10 130 #define IMX_ADMA_LPCG_SPI3_IPG_CLK 11 131 #define IMX_ADMA_LPCG_SPI0_CLK 12 132 #define IMX_ADMA_LPCG_SPI1_CLK 13 133 #define IMX_ADMA_LPCG_SPI2_CLK 14 134 #define IMX_ADMA_LPCG_SPI3_CLK 15 135 #define IMX_ADMA_LPCG_CAN0_IPG_CLK 16 136 #define IMX_ADMA_LPCG_CAN0_IPG_PE_CLK 17 137 #define IMX_ADMA_LPCG_CAN0_IPG_CHI_CLK 18 138 #define IMX_ADMA_LPCG_CAN1_IPG_CLK 19 139 #define IMX_ADMA_LPCG_CAN1_IPG_PE_CLK 20 140 #define IMX_ADMA_LPCG_CAN1_IPG_CHI_CLK 21 141 #define IMX_ADMA_LPCG_CAN2_IPG_CLK 22 142 #define IMX_ADMA_LPCG_CAN2_IPG_PE_CLK 23 143 #define IMX_ADMA_LPCG_CAN2_IPG_CHI_CLK 24 144 #define IMX_ADMA_LPCG_I2C0_CLK 25 145 #define IMX_ADMA_LPCG_I2C1_CLK 26 146 #define IMX_ADMA_LPCG_I2C2_CLK 27 147 #define IMX_ADMA_LPCG_I2C3_CLK 28 148 #define IMX_ADMA_LPCG_I2C0_IPG_CLK 29 149 #define IMX_ADMA_LPCG_I2C1_IPG_CLK 30 150 #define IMX_ADMA_LPCG_I2C2_IPG_CLK 31 151 #define IMX_ADMA_LPCG_I2C3_IPG_CLK 32 152 #define IMX_ADMA_LPCG_FTM0_CLK 33 153 #define IMX_ADMA_LPCG_FTM1_CLK 34 154 #define IMX_ADMA_LPCG_FTM0_IPG_CLK 35 155 #define IMX_ADMA_LPCG_FTM1_IPG_CLK 36 156 #define IMX_ADMA_LPCG_PWM_HI_CLK 37 157 #define IMX_ADMA_LPCG_PWM_IPG_CLK 38 158 #define IMX_ADMA_LPCG_LCD_PIX_CLK 39 159 #define IMX_ADMA_LPCG_LCD_APB_CLK 40 160 #define IMX_ADMA_LPCG_DSP_ADB_CLK 41 161 #define IMX_ADMA_LPCG_DSP_IPG_CLK 42 162 #define IMX_ADMA_LPCG_DSP_CORE_CLK 43 163 #define IMX_ADMA_LPCG_OCRAM_IPG_CLK 44 164 165 #define IMX_ADMA_LPCG_CLK_END 45 166 167 #define IMX_ADMA_ACM_AUD_CLK0_SEL 0 168 #define IMX_ADMA_ACM_AUD_CLK1_SEL 1 169 #define IMX_ADMA_ACM_MCLKOUT0_SEL 2 170 #define IMX_ADMA_ACM_MCLKOUT1_SEL 3 171 #define IMX_ADMA_ACM_ESAI0_MCLK_SEL 4 172 #define IMX_ADMA_ACM_ESAI1_MCLK_SEL 5 173 #define IMX_ADMA_ACM_GPT0_MUX_CLK_SEL 6 174 #define IMX_ADMA_ACM_GPT1_MUX_CLK_SEL 7 175 #define IMX_ADMA_ACM_GPT2_MUX_CLK_SEL 8 176 #define IMX_ADMA_ACM_GPT3_MUX_CLK_SEL 9 177 #define IMX_ADMA_ACM_GPT4_MUX_CLK_SEL 10 178 #define IMX_ADMA_ACM_GPT5_MUX_CLK_SEL 11 179 #define IMX_ADMA_ACM_SAI0_MCLK_SEL 12 180 #define IMX_ADMA_ACM_SAI1_MCLK_SEL 13 181 #define IMX_ADMA_ACM_SAI2_MCLK_SEL 14 182 #define IMX_ADMA_ACM_SAI3_MCLK_SEL 15 183 #define IMX_ADMA_ACM_SAI4_MCLK_SEL 16 184 #define IMX_ADMA_ACM_SAI5_MCLK_SEL 17 185 #define IMX_ADMA_ACM_SAI6_MCLK_SEL 18 186 #define IMX_ADMA_ACM_SAI7_MCLK_SEL 19 187 #define IMX_ADMA_ACM_SPDIF0_TX_CLK_SEL 20 188 #define IMX_ADMA_ACM_SPDIF1_TX_CLK_SEL 21 189 #define IMX_ADMA_ACM_MQS_TX_CLK_SEL 22 190 #define IMX_ADMA_ACM_ASRC0_MUX_CLK_SEL 23 191 #define IMX_ADMA_ACM_ASRC1_MUX_CLK_SEL 24 192 193 #define IMX_ADMA_ACM_CLK_END 25 194 195 #endif /* __DT_BINDINGS_CLOCK_IMX_H */ 196
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