1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Author: Yinbo Zhu <zhuyinbo@loongson.cn> 4 * Copyright (C) 2022-2023 Loongson Technology Corporation Limited 5 */ 6 7 #ifndef __DT_BINDINGS_CLOCK_LOONGSON2_H 8 #define __DT_BINDINGS_CLOCK_LOONGSON2_H 9 10 #define LOONGSON2_REF_100M 0 11 #define LOONGSON2_NODE_PLL 1 12 #define LOONGSON2_DDR_PLL 2 13 #define LOONGSON2_DC_PLL 3 14 #define LOONGSON2_PIX0_PLL 4 15 #define LOONGSON2_PIX1_PLL 5 16 #define LOONGSON2_NODE_CLK 6 17 #define LOONGSON2_HDA_CLK 7 18 #define LOONGSON2_GPU_CLK 8 19 #define LOONGSON2_DDR_CLK 9 20 #define LOONGSON2_GMAC_CLK 10 21 #define LOONGSON2_DC_CLK 11 22 #define LOONGSON2_APB_CLK 12 23 #define LOONGSON2_USB_CLK 13 24 #define LOONGSON2_SATA_CLK 14 25 #define LOONGSON2_PIX0_CLK 15 26 #define LOONGSON2_PIX1_CLK 16 27 #define LOONGSON2_BOOT_CLK 17 28 #define LOONGSON2_OUT0_GATE 18 29 #define LOONGSON2_GMAC_GATE 19 30 #define LOONGSON2_RIO_GATE 20 31 #define LOONGSON2_DC_GATE 21 32 #define LOONGSON2_GPU_GATE 22 33 #define LOONGSON2_DDR_GATE 23 34 #define LOONGSON2_HDA_GATE 24 35 #define LOONGSON2_NODE_GATE 25 36 #define LOONGSON2_EMMC_GATE 26 37 #define LOONGSON2_PIX0_GATE 27 38 #define LOONGSON2_PIX1_GATE 28 39 #define LOONGSON2_OUT0_CLK 29 40 #define LOONGSON2_RIO_CLK 30 41 #define LOONGSON2_EMMC_CLK 31 42 #define LOONGSON2_DES_CLK 32 43 #define LOONGSON2_I2S_CLK 33 44 #define LOONGSON2_MISC_CLK 34 45 46 #endif 47
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