1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2021, Konrad Dybcio <konrad.dybcio@somainline.org> 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_MSM_GCC_9607_H 7 #define _DT_BINDINGS_CLK_MSM_GCC_9607_H 8 9 #define GPLL0 0 10 #define GPLL0_EARLY 1 11 #define GPLL1 2 12 #define GPLL1_VOTE 3 13 #define GPLL2 4 14 #define GPLL2_EARLY 5 15 #define PCNOC_BFDCD_CLK_SRC 6 16 #define SYSTEM_NOC_BFDCD_CLK_SRC 7 17 #define GCC_SMMU_CFG_CLK 8 18 #define APSS_AHB_CLK_SRC 9 19 #define GCC_QDSS_DAP_CLK 10 20 #define BLSP1_QUP1_I2C_APPS_CLK_SRC 11 21 #define BLSP1_QUP1_SPI_APPS_CLK_SRC 12 22 #define BLSP1_QUP2_I2C_APPS_CLK_SRC 13 23 #define BLSP1_QUP2_SPI_APPS_CLK_SRC 14 24 #define BLSP1_QUP3_I2C_APPS_CLK_SRC 15 25 #define BLSP1_QUP3_SPI_APPS_CLK_SRC 16 26 #define BLSP1_QUP4_I2C_APPS_CLK_SRC 17 27 #define BLSP1_QUP4_SPI_APPS_CLK_SRC 18 28 #define BLSP1_QUP5_I2C_APPS_CLK_SRC 19 29 #define BLSP1_QUP5_SPI_APPS_CLK_SRC 20 30 #define BLSP1_QUP6_I2C_APPS_CLK_SRC 21 31 #define BLSP1_QUP6_SPI_APPS_CLK_SRC 22 32 #define BLSP1_UART1_APPS_CLK_SRC 23 33 #define BLSP1_UART2_APPS_CLK_SRC 24 34 #define CRYPTO_CLK_SRC 25 35 #define GP1_CLK_SRC 26 36 #define GP2_CLK_SRC 27 37 #define GP3_CLK_SRC 28 38 #define PDM2_CLK_SRC 29 39 #define SDCC1_APPS_CLK_SRC 30 40 #define SDCC2_APPS_CLK_SRC 31 41 #define APSS_TCU_CLK_SRC 32 42 #define USB_HS_SYSTEM_CLK_SRC 33 43 #define GCC_BLSP1_AHB_CLK 34 44 #define GCC_BLSP1_SLEEP_CLK 35 45 #define GCC_BLSP1_QUP1_I2C_APPS_CLK 36 46 #define GCC_BLSP1_QUP1_SPI_APPS_CLK 37 47 #define GCC_BLSP1_QUP2_I2C_APPS_CLK 38 48 #define GCC_BLSP1_QUP2_SPI_APPS_CLK 39 49 #define GCC_BLSP1_QUP3_I2C_APPS_CLK 40 50 #define GCC_BLSP1_QUP3_SPI_APPS_CLK 41 51 #define GCC_BLSP1_QUP4_I2C_APPS_CLK 42 52 #define GCC_BLSP1_QUP4_SPI_APPS_CLK 43 53 #define GCC_BLSP1_QUP5_I2C_APPS_CLK 44 54 #define GCC_BLSP1_QUP5_SPI_APPS_CLK 45 55 #define GCC_BLSP1_QUP6_I2C_APPS_CLK 46 56 #define GCC_BLSP1_QUP6_SPI_APPS_CLK 47 57 #define GCC_BLSP1_UART1_APPS_CLK 48 58 #define GCC_BLSP1_UART2_APPS_CLK 49 59 #define GCC_BOOT_ROM_AHB_CLK 50 60 #define GCC_CRYPTO_AHB_CLK 51 61 #define GCC_CRYPTO_AXI_CLK 52 62 #define GCC_CRYPTO_CLK 53 63 #define GCC_GP1_CLK 54 64 #define GCC_GP2_CLK 55 65 #define GCC_GP3_CLK 56 66 #define GCC_MSS_CFG_AHB_CLK 57 67 #define GCC_PDM2_CLK 58 68 #define GCC_PDM_AHB_CLK 59 69 #define GCC_PRNG_AHB_CLK 60 70 #define GCC_SDCC1_AHB_CLK 61 71 #define GCC_SDCC1_APPS_CLK 62 72 #define GCC_SDCC2_AHB_CLK 63 73 #define GCC_SDCC2_APPS_CLK 64 74 #define GCC_USB2A_PHY_SLEEP_CLK 65 75 #define GCC_USB_HS_AHB_CLK 66 76 #define GCC_USB_HS_SYSTEM_CLK 67 77 #define GCC_APSS_TCU_CLK 68 78 #define GCC_MSS_Q6_BIMC_AXI_CLK 69 79 #define BIMC_PLL 70 80 #define BIMC_PLL_VOTE 71 81 #define BIMC_DDR_CLK_SRC 72 82 #define BLSP1_UART3_APPS_CLK_SRC 73 83 #define BLSP1_UART4_APPS_CLK_SRC 74 84 #define BLSP1_UART5_APPS_CLK_SRC 75 85 #define BLSP1_UART6_APPS_CLK_SRC 76 86 #define GCC_BLSP1_UART3_APPS_CLK 77 87 #define GCC_BLSP1_UART4_APPS_CLK 78 88 #define GCC_BLSP1_UART5_APPS_CLK 79 89 #define GCC_BLSP1_UART6_APPS_CLK 80 90 #define GCC_APSS_AHB_CLK 81 91 #define GCC_APSS_AXI_CLK 82 92 #define GCC_USB_HS_PHY_CFG_AHB_CLK 83 93 #define GCC_USB_HSIC_CLK_SRC 84 94 #define GCC_USB_HSIC_IO_CAL_CLK_SRC 85 95 #define GCC_USB_HSIC_SYSTEM_CLK_SRC 86 96 97 /* Resets */ 98 #define USB2_HS_PHY_ONLY_BCR 0 99 #define QUSB2_PHY_BCR 1 100 #define GCC_MSS_RESTART 2 101 #define USB_HS_HSIC_BCR 3 102 #define USB_HS_BCR 4 103 104 #endif 105
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