1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved. 4 * Copyright (c) 2020-2021, Linaro Limited 5 */ 6 7 #ifndef _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H 8 #define _DT_BINDINGS_CLK_QCOM_GCC_SM8350_H 9 10 /* GCC HW clocks */ 11 #define PCIE_0_PIPE_CLK 1 12 #define PCIE_1_PIPE_CLK 2 13 #define UFS_CARD_RX_SYMBOL_0_CLK 3 14 #define UFS_CARD_RX_SYMBOL_1_CLK 4 15 #define UFS_CARD_TX_SYMBOL_0_CLK 5 16 #define UFS_PHY_RX_SYMBOL_0_CLK 6 17 #define UFS_PHY_RX_SYMBOL_1_CLK 7 18 #define UFS_PHY_TX_SYMBOL_0_CLK 8 19 #define USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK 9 20 #define USB3_UNI_PHY_SEC_GCC_USB30_PIPE_CLK 10 21 22 /* GCC clocks */ 23 #define GCC_AGGRE_NOC_PCIE_0_AXI_CLK 11 24 #define GCC_AGGRE_NOC_PCIE_1_AXI_CLK 12 25 #define GCC_AGGRE_NOC_PCIE_TBU_CLK 13 26 #define GCC_AGGRE_UFS_CARD_AXI_CLK 14 27 #define GCC_AGGRE_UFS_CARD_AXI_HW_CTL_CLK 15 28 #define GCC_AGGRE_UFS_PHY_AXI_CLK 16 29 #define GCC_AGGRE_UFS_PHY_AXI_HW_CTL_CLK 17 30 #define GCC_AGGRE_USB3_PRIM_AXI_CLK 18 31 #define GCC_AGGRE_USB3_SEC_AXI_CLK 19 32 #define GCC_BOOT_ROM_AHB_CLK 20 33 #define GCC_CAMERA_HF_AXI_CLK 21 34 #define GCC_CAMERA_SF_AXI_CLK 22 35 #define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 23 36 #define GCC_CFG_NOC_USB3_SEC_AXI_CLK 24 37 #define GCC_DDRSS_GPU_AXI_CLK 25 38 #define GCC_DDRSS_PCIE_SF_TBU_CLK 26 39 #define GCC_DISP_HF_AXI_CLK 27 40 #define GCC_DISP_SF_AXI_CLK 28 41 #define GCC_GP1_CLK 29 42 #define GCC_GP1_CLK_SRC 30 43 #define GCC_GP2_CLK 31 44 #define GCC_GP2_CLK_SRC 32 45 #define GCC_GP3_CLK 33 46 #define GCC_GP3_CLK_SRC 34 47 #define GCC_GPLL0 35 48 #define GCC_GPLL0_OUT_EVEN 36 49 #define GCC_GPLL4 37 50 #define GCC_GPLL9 38 51 #define GCC_GPU_GPLL0_CLK_SRC 39 52 #define GCC_GPU_GPLL0_DIV_CLK_SRC 40 53 #define GCC_GPU_IREF_EN 41 54 #define GCC_GPU_MEMNOC_GFX_CLK 42 55 #define GCC_GPU_SNOC_DVM_GFX_CLK 43 56 #define GCC_PCIE0_PHY_RCHNG_CLK 44 57 #define GCC_PCIE1_PHY_RCHNG_CLK 45 58 #define GCC_PCIE_0_AUX_CLK 46 59 #define GCC_PCIE_0_AUX_CLK_SRC 47 60 #define GCC_PCIE_0_CFG_AHB_CLK 48 61 #define GCC_PCIE_0_CLKREF_EN 49 62 #define GCC_PCIE_0_MSTR_AXI_CLK 50 63 #define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 51 64 #define GCC_PCIE_0_PIPE_CLK 52 65 #define GCC_PCIE_0_PIPE_CLK_SRC 53 66 #define GCC_PCIE_0_SLV_AXI_CLK 54 67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 68 #define GCC_PCIE_1_AUX_CLK 56 69 #define GCC_PCIE_1_AUX_CLK_SRC 57 70 #define GCC_PCIE_1_CFG_AHB_CLK 58 71 #define GCC_PCIE_1_CLKREF_EN 59 72 #define GCC_PCIE_1_MSTR_AXI_CLK 60 73 #define GCC_PCIE_1_PHY_RCHNG_CLK_SRC 61 74 #define GCC_PCIE_1_PIPE_CLK 62 75 #define GCC_PCIE_1_PIPE_CLK_SRC 63 76 #define GCC_PCIE_1_SLV_AXI_CLK 64 77 #define GCC_PCIE_1_SLV_Q2A_AXI_CLK 65 78 #define GCC_PDM2_CLK 66 79 #define GCC_PDM2_CLK_SRC 67 80 #define GCC_PDM_AHB_CLK 68 81 #define GCC_PDM_XO4_CLK 69 82 #define GCC_QMIP_CAMERA_NRT_AHB_CLK 70 83 #define GCC_QMIP_CAMERA_RT_AHB_CLK 71 84 #define GCC_QMIP_DISP_AHB_CLK 72 85 #define GCC_QMIP_VIDEO_CVP_AHB_CLK 73 86 #define GCC_QMIP_VIDEO_VCODEC_AHB_CLK 74 87 #define GCC_QUPV3_WRAP0_CORE_2X_CLK 75 88 #define GCC_QUPV3_WRAP0_CORE_CLK 76 89 #define GCC_QUPV3_WRAP0_S0_CLK 77 90 #define GCC_QUPV3_WRAP0_S0_CLK_SRC 78 91 #define GCC_QUPV3_WRAP0_S1_CLK 79 92 #define GCC_QUPV3_WRAP0_S1_CLK_SRC 80 93 #define GCC_QUPV3_WRAP0_S2_CLK 81 94 #define GCC_QUPV3_WRAP0_S2_CLK_SRC 82 95 #define GCC_QUPV3_WRAP0_S3_CLK 83 96 #define GCC_QUPV3_WRAP0_S3_CLK_SRC 84 97 #define GCC_QUPV3_WRAP0_S4_CLK 85 98 #define GCC_QUPV3_WRAP0_S4_CLK_SRC 86 99 #define GCC_QUPV3_WRAP0_S5_CLK 87 100 #define GCC_QUPV3_WRAP0_S5_CLK_SRC 88 101 #define GCC_QUPV3_WRAP0_S6_CLK 89 102 #define GCC_QUPV3_WRAP0_S6_CLK_SRC 90 103 #define GCC_QUPV3_WRAP0_S7_CLK 91 104 #define GCC_QUPV3_WRAP0_S7_CLK_SRC 92 105 #define GCC_QUPV3_WRAP1_CORE_2X_CLK 93 106 #define GCC_QUPV3_WRAP1_CORE_CLK 94 107 #define GCC_QUPV3_WRAP1_S0_CLK 95 108 #define GCC_QUPV3_WRAP1_S0_CLK_SRC 96 109 #define GCC_QUPV3_WRAP1_S1_CLK 97 110 #define GCC_QUPV3_WRAP1_S1_CLK_SRC 98 111 #define GCC_QUPV3_WRAP1_S2_CLK 99 112 #define GCC_QUPV3_WRAP1_S2_CLK_SRC 100 113 #define GCC_QUPV3_WRAP1_S3_CLK 101 114 #define GCC_QUPV3_WRAP1_S3_CLK_SRC 102 115 #define GCC_QUPV3_WRAP1_S4_CLK 103 116 #define GCC_QUPV3_WRAP1_S4_CLK_SRC 104 117 #define GCC_QUPV3_WRAP1_S5_CLK 105 118 #define GCC_QUPV3_WRAP1_S5_CLK_SRC 106 119 #define GCC_QUPV3_WRAP2_CORE_2X_CLK 107 120 #define GCC_QUPV3_WRAP2_CORE_CLK 108 121 #define GCC_QUPV3_WRAP2_S0_CLK 109 122 #define GCC_QUPV3_WRAP2_S0_CLK_SRC 110 123 #define GCC_QUPV3_WRAP2_S1_CLK 111 124 #define GCC_QUPV3_WRAP2_S1_CLK_SRC 112 125 #define GCC_QUPV3_WRAP2_S2_CLK 113 126 #define GCC_QUPV3_WRAP2_S2_CLK_SRC 114 127 #define GCC_QUPV3_WRAP2_S3_CLK 115 128 #define GCC_QUPV3_WRAP2_S3_CLK_SRC 116 129 #define GCC_QUPV3_WRAP2_S4_CLK 117 130 #define GCC_QUPV3_WRAP2_S4_CLK_SRC 118 131 #define GCC_QUPV3_WRAP2_S5_CLK 119 132 #define GCC_QUPV3_WRAP2_S5_CLK_SRC 120 133 #define GCC_QUPV3_WRAP_0_M_AHB_CLK 121 134 #define GCC_QUPV3_WRAP_0_S_AHB_CLK 122 135 #define GCC_QUPV3_WRAP_1_M_AHB_CLK 123 136 #define GCC_QUPV3_WRAP_1_S_AHB_CLK 124 137 #define GCC_QUPV3_WRAP_2_M_AHB_CLK 125 138 #define GCC_QUPV3_WRAP_2_S_AHB_CLK 126 139 #define GCC_SDCC2_AHB_CLK 127 140 #define GCC_SDCC2_APPS_CLK 128 141 #define GCC_SDCC2_APPS_CLK_SRC 129 142 #define GCC_SDCC4_AHB_CLK 130 143 #define GCC_SDCC4_APPS_CLK 131 144 #define GCC_SDCC4_APPS_CLK_SRC 132 145 #define GCC_THROTTLE_PCIE_AHB_CLK 133 146 #define GCC_UFS_1_CLKREF_EN 134 147 #define GCC_UFS_CARD_AHB_CLK 135 148 #define GCC_UFS_CARD_AXI_CLK 136 149 #define GCC_UFS_CARD_AXI_CLK_SRC 137 150 #define GCC_UFS_CARD_AXI_HW_CTL_CLK 138 151 #define GCC_UFS_CARD_ICE_CORE_CLK 139 152 #define GCC_UFS_CARD_ICE_CORE_CLK_SRC 140 153 #define GCC_UFS_CARD_ICE_CORE_HW_CTL_CLK 141 154 #define GCC_UFS_CARD_PHY_AUX_CLK 142 155 #define GCC_UFS_CARD_PHY_AUX_CLK_SRC 143 156 #define GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK 144 157 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK 145 158 #define GCC_UFS_CARD_RX_SYMBOL_0_CLK_SRC 146 159 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK 147 160 #define GCC_UFS_CARD_RX_SYMBOL_1_CLK_SRC 148 161 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK 149 162 #define GCC_UFS_CARD_TX_SYMBOL_0_CLK_SRC 150 163 #define GCC_UFS_CARD_UNIPRO_CORE_CLK 151 164 #define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC 152 165 #define GCC_UFS_CARD_UNIPRO_CORE_HW_CTL_CLK 153 166 #define GCC_UFS_PHY_AHB_CLK 154 167 #define GCC_UFS_PHY_AXI_CLK 155 168 #define GCC_UFS_PHY_AXI_CLK_SRC 156 169 #define GCC_UFS_PHY_AXI_HW_CTL_CLK 157 170 #define GCC_UFS_PHY_ICE_CORE_CLK 158 171 #define GCC_UFS_PHY_ICE_CORE_CLK_SRC 159 172 #define GCC_UFS_PHY_ICE_CORE_HW_CTL_CLK 160 173 #define GCC_UFS_PHY_PHY_AUX_CLK 161 174 #define GCC_UFS_PHY_PHY_AUX_CLK_SRC 162 175 #define GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK 163 176 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK 164 177 #define GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC 165 178 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK 166 179 #define GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC 167 180 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK 168 181 #define GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC 169 182 #define GCC_UFS_PHY_UNIPRO_CORE_CLK 170 183 #define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 171 184 #define GCC_UFS_PHY_UNIPRO_CORE_HW_CTL_CLK 172 185 #define GCC_USB30_PRIM_MASTER_CLK 173 186 #define GCC_USB30_PRIM_MASTER_CLK__FORCE_MEM_CORE_ON 174 187 #define GCC_USB30_PRIM_MASTER_CLK_SRC 175 188 #define GCC_USB30_PRIM_MOCK_UTMI_CLK 176 189 #define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 177 190 #define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 178 191 #define GCC_USB30_PRIM_SLEEP_CLK 179 192 #define GCC_USB30_SEC_MASTER_CLK 180 193 #define GCC_USB30_SEC_MASTER_CLK__FORCE_MEM_CORE_ON 181 194 #define GCC_USB30_SEC_MASTER_CLK_SRC 182 195 #define GCC_USB30_SEC_MOCK_UTMI_CLK 183 196 #define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC 184 197 #define GCC_USB30_SEC_MOCK_UTMI_POSTDIV_CLK_SRC 185 198 #define GCC_USB30_SEC_SLEEP_CLK 186 199 #define GCC_USB3_PRIM_PHY_AUX_CLK 187 200 #define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 188 201 #define GCC_USB3_PRIM_PHY_COM_AUX_CLK 189 202 #define GCC_USB3_PRIM_PHY_PIPE_CLK 190 203 #define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 191 204 #define GCC_USB3_SEC_CLKREF_EN 192 205 #define GCC_USB3_SEC_PHY_AUX_CLK 193 206 #define GCC_USB3_SEC_PHY_AUX_CLK_SRC 194 207 #define GCC_USB3_SEC_PHY_COM_AUX_CLK 195 208 #define GCC_USB3_SEC_PHY_PIPE_CLK 196 209 #define GCC_USB3_SEC_PHY_PIPE_CLK_SRC 197 210 #define GCC_VIDEO_AXI0_CLK 198 211 #define GCC_VIDEO_AXI1_CLK 199 212 213 /* GCC resets */ 214 #define GCC_CAMERA_BCR 0 215 #define GCC_DISPLAY_BCR 1 216 #define GCC_GPU_BCR 2 217 #define GCC_MMSS_BCR 3 218 #define GCC_PCIE_0_BCR 4 219 #define GCC_PCIE_0_LINK_DOWN_BCR 5 220 #define GCC_PCIE_0_NOCSR_COM_PHY_BCR 6 221 #define GCC_PCIE_0_PHY_BCR 7 222 #define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 8 223 #define GCC_PCIE_1_BCR 9 224 #define GCC_PCIE_1_LINK_DOWN_BCR 10 225 #define GCC_PCIE_1_NOCSR_COM_PHY_BCR 11 226 #define GCC_PCIE_1_PHY_BCR 12 227 #define GCC_PCIE_1_PHY_NOCSR_COM_PHY_BCR 13 228 #define GCC_PCIE_PHY_CFG_AHB_BCR 14 229 #define GCC_PCIE_PHY_COM_BCR 15 230 #define GCC_PDM_BCR 16 231 #define GCC_QUPV3_WRAPPER_0_BCR 17 232 #define GCC_QUPV3_WRAPPER_1_BCR 18 233 #define GCC_QUPV3_WRAPPER_2_BCR 19 234 #define GCC_QUSB2PHY_PRIM_BCR 20 235 #define GCC_QUSB2PHY_SEC_BCR 21 236 #define GCC_SDCC2_BCR 22 237 #define GCC_SDCC4_BCR 23 238 #define GCC_UFS_CARD_BCR 24 239 #define GCC_UFS_PHY_BCR 25 240 #define GCC_USB30_PRIM_BCR 26 241 #define GCC_USB30_SEC_BCR 27 242 #define GCC_USB3_DP_PHY_PRIM_BCR 28 243 #define GCC_USB3_DP_PHY_SEC_BCR 29 244 #define GCC_USB3_PHY_PRIM_BCR 30 245 #define GCC_USB3_PHY_SEC_BCR 31 246 #define GCC_USB3PHY_PHY_PRIM_BCR 32 247 #define GCC_USB3PHY_PHY_SEC_BCR 33 248 #define GCC_USB_PHY_CFG_AHB2PHY_BCR 34 249 #define GCC_VIDEO_AXI0_CLK_ARES 35 250 #define GCC_VIDEO_AXI1_CLK_ARES 36 251 #define GCC_VIDEO_BCR 37 252 253 /* GCC power domains */ 254 #define PCIE_0_GDSC 0 255 #define PCIE_1_GDSC 1 256 #define UFS_CARD_GDSC 2 257 #define UFS_PHY_GDSC 3 258 #define USB30_PRIM_GDSC 4 259 #define USB30_SEC_GDSC 5 260 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 6 261 #define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC 7 262 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC 8 263 #define HLOS1_VOTE_MMNOC_MMU_TBU_SF1_GDSC 9 264 265 #endif 266
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