1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6 #ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H 7 #define _DT_BINDINGS_CLK_QCOM_CAM_CC_SM4450_H 8 9 /* CAM_CC clocks */ 10 #define CAM_CC_BPS_AHB_CLK 0 11 #define CAM_CC_BPS_AREG_CLK 1 12 #define CAM_CC_BPS_CLK 2 13 #define CAM_CC_BPS_CLK_SRC 3 14 #define CAM_CC_CAMNOC_ATB_CLK 4 15 #define CAM_CC_CAMNOC_AXI_CLK 5 16 #define CAM_CC_CAMNOC_AXI_CLK_SRC 6 17 #define CAM_CC_CAMNOC_AXI_HF_CLK 7 18 #define CAM_CC_CAMNOC_AXI_SF_CLK 8 19 #define CAM_CC_CCI_0_CLK 9 20 #define CAM_CC_CCI_0_CLK_SRC 10 21 #define CAM_CC_CCI_1_CLK 11 22 #define CAM_CC_CCI_1_CLK_SRC 12 23 #define CAM_CC_CORE_AHB_CLK 13 24 #define CAM_CC_CPAS_AHB_CLK 14 25 #define CAM_CC_CPHY_RX_CLK_SRC 15 26 #define CAM_CC_CRE_AHB_CLK 16 27 #define CAM_CC_CRE_CLK 17 28 #define CAM_CC_CRE_CLK_SRC 18 29 #define CAM_CC_CSI0PHYTIMER_CLK 19 30 #define CAM_CC_CSI0PHYTIMER_CLK_SRC 20 31 #define CAM_CC_CSI1PHYTIMER_CLK 21 32 #define CAM_CC_CSI1PHYTIMER_CLK_SRC 22 33 #define CAM_CC_CSI2PHYTIMER_CLK 23 34 #define CAM_CC_CSI2PHYTIMER_CLK_SRC 24 35 #define CAM_CC_CSIPHY0_CLK 25 36 #define CAM_CC_CSIPHY1_CLK 26 37 #define CAM_CC_CSIPHY2_CLK 27 38 #define CAM_CC_FAST_AHB_CLK_SRC 28 39 #define CAM_CC_ICP_ATB_CLK 29 40 #define CAM_CC_ICP_CLK 30 41 #define CAM_CC_ICP_CLK_SRC 31 42 #define CAM_CC_ICP_CTI_CLK 32 43 #define CAM_CC_ICP_TS_CLK 33 44 #define CAM_CC_MCLK0_CLK 34 45 #define CAM_CC_MCLK0_CLK_SRC 35 46 #define CAM_CC_MCLK1_CLK 36 47 #define CAM_CC_MCLK1_CLK_SRC 37 48 #define CAM_CC_MCLK2_CLK 38 49 #define CAM_CC_MCLK2_CLK_SRC 39 50 #define CAM_CC_MCLK3_CLK 40 51 #define CAM_CC_MCLK3_CLK_SRC 41 52 #define CAM_CC_OPE_0_AHB_CLK 42 53 #define CAM_CC_OPE_0_AREG_CLK 43 54 #define CAM_CC_OPE_0_CLK 44 55 #define CAM_CC_OPE_0_CLK_SRC 45 56 #define CAM_CC_PLL0 46 57 #define CAM_CC_PLL0_OUT_EVEN 47 58 #define CAM_CC_PLL0_OUT_ODD 48 59 #define CAM_CC_PLL1 49 60 #define CAM_CC_PLL1_OUT_EVEN 50 61 #define CAM_CC_PLL2 51 62 #define CAM_CC_PLL2_OUT_EVEN 52 63 #define CAM_CC_PLL3 53 64 #define CAM_CC_PLL3_OUT_EVEN 54 65 #define CAM_CC_PLL4 55 66 #define CAM_CC_PLL4_OUT_EVEN 56 67 #define CAM_CC_SLOW_AHB_CLK_SRC 57 68 #define CAM_CC_SOC_AHB_CLK 58 69 #define CAM_CC_SYS_TMR_CLK 59 70 #define CAM_CC_TFE_0_AHB_CLK 60 71 #define CAM_CC_TFE_0_CLK 61 72 #define CAM_CC_TFE_0_CLK_SRC 62 73 #define CAM_CC_TFE_0_CPHY_RX_CLK 63 74 #define CAM_CC_TFE_0_CSID_CLK 64 75 #define CAM_CC_TFE_0_CSID_CLK_SRC 65 76 #define CAM_CC_TFE_1_AHB_CLK 66 77 #define CAM_CC_TFE_1_CLK 67 78 #define CAM_CC_TFE_1_CLK_SRC 68 79 #define CAM_CC_TFE_1_CPHY_RX_CLK 69 80 #define CAM_CC_TFE_1_CSID_CLK 70 81 #define CAM_CC_TFE_1_CSID_CLK_SRC 71 82 83 /* CAM_CC power domains */ 84 #define CAM_CC_CAMSS_TOP_GDSC 0 85 86 /* CAM_CC resets */ 87 #define CAM_CC_BPS_BCR 0 88 #define CAM_CC_CAMNOC_BCR 1 89 #define CAM_CC_CAMSS_TOP_BCR 2 90 #define CAM_CC_CCI_0_BCR 3 91 #define CAM_CC_CCI_1_BCR 4 92 #define CAM_CC_CPAS_BCR 5 93 #define CAM_CC_CRE_BCR 6 94 #define CAM_CC_CSI0PHY_BCR 7 95 #define CAM_CC_CSI1PHY_BCR 8 96 #define CAM_CC_CSI2PHY_BCR 9 97 #define CAM_CC_ICP_BCR 10 98 #define CAM_CC_MCLK0_BCR 11 99 #define CAM_CC_MCLK1_BCR 12 100 #define CAM_CC_MCLK2_BCR 13 101 #define CAM_CC_MCLK3_BCR 14 102 #define CAM_CC_OPE_0_BCR 15 103 #define CAM_CC_TFE_0_BCR 16 104 #define CAM_CC_TFE_1_BCR 17 105 106 #endif 107
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