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TOMOYO Linux Cross Reference
Linux/include/dt-bindings/clock/qcom,sm8650-dispcc.h

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  1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*
  3  * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved
  4  * Copyright (c) 2023, Linaro Ltd.
  5  */
  6 
  7 #ifndef _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
  8 #define _DT_BINDINGS_CLK_QCOM_SM8650_DISP_CC_H
  9 
 10 /* DISP_CC clocks */
 11 #define DISP_CC_MDSS_ACCU_CLK                                   0
 12 #define DISP_CC_MDSS_AHB1_CLK                                   1
 13 #define DISP_CC_MDSS_AHB_CLK                                    2
 14 #define DISP_CC_MDSS_AHB_CLK_SRC                                3
 15 #define DISP_CC_MDSS_BYTE0_CLK                                  4
 16 #define DISP_CC_MDSS_BYTE0_CLK_SRC                              5
 17 #define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC                          6
 18 #define DISP_CC_MDSS_BYTE0_INTF_CLK                             7
 19 #define DISP_CC_MDSS_BYTE1_CLK                                  8
 20 #define DISP_CC_MDSS_BYTE1_CLK_SRC                              9
 21 #define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC                          10
 22 #define DISP_CC_MDSS_BYTE1_INTF_CLK                             11
 23 #define DISP_CC_MDSS_DPTX0_AUX_CLK                              12
 24 #define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC                          13
 25 #define DISP_CC_MDSS_DPTX0_CRYPTO_CLK                           14
 26 #define DISP_CC_MDSS_DPTX0_LINK_CLK                             15
 27 #define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC                         16
 28 #define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC                     17
 29 #define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK                        18
 30 #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK                           19
 31 #define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC                       20
 32 #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK                           21
 33 #define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC                       22
 34 #define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK             23
 35 #define DISP_CC_MDSS_DPTX1_AUX_CLK                              24
 36 #define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC                          25
 37 #define DISP_CC_MDSS_DPTX1_CRYPTO_CLK                           26
 38 #define DISP_CC_MDSS_DPTX1_LINK_CLK                             27
 39 #define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC                         28
 40 #define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC                     29
 41 #define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK                        30
 42 #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK                           31
 43 #define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC                       32
 44 #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK                           33
 45 #define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC                       34
 46 #define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK             35
 47 #define DISP_CC_MDSS_DPTX2_AUX_CLK                              36
 48 #define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC                          37
 49 #define DISP_CC_MDSS_DPTX2_CRYPTO_CLK                           38
 50 #define DISP_CC_MDSS_DPTX2_LINK_CLK                             39
 51 #define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC                         40
 52 #define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC                     41
 53 #define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK                        42
 54 #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK                           43
 55 #define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC                       44
 56 #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK                           45
 57 #define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC                       46
 58 #define DISP_CC_MDSS_DPTX3_AUX_CLK                              47
 59 #define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC                          48
 60 #define DISP_CC_MDSS_DPTX3_CRYPTO_CLK                           49
 61 #define DISP_CC_MDSS_DPTX3_LINK_CLK                             50
 62 #define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC                         51
 63 #define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC                     52
 64 #define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK                        53
 65 #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK                           54
 66 #define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC                       55
 67 #define DISP_CC_MDSS_ESC0_CLK                                   56
 68 #define DISP_CC_MDSS_ESC0_CLK_SRC                               57
 69 #define DISP_CC_MDSS_ESC1_CLK                                   58
 70 #define DISP_CC_MDSS_ESC1_CLK_SRC                               59
 71 #define DISP_CC_MDSS_MDP1_CLK                                   60
 72 #define DISP_CC_MDSS_MDP_CLK                                    61
 73 #define DISP_CC_MDSS_MDP_CLK_SRC                                62
 74 #define DISP_CC_MDSS_MDP_LUT1_CLK                               63
 75 #define DISP_CC_MDSS_MDP_LUT_CLK                                64
 76 #define DISP_CC_MDSS_NON_GDSC_AHB_CLK                           65
 77 #define DISP_CC_MDSS_PCLK0_CLK                                  66
 78 #define DISP_CC_MDSS_PCLK0_CLK_SRC                              67
 79 #define DISP_CC_MDSS_PCLK1_CLK                                  68
 80 #define DISP_CC_MDSS_PCLK1_CLK_SRC                              69
 81 #define DISP_CC_MDSS_RSCC_AHB_CLK                               70
 82 #define DISP_CC_MDSS_RSCC_VSYNC_CLK                             71
 83 #define DISP_CC_MDSS_VSYNC1_CLK                                 72
 84 #define DISP_CC_MDSS_VSYNC_CLK                                  73
 85 #define DISP_CC_MDSS_VSYNC_CLK_SRC                              74
 86 #define DISP_CC_PLL0                                            75
 87 #define DISP_CC_PLL1                                            76
 88 #define DISP_CC_SLEEP_CLK                                       77
 89 #define DISP_CC_SLEEP_CLK_SRC                                   78
 90 #define DISP_CC_XO_CLK                                          79
 91 #define DISP_CC_XO_CLK_SRC                                      80
 92 
 93 /* DISP_CC resets */
 94 #define DISP_CC_MDSS_CORE_BCR                                   0
 95 #define DISP_CC_MDSS_CORE_INT2_BCR                              1
 96 #define DISP_CC_MDSS_RSCC_BCR                                   2
 97 
 98 /* DISP_CC GDSCR */
 99 #define MDSS_GDSC                                               0
100 #define MDSS_INT2_GDSC                                          1
101 
102 #endif
103 

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