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Linux/include/dt-bindings/clock/r8a779g0-cpg-mssr.h

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  1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
  2 /*
  3  * Copyright (C) 2022 Renesas Electronics Corp.
  4  */
  5 #ifndef __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
  6 #define __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__
  7 
  8 #include <dt-bindings/clock/renesas-cpg-mssr.h>
  9 
 10 /* r8a779g0 CPG Core Clocks */
 11 
 12 #define R8A779G0_CLK_ZX                 0
 13 #define R8A779G0_CLK_ZS                 1
 14 #define R8A779G0_CLK_ZT                 2
 15 #define R8A779G0_CLK_ZTR                3
 16 #define R8A779G0_CLK_S0D2               4
 17 #define R8A779G0_CLK_S0D3               5
 18 #define R8A779G0_CLK_S0D4               6
 19 #define R8A779G0_CLK_S0D1_VIO           7
 20 #define R8A779G0_CLK_S0D2_VIO           8
 21 #define R8A779G0_CLK_S0D4_VIO           9
 22 #define R8A779G0_CLK_S0D8_VIO           10
 23 #define R8A779G0_CLK_S0D1_VC            11
 24 #define R8A779G0_CLK_S0D2_VC            12
 25 #define R8A779G0_CLK_S0D4_VC            13
 26 #define R8A779G0_CLK_S0D2_MM            14
 27 #define R8A779G0_CLK_S0D4_MM            15
 28 #define R8A779G0_CLK_S0D2_U3DG          16
 29 #define R8A779G0_CLK_S0D4_U3DG          17
 30 #define R8A779G0_CLK_S0D2_RT            18
 31 #define R8A779G0_CLK_S0D3_RT            19
 32 #define R8A779G0_CLK_S0D4_RT            20
 33 #define R8A779G0_CLK_S0D6_RT            21
 34 #define R8A779G0_CLK_S0D24_RT           22
 35 #define R8A779G0_CLK_S0D2_PER           23
 36 #define R8A779G0_CLK_S0D3_PER           24
 37 #define R8A779G0_CLK_S0D4_PER           25
 38 #define R8A779G0_CLK_S0D6_PER           26
 39 #define R8A779G0_CLK_S0D12_PER          27
 40 #define R8A779G0_CLK_S0D24_PER          28
 41 #define R8A779G0_CLK_S0D1_HSC           29
 42 #define R8A779G0_CLK_S0D2_HSC           30
 43 #define R8A779G0_CLK_S0D4_HSC           31
 44 #define R8A779G0_CLK_S0D2_CC            32
 45 #define R8A779G0_CLK_SVD1_IR            33
 46 #define R8A779G0_CLK_SVD2_IR            34
 47 #define R8A779G0_CLK_SVD1_VIP           35
 48 #define R8A779G0_CLK_SVD2_VIP           36
 49 #define R8A779G0_CLK_CL                 37
 50 #define R8A779G0_CLK_CL16M              38
 51 #define R8A779G0_CLK_CL16M_MM           39
 52 #define R8A779G0_CLK_CL16M_RT           40
 53 #define R8A779G0_CLK_CL16M_PER          41
 54 #define R8A779G0_CLK_CL16M_HSC          42
 55 #define R8A779G0_CLK_Z0                 43
 56 #define R8A779G0_CLK_ZB3                44
 57 #define R8A779G0_CLK_ZB3D2              45
 58 #define R8A779G0_CLK_ZB3D4              46
 59 #define R8A779G0_CLK_ZG                 47
 60 #define R8A779G0_CLK_SD0H               48
 61 #define R8A779G0_CLK_SD0                49
 62 #define R8A779G0_CLK_RPC                50
 63 #define R8A779G0_CLK_RPCD2              51
 64 #define R8A779G0_CLK_MSO                52
 65 #define R8A779G0_CLK_CANFD              53
 66 #define R8A779G0_CLK_CSI                54
 67 #define R8A779G0_CLK_FRAY               55
 68 #define R8A779G0_CLK_IPC                56
 69 #define R8A779G0_CLK_SASYNCRT           57
 70 #define R8A779G0_CLK_SASYNCPERD1        58
 71 #define R8A779G0_CLK_SASYNCPERD2        59
 72 #define R8A779G0_CLK_SASYNCPERD4        60
 73 #define R8A779G0_CLK_VIOBUS             61
 74 #define R8A779G0_CLK_VIOBUSD2           62
 75 #define R8A779G0_CLK_VCBUS              63
 76 #define R8A779G0_CLK_VCBUSD2            64
 77 #define R8A779G0_CLK_DSIEXT             65
 78 #define R8A779G0_CLK_DSIREF             66
 79 #define R8A779G0_CLK_ADGH               67
 80 #define R8A779G0_CLK_OSC                68
 81 #define R8A779G0_CLK_ZR0                69
 82 #define R8A779G0_CLK_ZR1                70
 83 #define R8A779G0_CLK_ZR2                71
 84 #define R8A779G0_CLK_IMPA               72
 85 #define R8A779G0_CLK_IMPAD4             73
 86 #define R8A779G0_CLK_CPEX               74
 87 #define R8A779G0_CLK_CBFUSA             75
 88 #define R8A779G0_CLK_R                  76
 89 #define R8A779G0_CLK_CP                 77
 90 
 91 #endif /* __DT_BINDINGS_CLOCK_R8A779G0_CPG_MSSR_H__ */
 92 

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