1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ 2 /* 3 * Copyright (c) 2023 Rockchip Electronics Co. Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Elaine Zhang <zhangqing@rock-chips.com> 7 * Author: Detlev Casanova <detlev.casanova@collabora.com> 8 */ 9 10 #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 11 #define _DT_BINDINGS_CLK_ROCKCHIP_RK3576_H 12 13 /* cru-clocks indices */ 14 15 /* cru plls */ 16 #define PLL_BPLL 0 17 #define PLL_LPLL 1 18 #define PLL_VPLL 2 19 #define PLL_AUPLL 3 20 #define PLL_CPLL 4 21 #define PLL_GPLL 5 22 #define PLL_PPLL 6 23 #define ARMCLK_L 7 24 #define ARMCLK_B 8 25 26 /* cru clocks */ 27 #define CLK_CPLL_DIV20 9 28 #define CLK_CPLL_DIV10 10 29 #define CLK_GPLL_DIV8 11 30 #define CLK_GPLL_DIV6 12 31 #define CLK_CPLL_DIV4 13 32 #define CLK_GPLL_DIV4 14 33 #define CLK_SPLL_DIV2 15 34 #define CLK_GPLL_DIV3 16 35 #define CLK_CPLL_DIV2 17 36 #define CLK_GPLL_DIV2 18 37 #define CLK_SPLL_DIV1 19 38 #define PCLK_TOP_ROOT 20 39 #define ACLK_TOP 21 40 #define HCLK_TOP 22 41 #define CLK_AUDIO_FRAC_0 23 42 #define CLK_AUDIO_FRAC_1 24 43 #define CLK_AUDIO_FRAC_2 25 44 #define CLK_AUDIO_FRAC_3 26 45 #define CLK_UART_FRAC_0 27 46 #define CLK_UART_FRAC_1 28 47 #define CLK_UART_FRAC_2 29 48 #define CLK_UART1_SRC_TOP 30 49 #define CLK_AUDIO_INT_0 31 50 #define CLK_AUDIO_INT_1 32 51 #define CLK_AUDIO_INT_2 33 52 #define CLK_PDM0_SRC_TOP 34 53 #define CLK_PDM1_OUT 35 54 #define CLK_GMAC0_125M_SRC 36 55 #define CLK_GMAC1_125M_SRC 37 56 #define LCLK_ASRC_SRC_0 38 57 #define LCLK_ASRC_SRC_1 39 58 #define REF_CLK0_OUT_PLL 40 59 #define REF_CLK1_OUT_PLL 41 60 #define REF_CLK2_OUT_PLL 42 61 #define REFCLKO25M_GMAC0_OUT 43 62 #define REFCLKO25M_GMAC1_OUT 44 63 #define CLK_CIFOUT_OUT 45 64 #define CLK_GMAC0_RMII_CRU 46 65 #define CLK_GMAC1_RMII_CRU 47 66 #define CLK_OTPC_AUTO_RD_G 48 67 #define CLK_OTP_PHY_G 49 68 #define CLK_MIPI_CAMERAOUT_M0 50 69 #define CLK_MIPI_CAMERAOUT_M1 51 70 #define CLK_MIPI_CAMERAOUT_M2 52 71 #define MCLK_PDM0_SRC_TOP 53 72 #define HCLK_AUDIO_ROOT 54 73 #define HCLK_ASRC_2CH_0 55 74 #define HCLK_ASRC_2CH_1 56 75 #define HCLK_ASRC_4CH_0 57 76 #define HCLK_ASRC_4CH_1 58 77 #define CLK_ASRC_2CH_0 59 78 #define CLK_ASRC_2CH_1 60 79 #define CLK_ASRC_4CH_0 61 80 #define CLK_ASRC_4CH_1 62 81 #define MCLK_SAI0_8CH_SRC 63 82 #define MCLK_SAI0_8CH 64 83 #define HCLK_SAI0_8CH 65 84 #define HCLK_SPDIF_RX0 66 85 #define MCLK_SPDIF_RX0 67 86 #define HCLK_SPDIF_RX1 68 87 #define MCLK_SPDIF_RX1 69 88 #define MCLK_SAI1_8CH_SRC 70 89 #define MCLK_SAI1_8CH 71 90 #define HCLK_SAI1_8CH 72 91 #define MCLK_SAI2_2CH_SRC 73 92 #define MCLK_SAI2_2CH 74 93 #define HCLK_SAI2_2CH 75 94 #define MCLK_SAI3_2CH_SRC 76 95 #define MCLK_SAI3_2CH 77 96 #define HCLK_SAI3_2CH 78 97 #define MCLK_SAI4_2CH_SRC 79 98 #define MCLK_SAI4_2CH 80 99 #define HCLK_SAI4_2CH 81 100 #define HCLK_ACDCDIG_DSM 82 101 #define MCLK_ACDCDIG_DSM 83 102 #define CLK_PDM1 84 103 #define HCLK_PDM1 85 104 #define MCLK_PDM1 86 105 #define HCLK_SPDIF_TX0 87 106 #define MCLK_SPDIF_TX0 88 107 #define HCLK_SPDIF_TX1 89 108 #define MCLK_SPDIF_TX1 90 109 #define CLK_SAI1_MCLKOUT 91 110 #define CLK_SAI2_MCLKOUT 92 111 #define CLK_SAI3_MCLKOUT 93 112 #define CLK_SAI4_MCLKOUT 94 113 #define CLK_SAI0_MCLKOUT 95 114 #define HCLK_BUS_ROOT 96 115 #define PCLK_BUS_ROOT 97 116 #define ACLK_BUS_ROOT 98 117 #define HCLK_CAN0 99 118 #define CLK_CAN0 100 119 #define HCLK_CAN1 101 120 #define CLK_CAN1 102 121 #define CLK_KEY_SHIFT 103 122 #define PCLK_I2C1 104 123 #define PCLK_I2C2 105 124 #define PCLK_I2C3 106 125 #define PCLK_I2C4 107 126 #define PCLK_I2C5 108 127 #define PCLK_I2C6 109 128 #define PCLK_I2C7 110 129 #define PCLK_I2C8 111 130 #define PCLK_I2C9 112 131 #define PCLK_WDT_BUSMCU 113 132 #define TCLK_WDT_BUSMCU 114 133 #define ACLK_GIC 115 134 #define CLK_I2C1 116 135 #define CLK_I2C2 117 136 #define CLK_I2C3 118 137 #define CLK_I2C4 119 138 #define CLK_I2C5 120 139 #define CLK_I2C6 121 140 #define CLK_I2C7 122 141 #define CLK_I2C8 123 142 #define CLK_I2C9 124 143 #define PCLK_SARADC 125 144 #define CLK_SARADC 126 145 #define PCLK_TSADC 127 146 #define CLK_TSADC 128 147 #define PCLK_UART0 129 148 #define PCLK_UART2 130 149 #define PCLK_UART3 131 150 #define PCLK_UART4 132 151 #define PCLK_UART5 133 152 #define PCLK_UART6 134 153 #define PCLK_UART7 135 154 #define PCLK_UART8 136 155 #define PCLK_UART9 137 156 #define PCLK_UART10 138 157 #define PCLK_UART11 139 158 #define SCLK_UART0 140 159 #define SCLK_UART2 141 160 #define SCLK_UART3 142 161 #define SCLK_UART4 143 162 #define SCLK_UART5 144 163 #define SCLK_UART6 145 164 #define SCLK_UART7 146 165 #define SCLK_UART8 147 166 #define SCLK_UART9 148 167 #define SCLK_UART10 149 168 #define SCLK_UART11 150 169 #define PCLK_SPI0 151 170 #define PCLK_SPI1 152 171 #define PCLK_SPI2 153 172 #define PCLK_SPI3 154 173 #define PCLK_SPI4 155 174 #define CLK_SPI0 156 175 #define CLK_SPI1 157 176 #define CLK_SPI2 158 177 #define CLK_SPI3 159 178 #define CLK_SPI4 160 179 #define PCLK_WDT0 161 180 #define TCLK_WDT0 162 181 #define PCLK_PWM1 163 182 #define CLK_PWM1 164 183 #define CLK_OSC_PWM1 165 184 #define CLK_RC_PWM1 166 185 #define PCLK_BUSTIMER0 167 186 #define PCLK_BUSTIMER1 168 187 #define CLK_TIMER0_ROOT 169 188 #define CLK_TIMER0 170 189 #define CLK_TIMER1 171 190 #define CLK_TIMER2 172 191 #define CLK_TIMER3 173 192 #define CLK_TIMER4 174 193 #define CLK_TIMER5 175 194 #define PCLK_MAILBOX0 176 195 #define PCLK_GPIO1 177 196 #define DBCLK_GPIO1 178 197 #define PCLK_GPIO2 179 198 #define DBCLK_GPIO2 180 199 #define PCLK_GPIO3 181 200 #define DBCLK_GPIO3 182 201 #define PCLK_GPIO4 183 202 #define DBCLK_GPIO4 184 203 #define ACLK_DECOM 185 204 #define PCLK_DECOM 186 205 #define DCLK_DECOM 187 206 #define CLK_TIMER1_ROOT 188 207 #define CLK_TIMER6 189 208 #define CLK_TIMER7 190 209 #define CLK_TIMER8 191 210 #define CLK_TIMER9 192 211 #define CLK_TIMER10 193 212 #define CLK_TIMER11 194 213 #define ACLK_DMAC0 195 214 #define ACLK_DMAC1 196 215 #define ACLK_DMAC2 197 216 #define ACLK_SPINLOCK 198 217 #define HCLK_I3C0 199 218 #define HCLK_I3C1 200 219 #define HCLK_BUS_CM0_ROOT 201 220 #define FCLK_BUS_CM0_CORE 202 221 #define CLK_BUS_CM0_RTC 203 222 #define PCLK_PMU2 204 223 #define PCLK_PWM2 205 224 #define CLK_PWM2 206 225 #define CLK_RC_PWM2 207 226 #define CLK_OSC_PWM2 208 227 #define CLK_FREQ_PWM1 209 228 #define CLK_COUNTER_PWM1 210 229 #define SAI_SCLKIN_FREQ 211 230 #define SAI_SCLKIN_COUNTER 212 231 #define CLK_I3C0 213 232 #define CLK_I3C1 214 233 #define PCLK_CSIDPHY1 215 234 #define PCLK_DDR_ROOT 216 235 #define PCLK_DDR_MON_CH0 217 236 #define TMCLK_DDR_MON_CH0 218 237 #define ACLK_DDR_ROOT 219 238 #define HCLK_DDR_ROOT 220 239 #define FCLK_DDR_CM0_CORE 221 240 #define CLK_DDR_TIMER_ROOT 222 241 #define CLK_DDR_TIMER0 223 242 #define CLK_DDR_TIMER1 224 243 #define TCLK_WDT_DDR 225 244 #define PCLK_WDT 226 245 #define PCLK_TIMER 227 246 #define CLK_DDR_CM0_RTC 228 247 #define ACLK_RKNN0 229 248 #define ACLK_RKNN1 230 249 #define HCLK_RKNN_ROOT 231 250 #define CLK_RKNN_DSU0 232 251 #define PCLK_NPUTOP_ROOT 233 252 #define PCLK_NPU_TIMER 234 253 #define CLK_NPUTIMER_ROOT 235 254 #define CLK_NPUTIMER0 236 255 #define CLK_NPUTIMER1 237 256 #define PCLK_NPU_WDT 238 257 #define TCLK_NPU_WDT 239 258 #define ACLK_RKNN_CBUF 240 259 #define HCLK_NPU_CM0_ROOT 241 260 #define FCLK_NPU_CM0_CORE 242 261 #define CLK_NPU_CM0_RTC 243 262 #define HCLK_RKNN_CBUF 244 263 #define HCLK_NVM_ROOT 245 264 #define ACLK_NVM_ROOT 246 265 #define SCLK_FSPI_X2 247 266 #define HCLK_FSPI 248 267 #define CCLK_SRC_EMMC 249 268 #define HCLK_EMMC 250 269 #define ACLK_EMMC 251 270 #define BCLK_EMMC 252 271 #define TCLK_EMMC 253 272 #define PCLK_PHP_ROOT 254 273 #define ACLK_PHP_ROOT 255 274 #define PCLK_PCIE0 256 275 #define CLK_PCIE0_AUX 257 276 #define ACLK_PCIE0_MST 258 277 #define ACLK_PCIE0_SLV 259 278 #define ACLK_PCIE0_DBI 260 279 #define ACLK_USB3OTG1 261 280 #define CLK_REF_USB3OTG1 262 281 #define CLK_SUSPEND_USB3OTG1 263 282 #define ACLK_MMU0 264 283 #define ACLK_SLV_MMU0 265 284 #define ACLK_MMU1 266 285 #define ACLK_SLV_MMU1 267 286 #define PCLK_PCIE1 268 287 #define CLK_PCIE1_AUX 269 288 #define ACLK_PCIE1_MST 270 289 #define ACLK_PCIE1_SLV 271 290 #define ACLK_PCIE1_DBI 272 291 #define CLK_RXOOB0 273 292 #define CLK_RXOOB1 274 293 #define CLK_PMALIVE0 275 294 #define CLK_PMALIVE1 276 295 #define ACLK_SATA0 277 296 #define ACLK_SATA1 278 297 #define CLK_USB3OTG1_PIPE_PCLK 279 298 #define CLK_USB3OTG1_UTMI 280 299 #define CLK_USB3OTG0_PIPE_PCLK 281 300 #define CLK_USB3OTG0_UTMI 282 301 #define HCLK_SDGMAC_ROOT 283 302 #define ACLK_SDGMAC_ROOT 284 303 #define PCLK_SDGMAC_ROOT 285 304 #define ACLK_GMAC0 286 305 #define ACLK_GMAC1 287 306 #define PCLK_GMAC0 288 307 #define PCLK_GMAC1 289 308 #define CCLK_SRC_SDIO 290 309 #define HCLK_SDIO 291 310 #define CLK_GMAC1_PTP_REF 292 311 #define CLK_GMAC0_PTP_REF 293 312 #define CLK_GMAC1_PTP_REF_SRC 294 313 #define CLK_GMAC0_PTP_REF_SRC 295 314 #define CCLK_SRC_SDMMC0 296 315 #define HCLK_SDMMC0 297 316 #define SCLK_FSPI1_X2 298 317 #define HCLK_FSPI1 299 318 #define ACLK_DSMC_ROOT 300 319 #define ACLK_DSMC 301 320 #define PCLK_DSMC 302 321 #define CLK_DSMC_SYS 303 322 #define HCLK_HSGPIO 304 323 #define CLK_HSGPIO_TX 305 324 #define CLK_HSGPIO_RX 306 325 #define ACLK_HSGPIO 307 326 #define PCLK_PHPPHY_ROOT 308 327 #define PCLK_PCIE2_COMBOPHY0 309 328 #define PCLK_PCIE2_COMBOPHY1 310 329 #define CLK_PCIE_100M_SRC 311 330 #define CLK_PCIE_100M_NDUTY_SRC 312 331 #define CLK_REF_PCIE0_PHY 313 332 #define CLK_REF_PCIE1_PHY 314 333 #define CLK_REF_MPHY_26M 315 334 #define HCLK_RKVDEC_ROOT 316 335 #define ACLK_RKVDEC_ROOT 317 336 #define HCLK_RKVDEC 318 337 #define CLK_RKVDEC_HEVC_CA 319 338 #define CLK_RKVDEC_CORE 320 339 #define ACLK_UFS_ROOT 321 340 #define ACLK_USB_ROOT 322 341 #define PCLK_USB_ROOT 323 342 #define ACLK_USB3OTG0 324 343 #define CLK_REF_USB3OTG0 325 344 #define CLK_SUSPEND_USB3OTG0 326 345 #define ACLK_MMU2 327 346 #define ACLK_SLV_MMU2 328 347 #define ACLK_UFS_SYS 329 348 #define ACLK_VPU_ROOT 330 349 #define ACLK_VPU_MID_ROOT 331 350 #define HCLK_VPU_ROOT 332 351 #define ACLK_JPEG_ROOT 333 352 #define ACLK_VPU_LOW_ROOT 334 353 #define HCLK_RGA2E_0 335 354 #define ACLK_RGA2E_0 336 355 #define CLK_CORE_RGA2E_0 337 356 #define ACLK_JPEG 338 357 #define HCLK_JPEG 339 358 #define HCLK_VDPP 340 359 #define ACLK_VDPP 341 360 #define CLK_CORE_VDPP 342 361 #define HCLK_RGA2E_1 343 362 #define ACLK_RGA2E_1 344 363 #define CLK_CORE_RGA2E_1 345 364 #define DCLK_EBC_FRAC_SRC 346 365 #define HCLK_EBC 347 366 #define ACLK_EBC 348 367 #define DCLK_EBC 349 368 #define HCLK_VEPU0_ROOT 350 369 #define ACLK_VEPU0_ROOT 351 370 #define HCLK_VEPU0 352 371 #define ACLK_VEPU0 353 372 #define CLK_VEPU0_CORE 354 373 #define ACLK_VI_ROOT 355 374 #define HCLK_VI_ROOT 356 375 #define PCLK_VI_ROOT 357 376 #define DCLK_VICAP 358 377 #define ACLK_VICAP 359 378 #define HCLK_VICAP 360 379 #define CLK_ISP_CORE 361 380 #define CLK_ISP_CORE_MARVIN 362 381 #define CLK_ISP_CORE_VICAP 363 382 #define ACLK_ISP 364 383 #define HCLK_ISP 365 384 #define ACLK_VPSS 366 385 #define HCLK_VPSS 367 386 #define CLK_CORE_VPSS 368 387 #define PCLK_CSI_HOST_0 369 388 #define PCLK_CSI_HOST_1 370 389 #define PCLK_CSI_HOST_2 371 390 #define PCLK_CSI_HOST_3 372 391 #define PCLK_CSI_HOST_4 373 392 #define ICLK_CSIHOST01 374 393 #define ICLK_CSIHOST0 375 394 #define CLK_ISP_PVTPLL_SRC 376 395 #define ACLK_VI_ROOT_INTER 377 396 #define CLK_VICAP_I0CLK 378 397 #define CLK_VICAP_I1CLK 379 398 #define CLK_VICAP_I2CLK 380 399 #define CLK_VICAP_I3CLK 381 400 #define CLK_VICAP_I4CLK 382 401 #define ACLK_VOP_ROOT 383 402 #define HCLK_VOP_ROOT 384 403 #define PCLK_VOP_ROOT 385 404 #define HCLK_VOP 386 405 #define ACLK_VOP 387 406 #define DCLK_VP0_SRC 388 407 #define DCLK_VP1_SRC 389 408 #define DCLK_VP2_SRC 390 409 #define DCLK_VP0 391 410 #define DCLK_VP1 392 411 #define DCLK_VP2 393 412 #define PCLK_VOPGRF 394 413 #define ACLK_VO0_ROOT 395 414 #define HCLK_VO0_ROOT 396 415 #define PCLK_VO0_ROOT 397 416 #define PCLK_VO0_GRF 398 417 #define ACLK_HDCP0 399 418 #define HCLK_HDCP0 400 419 #define PCLK_HDCP0 401 420 #define CLK_TRNG0_SKP 402 421 #define PCLK_DSIHOST0 403 422 #define CLK_DSIHOST0 404 423 #define PCLK_HDMITX0 405 424 #define CLK_HDMITX0_EARC 406 425 #define CLK_HDMITX0_REF 407 426 #define PCLK_EDP0 408 427 #define CLK_EDP0_24M 409 428 #define CLK_EDP0_200M 410 429 #define MCLK_SAI5_8CH_SRC 411 430 #define MCLK_SAI5_8CH 412 431 #define HCLK_SAI5_8CH 413 432 #define MCLK_SAI6_8CH_SRC 414 433 #define MCLK_SAI6_8CH 415 434 #define HCLK_SAI6_8CH 416 435 #define HCLK_SPDIF_TX2 417 436 #define MCLK_SPDIF_TX2 418 437 #define HCLK_SPDIF_RX2 419 438 #define MCLK_SPDIF_RX2 420 439 #define HCLK_SAI8_8CH 421 440 #define MCLK_SAI8_8CH_SRC 422 441 #define MCLK_SAI8_8CH 423 442 #define ACLK_VO1_ROOT 424 443 #define HCLK_VO1_ROOT 425 444 #define PCLK_VO1_ROOT 426 445 #define MCLK_SAI7_8CH_SRC 427 446 #define MCLK_SAI7_8CH 428 447 #define HCLK_SAI7_8CH 429 448 #define HCLK_SPDIF_TX3 430 449 #define HCLK_SPDIF_TX4 431 450 #define HCLK_SPDIF_TX5 432 451 #define MCLK_SPDIF_TX3 433 452 #define CLK_AUX16MHZ_0 434 453 #define ACLK_DP0 435 454 #define PCLK_DP0 436 455 #define PCLK_VO1_GRF 437 456 #define ACLK_HDCP1 438 457 #define HCLK_HDCP1 439 458 #define PCLK_HDCP1 440 459 #define CLK_TRNG1_SKP 441 460 #define HCLK_SAI9_8CH 442 461 #define MCLK_SAI9_8CH_SRC 443 462 #define MCLK_SAI9_8CH 444 463 #define MCLK_SPDIF_TX4 445 464 #define MCLK_SPDIF_TX5 446 465 #define CLK_GPU_SRC_PRE 447 466 #define CLK_GPU 448 467 #define PCLK_GPU_ROOT 449 468 #define ACLK_CENTER_ROOT 450 469 #define ACLK_CENTER_LOW_ROOT 451 470 #define HCLK_CENTER_ROOT 452 471 #define PCLK_CENTER_ROOT 453 472 #define ACLK_DMA2DDR 454 473 #define ACLK_DDR_SHAREMEM 455 474 #define PCLK_DMA2DDR 456 475 #define PCLK_SHAREMEM 457 476 #define HCLK_VEPU1_ROOT 458 477 #define ACLK_VEPU1_ROOT 459 478 #define HCLK_VEPU1 460 479 #define ACLK_VEPU1 461 480 #define CLK_VEPU1_CORE 462 481 #define CLK_JDBCK_DAP 463 482 #define PCLK_MIPI_DCPHY 464 483 #define CLK_32K_USB2DEBUG 465 484 #define PCLK_CSIDPHY 466 485 #define PCLK_USBDPPHY 467 486 #define CLK_PMUPHY_REF_SRC 468 487 #define CLK_USBDP_COMBO_PHY_IMMORTAL 469 488 #define CLK_HDMITXHDP 470 489 #define PCLK_MPHY 471 490 #define CLK_REF_OSC_MPHY 472 491 #define CLK_REF_UFS_CLKOUT 473 492 #define HCLK_PMU1_ROOT 474 493 #define HCLK_PMU_CM0_ROOT 475 494 #define CLK_200M_PMU_SRC 476 495 #define CLK_100M_PMU_SRC 477 496 #define CLK_50M_PMU_SRC 478 497 #define FCLK_PMU_CM0_CORE 479 498 #define CLK_PMU_CM0_RTC 480 499 #define PCLK_PMU1 481 500 #define CLK_PMU1 482 501 #define PCLK_PMU1WDT 483 502 #define TCLK_PMU1WDT 484 503 #define PCLK_PMUTIMER 485 504 #define CLK_PMUTIMER_ROOT 486 505 #define CLK_PMUTIMER0 487 506 #define CLK_PMUTIMER1 488 507 #define PCLK_PMU1PWM 489 508 #define CLK_PMU1PWM 490 509 #define CLK_PMU1PWM_OSC 491 510 #define PCLK_PMUPHY_ROOT 492 511 #define PCLK_I2C0 493 512 #define CLK_I2C0 494 513 #define SCLK_UART1 495 514 #define PCLK_UART1 496 515 #define CLK_PMU1PWM_RC 497 516 #define CLK_PDM0 498 517 #define HCLK_PDM0 499 518 #define MCLK_PDM0 500 519 #define HCLK_VAD 501 520 #define CLK_OSCCHK_PVTM 502 521 #define CLK_PDM0_OUT 503 522 #define CLK_HPTIMER_SRC 504 523 #define PCLK_PMU0_ROOT 505 524 #define PCLK_PMU0 506 525 #define PCLK_GPIO0 507 526 #define DBCLK_GPIO0 508 527 #define CLK_OSC0_PMU1 509 528 #define PCLK_PMU1_ROOT 510 529 #define XIN_OSC0_DIV 511 530 #define ACLK_USB 512 531 #define ACLK_UFS 513 532 #define ACLK_SDGMAC 514 533 #define HCLK_SDGMAC 515 534 #define PCLK_SDGMAC 516 535 #define HCLK_VO1 517 536 #define HCLK_VO0 518 537 #define PCLK_CCI_ROOT 519 538 #define ACLK_CCI_ROOT 520 539 #define HCLK_VO0VOP_CHANNEL 521 540 #define ACLK_VO0VOP_CHANNEL 522 541 #define ACLK_TOP_MID 523 542 #define ACLK_SECURE_HIGH 524 543 #define CLK_USBPHY_REF_SRC 525 544 #define CLK_PHY_REF_SRC 526 545 #define CLK_CPLL_REF_SRC 527 546 #define CLK_AUPLL_REF_SRC 528 547 #define PCLK_SECURE_NS 529 548 #define HCLK_SECURE_NS 530 549 #define ACLK_SECURE_NS 531 550 #define PCLK_OTPC_NS 532 551 #define HCLK_CRYPTO_NS 533 552 #define HCLK_TRNG_NS 534 553 #define CLK_OTPC_NS 535 554 #define SCLK_DSU 536 555 #define SCLK_DDR 537 556 #define ACLK_CRYPTO_NS 538 557 #define CLK_PKA_CRYPTO_NS 539 558 #define ACLK_RKVDEC_ROOT_BAK 540 559 #define CLK_AUDIO_FRAC_0_SRC 541 560 #define CLK_AUDIO_FRAC_1_SRC 542 561 #define CLK_AUDIO_FRAC_2_SRC 543 562 #define CLK_AUDIO_FRAC_3_SRC 544 563 #define PCLK_HDPTX_APB 545 564 565 /* secure clk */ 566 #define CLK_STIMER0_ROOT 546 567 #define CLK_STIMER1_ROOT 547 568 #define PCLK_SECURE_S 548 569 #define HCLK_SECURE_S 549 570 #define ACLK_SECURE_S 550 571 #define CLK_PKA_CRYPTO_S 551 572 #define HCLK_VO1_S 552 573 #define PCLK_VO1_S 553 574 #define HCLK_VO0_S 554 575 #define PCLK_VO0_S 555 576 #define PCLK_KLAD 556 577 #define HCLK_CRYPTO_S 557 578 #define HCLK_KLAD 558 579 #define ACLK_CRYPTO_S 559 580 #define HCLK_TRNG_S 560 581 #define PCLK_OTPC_S 561 582 #define CLK_OTPC_S 562 583 #define PCLK_WDT_S 563 584 #define TCLK_WDT_S 564 585 #define PCLK_HDCP0_TRNG 565 586 #define PCLK_HDCP1_TRNG 566 587 #define HCLK_HDCP_KEY0 567 588 #define HCLK_HDCP_KEY1 568 589 #define PCLK_EDP_S 569 590 #define ACLK_KLAD 570 591 592 #endif 593
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