1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ 2 /* 3 * Sunplus SP7021 dt-bindings Pinctrl header file 4 * Copyright (C) Sunplus Tech/Tibbo Tech. 5 * Author: Dvorkin Dmitry <dvorkin@tibbo.com> 6 */ 7 8 #ifndef __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 9 #define __DT_BINDINGS_PINCTRL_SPPCTL_SP7021_H__ 10 11 #include <dt-bindings/pinctrl/sppctl.h> 12 13 /* 14 * Please don't change the order of the following defines. 15 * They are based on order of 'hardware' control register 16 * defined in MOON2 ~ MOON3 registers. 17 */ 18 #define MUXF_GPIO 0 19 #define MUXF_IOP 1 20 #define MUXF_L2SW_CLK_OUT 2 21 #define MUXF_L2SW_MAC_SMI_MDC 3 22 #define MUXF_L2SW_LED_FLASH0 4 23 #define MUXF_L2SW_LED_FLASH1 5 24 #define MUXF_L2SW_LED_ON0 6 25 #define MUXF_L2SW_LED_ON1 7 26 #define MUXF_L2SW_MAC_SMI_MDIO 8 27 #define MUXF_L2SW_P0_MAC_RMII_TXEN 9 28 #define MUXF_L2SW_P0_MAC_RMII_TXD0 10 29 #define MUXF_L2SW_P0_MAC_RMII_TXD1 11 30 #define MUXF_L2SW_P0_MAC_RMII_CRSDV 12 31 #define MUXF_L2SW_P0_MAC_RMII_RXD0 13 32 #define MUXF_L2SW_P0_MAC_RMII_RXD1 14 33 #define MUXF_L2SW_P0_MAC_RMII_RXER 15 34 #define MUXF_L2SW_P1_MAC_RMII_TXEN 16 35 #define MUXF_L2SW_P1_MAC_RMII_TXD0 17 36 #define MUXF_L2SW_P1_MAC_RMII_TXD1 18 37 #define MUXF_L2SW_P1_MAC_RMII_CRSDV 19 38 #define MUXF_L2SW_P1_MAC_RMII_RXD0 20 39 #define MUXF_L2SW_P1_MAC_RMII_RXD1 21 40 #define MUXF_L2SW_P1_MAC_RMII_RXER 22 41 #define MUXF_DAISY_MODE 23 42 #define MUXF_SDIO_CLK 24 43 #define MUXF_SDIO_CMD 25 44 #define MUXF_SDIO_D0 26 45 #define MUXF_SDIO_D1 27 46 #define MUXF_SDIO_D2 28 47 #define MUXF_SDIO_D3 29 48 #define MUXF_PWM0 30 49 #define MUXF_PWM1 31 50 #define MUXF_PWM2 32 51 #define MUXF_PWM3 33 52 #define MUXF_PWM4 34 53 #define MUXF_PWM5 35 54 #define MUXF_PWM6 36 55 #define MUXF_PWM7 37 56 #define MUXF_ICM0_D 38 57 #define MUXF_ICM1_D 39 58 #define MUXF_ICM2_D 40 59 #define MUXF_ICM3_D 41 60 #define MUXF_ICM0_CLK 42 61 #define MUXF_ICM1_CLK 43 62 #define MUXF_ICM2_CLK 44 63 #define MUXF_ICM3_CLK 45 64 #define MUXF_SPIM0_INT 46 65 #define MUXF_SPIM0_CLK 47 66 #define MUXF_SPIM0_EN 48 67 #define MUXF_SPIM0_DO 49 68 #define MUXF_SPIM0_DI 50 69 #define MUXF_SPIM1_INT 51 70 #define MUXF_SPIM1_CLK 52 71 #define MUXF_SPIM1_EN 53 72 #define MUXF_SPIM1_DO 54 73 #define MUXF_SPIM1_DI 55 74 #define MUXF_SPIM2_INT 56 75 #define MUXF_SPIM2_CLK 57 76 #define MUXF_SPIM2_EN 58 77 #define MUXF_SPIM2_DO 59 78 #define MUXF_SPIM2_DI 60 79 #define MUXF_SPIM3_INT 61 80 #define MUXF_SPIM3_CLK 62 81 #define MUXF_SPIM3_EN 63 82 #define MUXF_SPIM3_DO 64 83 #define MUXF_SPIM3_DI 65 84 #define MUXF_SPI0S_INT 66 85 #define MUXF_SPI0S_CLK 67 86 #define MUXF_SPI0S_EN 68 87 #define MUXF_SPI0S_DO 69 88 #define MUXF_SPI0S_DI 70 89 #define MUXF_SPI1S_INT 71 90 #define MUXF_SPI1S_CLK 72 91 #define MUXF_SPI1S_EN 73 92 #define MUXF_SPI1S_DO 74 93 #define MUXF_SPI1S_DI 75 94 #define MUXF_SPI2S_INT 76 95 #define MUXF_SPI2S_CLK 77 96 #define MUXF_SPI2S_EN 78 97 #define MUXF_SPI2S_DO 79 98 #define MUXF_SPI2S_DI 80 99 #define MUXF_SPI3S_INT 81 100 #define MUXF_SPI3S_CLK 82 101 #define MUXF_SPI3S_EN 83 102 #define MUXF_SPI3S_DO 84 103 #define MUXF_SPI3S_DI 85 104 #define MUXF_I2CM0_CLK 86 105 #define MUXF_I2CM0_DAT 87 106 #define MUXF_I2CM1_CLK 88 107 #define MUXF_I2CM1_DAT 89 108 #define MUXF_I2CM2_CLK 90 109 #define MUXF_I2CM2_DAT 91 110 #define MUXF_I2CM3_CLK 92 111 #define MUXF_I2CM3_DAT 93 112 #define MUXF_UA1_TX 94 113 #define MUXF_UA1_RX 95 114 #define MUXF_UA1_CTS 96 115 #define MUXF_UA1_RTS 97 116 #define MUXF_UA2_TX 98 117 #define MUXF_UA2_RX 99 118 #define MUXF_UA2_CTS 100 119 #define MUXF_UA2_RTS 101 120 #define MUXF_UA3_TX 102 121 #define MUXF_UA3_RX 103 122 #define MUXF_UA3_CTS 104 123 #define MUXF_UA3_RTS 105 124 #define MUXF_UA4_TX 106 125 #define MUXF_UA4_RX 107 126 #define MUXF_UA4_CTS 108 127 #define MUXF_UA4_RTS 109 128 #define MUXF_TIMER0_INT 110 129 #define MUXF_TIMER1_INT 111 130 #define MUXF_TIMER2_INT 112 131 #define MUXF_TIMER3_INT 113 132 #define MUXF_GPIO_INT0 114 133 #define MUXF_GPIO_INT1 115 134 #define MUXF_GPIO_INT2 116 135 #define MUXF_GPIO_INT3 117 136 #define MUXF_GPIO_INT4 118 137 #define MUXF_GPIO_INT5 119 138 #define MUXF_GPIO_INT6 120 139 #define MUXF_GPIO_INT7 121 140 141 /* 142 * Please don't change the order of the following defines. 143 * They are based on order of items in array 'sppctl_list_funcs' 144 * in Sunplus pinctrl driver. 145 */ 146 #define GROP_SPI_FLASH 122 147 #define GROP_SPI_FLASH_4BIT 123 148 #define GROP_SPI_NAND 124 149 #define GROP_CARD0_EMMC 125 150 #define GROP_SD_CARD 126 151 #define GROP_UA0 127 152 #define GROP_ACHIP_DEBUG 128 153 #define GROP_ACHIP_UA2AXI 129 154 #define GROP_FPGA_IFX 130 155 #define GROP_HDMI_TX 131 156 #define GROP_AUD_EXT_ADC_IFX0 132 157 #define GROP_AUD_EXT_DAC_IFX0 133 158 #define GROP_SPDIF_RX 134 159 #define GROP_SPDIF_TX 135 160 #define GROP_TDMTX_IFX0 136 161 #define GROP_TDMRX_IFX0 137 162 #define GROP_PDMRX_IFX0 138 163 #define GROP_PCM_IEC_TX 139 164 #define GROP_LCDIF 140 165 #define GROP_DVD_DSP_DEBUG 141 166 #define GROP_I2C_DEBUG 142 167 #define GROP_I2C_SLAVE 143 168 #define GROP_WAKEUP 144 169 #define GROP_UART2AXI 145 170 #define GROP_USB0_I2C 146 171 #define GROP_USB1_I2C 147 172 #define GROP_USB0_OTG 148 173 #define GROP_USB1_OTG 149 174 #define GROP_UPHY0_DEBUG 150 175 #define GROP_UPHY1_DEBUG 151 176 #define GROP_UPHY0_EXT 152 177 #define GROP_PROBE_PORT 153 178 179 #endif 180
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