1 /* SPDX-License-Identifier: GPL-2.0 */
2 #ifndef LINUX_BCMA_DRIVER_GMAC_CMN_H_
3 #define LINUX_BCMA_DRIVER_GMAC_CMN_H_
4
5 #include <linux/types.h>
6
7 #define BCMA_GMAC_CMN_STAG0 0x000
8 #define BCMA_GMAC_CMN_STAG1 0x004
9 #define BCMA_GMAC_CMN_STAG2 0x008
10 #define BCMA_GMAC_CMN_STAG3 0x00C
11 #define BCMA_GMAC_CMN_PARSER_CTL 0x020
12 #define BCMA_GMAC_CMN_MIB_MAX_LEN 0x024
13 #define BCMA_GMAC_CMN_PHY_ACCESS 0x100
14 #define BCMA_GMAC_CMN_PA_DATA_MASK 0x0000ffff
15 #define BCMA_GMAC_CMN_PA_ADDR_MASK 0x001f0000
16 #define BCMA_GMAC_CMN_PA_ADDR_SHIFT 16
17 #define BCMA_GMAC_CMN_PA_REG_MASK 0x1f000000
18 #define BCMA_GMAC_CMN_PA_REG_SHIFT 24
19 #define BCMA_GMAC_CMN_PA_WRITE 0x20000000
20 #define BCMA_GMAC_CMN_PA_START 0x40000000
21 #define BCMA_GMAC_CMN_PHY_CTL 0x104
22 #define BCMA_GMAC_CMN_PC_EPA_MASK 0x0000001f
23 #define BCMA_GMAC_CMN_PC_MCT_MASK 0x007f0000
24 #define BCMA_GMAC_CMN_PC_MCT_SHIFT 16
25 #define BCMA_GMAC_CMN_PC_MTE 0x00800000
26 #define BCMA_GMAC_CMN_GMAC0_RGMII_CTL 0x110
27 #define BCMA_GMAC_CMN_CFP_ACCESS 0x200
28 #define BCMA_GMAC_CMN_CFP_TCAM_DATA0 0x210
29 #define BCMA_GMAC_CMN_CFP_TCAM_DATA1 0x214
30 #define BCMA_GMAC_CMN_CFP_TCAM_DATA2 0x218
31 #define BCMA_GMAC_CMN_CFP_TCAM_DATA3 0x21C
32 #define BCMA_GMAC_CMN_CFP_TCAM_DATA4 0x220
33 #define BCMA_GMAC_CMN_CFP_TCAM_DATA5 0x224
34 #define BCMA_GMAC_CMN_CFP_TCAM_DATA6 0x228
35 #define BCMA_GMAC_CMN_CFP_TCAM_DATA7 0x22C
36 #define BCMA_GMAC_CMN_CFP_TCAM_MASK0 0x230
37 #define BCMA_GMAC_CMN_CFP_TCAM_MASK1 0x234
38 #define BCMA_GMAC_CMN_CFP_TCAM_MASK2 0x238
39 #define BCMA_GMAC_CMN_CFP_TCAM_MASK3 0x23C
40 #define BCMA_GMAC_CMN_CFP_TCAM_MASK4 0x240
41 #define BCMA_GMAC_CMN_CFP_TCAM_MASK5 0x244
42 #define BCMA_GMAC_CMN_CFP_TCAM_MASK6 0x248
43 #define BCMA_GMAC_CMN_CFP_TCAM_MASK7 0x24C
44 #define BCMA_GMAC_CMN_CFP_ACTION_DATA 0x250
45 #define BCMA_GMAC_CMN_TCAM_BIST_CTL 0x2A0
46 #define BCMA_GMAC_CMN_TCAM_BIST_STATUS 0x2A4
47 #define BCMA_GMAC_CMN_TCAM_CMP_STATUS 0x2A8
48 #define BCMA_GMAC_CMN_TCAM_DISABLE 0x2AC
49 #define BCMA_GMAC_CMN_TCAM_TEST_CTL 0x2F0
50 #define BCMA_GMAC_CMN_UDF_0_A3_A0 0x300
51 #define BCMA_GMAC_CMN_UDF_0_A7_A4 0x304
52 #define BCMA_GMAC_CMN_UDF_0_A8 0x308
53 #define BCMA_GMAC_CMN_UDF_1_A3_A0 0x310
54 #define BCMA_GMAC_CMN_UDF_1_A7_A4 0x314
55 #define BCMA_GMAC_CMN_UDF_1_A8 0x318
56 #define BCMA_GMAC_CMN_UDF_2_A3_A0 0x320
57 #define BCMA_GMAC_CMN_UDF_2_A7_A4 0x324
58 #define BCMA_GMAC_CMN_UDF_2_A8 0x328
59 #define BCMA_GMAC_CMN_UDF_0_B3_B0 0x330
60 #define BCMA_GMAC_CMN_UDF_0_B7_B4 0x334
61 #define BCMA_GMAC_CMN_UDF_0_B8 0x338
62 #define BCMA_GMAC_CMN_UDF_1_B3_B0 0x340
63 #define BCMA_GMAC_CMN_UDF_1_B7_B4 0x344
64 #define BCMA_GMAC_CMN_UDF_1_B8 0x348
65 #define BCMA_GMAC_CMN_UDF_2_B3_B0 0x350
66 #define BCMA_GMAC_CMN_UDF_2_B7_B4 0x354
67 #define BCMA_GMAC_CMN_UDF_2_B8 0x358
68 #define BCMA_GMAC_CMN_UDF_0_C3_C0 0x360
69 #define BCMA_GMAC_CMN_UDF_0_C7_C4 0x364
70 #define BCMA_GMAC_CMN_UDF_0_C8 0x368
71 #define BCMA_GMAC_CMN_UDF_1_C3_C0 0x370
72 #define BCMA_GMAC_CMN_UDF_1_C7_C4 0x374
73 #define BCMA_GMAC_CMN_UDF_1_C8 0x378
74 #define BCMA_GMAC_CMN_UDF_2_C3_C0 0x380
75 #define BCMA_GMAC_CMN_UDF_2_C7_C4 0x384
76 #define BCMA_GMAC_CMN_UDF_2_C8 0x388
77 #define BCMA_GMAC_CMN_UDF_0_D3_D0 0x390
78 #define BCMA_GMAC_CMN_UDF_0_D7_D4 0x394
79 #define BCMA_GMAC_CMN_UDF_0_D11_D8 0x394
80
81 struct bcma_drv_gmac_cmn {
82 struct bcma_device *core;
83
84 /* Drivers accessing BCMA_GMAC_CMN_PHY_ACCESS and
85 * BCMA_GMAC_CMN_PHY_CTL need to take that mutex first. */
86 struct mutex phy_mutex;
87 };
88
89 /* Register access */
90 #define gmac_cmn_read16(gc, offset) bcma_read16((gc)->core, offset)
91 #define gmac_cmn_read32(gc, offset) bcma_read32((gc)->core, offset)
92 #define gmac_cmn_write16(gc, offset, val) bcma_write16((gc)->core, offset, val)
93 #define gmac_cmn_write32(gc, offset, val) bcma_write32((gc)->core, offset, val)
94
95 #endif /* LINUX_BCMA_DRIVER_GMAC_CMN_H_ */
96
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