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TOMOYO Linux Cross Reference
Linux/include/linux/cs5535.h

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  1 /* SPDX-License-Identifier: GPL-2.0-only */
  2 /*
  3  * AMD CS5535/CS5536 definitions
  4  * Copyright (C) 2006  Advanced Micro Devices, Inc.
  5  * Copyright (C) 2009  Andres Salomon <dilinger@collabora.co.uk>
  6  */
  7 
  8 #ifndef _CS5535_H
  9 #define _CS5535_H
 10 
 11 #include <asm/msr.h>
 12 
 13 /* MSRs */
 14 #define MSR_GLIU_P2D_RO0        0x10000029
 15 
 16 #define MSR_LX_GLD_MSR_CONFIG   0x48002001
 17 #define MSR_LX_MSR_PADSEL       0x48002011      /* NOT 0x48000011; the data
 18                                                  * sheet has the wrong value */
 19 #define MSR_GLCP_SYS_RSTPLL     0x4C000014
 20 #define MSR_GLCP_DOTPLL         0x4C000015
 21 
 22 #define MSR_LBAR_SMB            0x5140000B
 23 #define MSR_LBAR_GPIO           0x5140000C
 24 #define MSR_LBAR_MFGPT          0x5140000D
 25 #define MSR_LBAR_ACPI           0x5140000E
 26 #define MSR_LBAR_PMS            0x5140000F
 27 
 28 #define MSR_DIVIL_SOFT_RESET    0x51400017
 29 
 30 #define MSR_PIC_YSEL_LOW        0x51400020
 31 #define MSR_PIC_YSEL_HIGH       0x51400021
 32 #define MSR_PIC_ZSEL_LOW        0x51400022
 33 #define MSR_PIC_ZSEL_HIGH       0x51400023
 34 #define MSR_PIC_IRQM_LPC        0x51400025
 35 
 36 #define MSR_MFGPT_IRQ           0x51400028
 37 #define MSR_MFGPT_NR            0x51400029
 38 #define MSR_MFGPT_SETUP         0x5140002B
 39 
 40 #define MSR_RTC_DOMA_OFFSET     0x51400055
 41 #define MSR_RTC_MONA_OFFSET     0x51400056
 42 #define MSR_RTC_CEN_OFFSET      0x51400057
 43 
 44 #define MSR_LX_SPARE_MSR        0x80000011      /* DC-specific */
 45 
 46 #define MSR_GX_GLD_MSR_CONFIG   0xC0002001
 47 #define MSR_GX_MSR_PADSEL       0xC0002011
 48 
 49 static inline int cs5535_pic_unreqz_select_high(unsigned int group,
 50                                                 unsigned int irq)
 51 {
 52         uint32_t lo, hi;
 53 
 54         rdmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
 55         lo &= ~(0xF << (group * 4));
 56         lo |= (irq & 0xF) << (group * 4);
 57         wrmsr(MSR_PIC_ZSEL_HIGH, lo, hi);
 58         return 0;
 59 }
 60 
 61 /* PIC registers */
 62 #define CS5536_PIC_INT_SEL1     0x4d0
 63 #define CS5536_PIC_INT_SEL2     0x4d1
 64 
 65 /* resource sizes */
 66 #define LBAR_GPIO_SIZE          0xFF
 67 #define LBAR_MFGPT_SIZE         0x40
 68 #define LBAR_ACPI_SIZE          0x40
 69 #define LBAR_PMS_SIZE           0x80
 70 
 71 /*
 72  * PMC registers (PMS block)
 73  * It is only safe to access these registers as dword accesses.
 74  * See CS5536 Specification Update erratas 17 & 18
 75  */
 76 #define CS5536_PM_SCLK          0x10
 77 #define CS5536_PM_IN_SLPCTL     0x20
 78 #define CS5536_PM_WKXD          0x34
 79 #define CS5536_PM_WKD           0x30
 80 #define CS5536_PM_SSC           0x54
 81 
 82 /*
 83  * PM registers (ACPI block)
 84  * It is only safe to access these registers as dword accesses.
 85  * See CS5536 Specification Update erratas 17 & 18
 86  */
 87 #define CS5536_PM1_STS          0x00
 88 #define CS5536_PM1_EN           0x02
 89 #define CS5536_PM1_CNT          0x08
 90 #define CS5536_PM_GPE0_STS      0x18
 91 #define CS5536_PM_GPE0_EN       0x1c
 92 
 93 /* CS5536_PM1_STS bits */
 94 #define CS5536_WAK_FLAG         (1 << 15)
 95 #define CS5536_RTC_FLAG         (1 << 10)
 96 #define CS5536_PWRBTN_FLAG      (1 << 8)
 97 
 98 /* CS5536_PM1_EN bits */
 99 #define CS5536_PM_PWRBTN        (1 << 8)
100 #define CS5536_PM_RTC           (1 << 10)
101 
102 /* CS5536_PM_GPE0_STS bits */
103 #define CS5536_GPIOM7_PME_FLAG  (1 << 31)
104 #define CS5536_GPIOM6_PME_FLAG  (1 << 30)
105 
106 /* CS5536_PM_GPE0_EN bits */
107 #define CS5536_GPIOM7_PME_EN    (1 << 31)
108 #define CS5536_GPIOM6_PME_EN    (1 << 30)
109 
110 /* VSA2 magic values */
111 #define VSA_VRC_INDEX           0xAC1C
112 #define VSA_VRC_DATA            0xAC1E
113 #define VSA_VR_UNLOCK           0xFC53  /* unlock virtual register */
114 #define VSA_VR_SIGNATURE        0x0003
115 #define VSA_VR_MEM_SIZE         0x0200
116 #define AMD_VSA_SIG             0x4132  /* signature is ascii 'VSA2' */
117 #define GSW_VSA_SIG             0x534d  /* General Software signature */
118 
119 #include <linux/io.h>
120 
121 static inline int cs5535_has_vsa2(void)
122 {
123         static int has_vsa2 = -1;
124 
125         if (has_vsa2 == -1) {
126                 uint16_t val;
127 
128                 /*
129                  * The VSA has virtual registers that we can query for a
130                  * signature.
131                  */
132                 outw(VSA_VR_UNLOCK, VSA_VRC_INDEX);
133                 outw(VSA_VR_SIGNATURE, VSA_VRC_INDEX);
134 
135                 val = inw(VSA_VRC_DATA);
136                 has_vsa2 = (val == AMD_VSA_SIG || val == GSW_VSA_SIG);
137         }
138 
139         return has_vsa2;
140 }
141 
142 /* GPIOs */
143 #define GPIO_OUTPUT_VAL         0x00
144 #define GPIO_OUTPUT_ENABLE      0x04
145 #define GPIO_OUTPUT_OPEN_DRAIN  0x08
146 #define GPIO_OUTPUT_INVERT      0x0C
147 #define GPIO_OUTPUT_AUX1        0x10
148 #define GPIO_OUTPUT_AUX2        0x14
149 #define GPIO_PULL_UP            0x18
150 #define GPIO_PULL_DOWN          0x1C
151 #define GPIO_INPUT_ENABLE       0x20
152 #define GPIO_INPUT_INVERT       0x24
153 #define GPIO_INPUT_FILTER       0x28
154 #define GPIO_INPUT_EVENT_COUNT  0x2C
155 #define GPIO_READ_BACK          0x30
156 #define GPIO_INPUT_AUX1         0x34
157 #define GPIO_EVENTS_ENABLE      0x38
158 #define GPIO_LOCK_ENABLE        0x3C
159 #define GPIO_POSITIVE_EDGE_EN   0x40
160 #define GPIO_NEGATIVE_EDGE_EN   0x44
161 #define GPIO_POSITIVE_EDGE_STS  0x48
162 #define GPIO_NEGATIVE_EDGE_STS  0x4C
163 
164 #define GPIO_FLTR7_AMOUNT       0xD8
165 
166 #define GPIO_MAP_X              0xE0
167 #define GPIO_MAP_Y              0xE4
168 #define GPIO_MAP_Z              0xE8
169 #define GPIO_MAP_W              0xEC
170 
171 #define GPIO_FE7_SEL            0xF7
172 
173 void cs5535_gpio_set(unsigned offset, unsigned int reg);
174 void cs5535_gpio_clear(unsigned offset, unsigned int reg);
175 int cs5535_gpio_isset(unsigned offset, unsigned int reg);
176 int cs5535_gpio_set_irq(unsigned group, unsigned irq);
177 void cs5535_gpio_setup_event(unsigned offset, int pair, int pme);
178 
179 /* MFGPTs */
180 
181 #define MFGPT_MAX_TIMERS        8
182 #define MFGPT_TIMER_ANY         (-1)
183 
184 #define MFGPT_DOMAIN_WORKING    1
185 #define MFGPT_DOMAIN_STANDBY    2
186 #define MFGPT_DOMAIN_ANY        (MFGPT_DOMAIN_WORKING | MFGPT_DOMAIN_STANDBY)
187 
188 #define MFGPT_CMP1              0
189 #define MFGPT_CMP2              1
190 
191 #define MFGPT_EVENT_IRQ         0
192 #define MFGPT_EVENT_NMI         1
193 #define MFGPT_EVENT_RESET       3
194 
195 #define MFGPT_REG_CMP1          0
196 #define MFGPT_REG_CMP2          2
197 #define MFGPT_REG_COUNTER       4
198 #define MFGPT_REG_SETUP         6
199 
200 #define MFGPT_SETUP_CNTEN       (1 << 15)
201 #define MFGPT_SETUP_CMP2        (1 << 14)
202 #define MFGPT_SETUP_CMP1        (1 << 13)
203 #define MFGPT_SETUP_SETUP       (1 << 12)
204 #define MFGPT_SETUP_STOPEN      (1 << 11)
205 #define MFGPT_SETUP_EXTEN       (1 << 10)
206 #define MFGPT_SETUP_REVEN       (1 << 5)
207 #define MFGPT_SETUP_CLKSEL      (1 << 4)
208 
209 struct cs5535_mfgpt_timer;
210 
211 extern uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer,
212                 uint16_t reg);
213 extern void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
214                 uint16_t value);
215 
216 extern int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
217                 int event, int enable);
218 extern int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp,
219                 int *irq, int enable);
220 extern struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer,
221                 int domain);
222 extern void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer);
223 
224 static inline int cs5535_mfgpt_setup_irq(struct cs5535_mfgpt_timer *timer,
225                 int cmp, int *irq)
226 {
227         return cs5535_mfgpt_set_irq(timer, cmp, irq, 1);
228 }
229 
230 static inline int cs5535_mfgpt_release_irq(struct cs5535_mfgpt_timer *timer,
231                 int cmp, int *irq)
232 {
233         return cs5535_mfgpt_set_irq(timer, cmp, irq, 0);
234 }
235 
236 #endif
237 

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