1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (c) 2020, Linaro Limited
4 */
5
6 #ifndef QCOM_GPI_DMA_H
7 #define QCOM_GPI_DMA_H
8
9 /**
10 * enum spi_transfer_cmd - spi transfer commands
11 */
12 enum spi_transfer_cmd {
13 SPI_TX = 1,
14 SPI_RX,
15 SPI_DUPLEX,
16 };
17
18 /**
19 * struct gpi_spi_config - spi config for peripheral
20 *
21 * @loopback_en: spi loopback enable when set
22 * @clock_pol_high: clock polarity
23 * @data_pol_high: data polarity
24 * @pack_en: process tx/rx buffers as packed
25 * @word_len: spi word length
26 * @clk_div: source clock divider
27 * @clk_src: serial clock
28 * @cmd: spi cmd
29 * @fragmentation: keep CS asserted at end of sequence
30 * @cs: chip select toggle
31 * @set_config: set peripheral config
32 * @rx_len: receive length for buffer
33 */
34 struct gpi_spi_config {
35 u8 set_config;
36 u8 loopback_en;
37 u8 clock_pol_high;
38 u8 data_pol_high;
39 u8 pack_en;
40 u8 word_len;
41 u8 fragmentation;
42 u8 cs;
43 u32 clk_div;
44 u32 clk_src;
45 enum spi_transfer_cmd cmd;
46 u32 rx_len;
47 };
48
49 enum i2c_op {
50 I2C_WRITE = 1,
51 I2C_READ,
52 };
53
54 /**
55 * struct gpi_i2c_config - i2c config for peripheral
56 *
57 * @pack_enable: process tx/rx buffers as packed
58 * @cycle_count: clock cycles to be sent
59 * @high_count: high period of clock
60 * @low_count: low period of clock
61 * @clk_div: source clock divider
62 * @addr: i2c bus address
63 * @stretch: stretch the clock at eot
64 * @set_config: set peripheral config
65 * @rx_len: receive length for buffer
66 * @op: i2c cmd
67 * @muli-msg: is part of multi i2c r-w msgs
68 */
69 struct gpi_i2c_config {
70 u8 set_config;
71 u8 pack_enable;
72 u8 cycle_count;
73 u8 high_count;
74 u8 low_count;
75 u8 addr;
76 u8 stretch;
77 u16 clk_div;
78 u32 rx_len;
79 enum i2c_op op;
80 bool multi_msg;
81 };
82
83 #endif /* QCOM_GPI_DMA_H */
84
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