1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Copyright (c) 2010-2015, 2018-2019 The Linux Foundation. All rights reserved.
3 * Copyright (C) 2015 Linaro Ltd.
4 */
5 #ifndef __QCOM_SCM_H
6 #define __QCOM_SCM_H
7
8 #include <linux/err.h>
9 #include <linux/types.h>
10 #include <linux/cpumask.h>
11
12 #include <dt-bindings/firmware/qcom,scm.h>
13
14 #define QCOM_SCM_VERSION(major, minor) (((major) << 16) | ((minor) & 0xFF))
15 #define QCOM_SCM_CPU_PWR_DOWN_L2_ON 0x0
16 #define QCOM_SCM_CPU_PWR_DOWN_L2_OFF 0x1
17 #define QCOM_SCM_HDCP_MAX_REQ_CNT 5
18
19 struct qcom_scm_hdcp_req {
20 u32 addr;
21 u32 val;
22 };
23
24 struct qcom_scm_vmperm {
25 int vmid;
26 int perm;
27 };
28
29 enum qcom_scm_ocmem_client {
30 QCOM_SCM_OCMEM_UNUSED_ID = 0x0,
31 QCOM_SCM_OCMEM_GRAPHICS_ID,
32 QCOM_SCM_OCMEM_VIDEO_ID,
33 QCOM_SCM_OCMEM_LP_AUDIO_ID,
34 QCOM_SCM_OCMEM_SENSORS_ID,
35 QCOM_SCM_OCMEM_OTHER_OS_ID,
36 QCOM_SCM_OCMEM_DEBUG_ID,
37 };
38
39 enum qcom_scm_sec_dev_id {
40 QCOM_SCM_MDSS_DEV_ID = 1,
41 QCOM_SCM_OCMEM_DEV_ID = 5,
42 QCOM_SCM_PCIE0_DEV_ID = 11,
43 QCOM_SCM_PCIE1_DEV_ID = 12,
44 QCOM_SCM_GFX_DEV_ID = 18,
45 QCOM_SCM_UFS_DEV_ID = 19,
46 QCOM_SCM_ICE_DEV_ID = 20,
47 };
48
49 enum qcom_scm_ice_cipher {
50 QCOM_SCM_ICE_CIPHER_AES_128_XTS = 0,
51 QCOM_SCM_ICE_CIPHER_AES_128_CBC = 1,
52 QCOM_SCM_ICE_CIPHER_AES_256_XTS = 3,
53 QCOM_SCM_ICE_CIPHER_AES_256_CBC = 4,
54 };
55
56 #define QCOM_SCM_PERM_READ 0x4
57 #define QCOM_SCM_PERM_WRITE 0x2
58 #define QCOM_SCM_PERM_EXEC 0x1
59 #define QCOM_SCM_PERM_RW (QCOM_SCM_PERM_READ | QCOM_SCM_PERM_WRITE)
60 #define QCOM_SCM_PERM_RWX (QCOM_SCM_PERM_RW | QCOM_SCM_PERM_EXEC)
61
62 bool qcom_scm_is_available(void);
63
64 int qcom_scm_set_cold_boot_addr(void *entry);
65 int qcom_scm_set_warm_boot_addr(void *entry);
66 void qcom_scm_cpu_power_down(u32 flags);
67 int qcom_scm_set_remote_state(u32 state, u32 id);
68
69 struct qcom_scm_pas_metadata {
70 void *ptr;
71 dma_addr_t phys;
72 ssize_t size;
73 };
74
75 int qcom_scm_pas_init_image(u32 peripheral, const void *metadata, size_t size,
76 struct qcom_scm_pas_metadata *ctx);
77 void qcom_scm_pas_metadata_release(struct qcom_scm_pas_metadata *ctx);
78 int qcom_scm_pas_mem_setup(u32 peripheral, phys_addr_t addr, phys_addr_t size);
79 int qcom_scm_pas_auth_and_reset(u32 peripheral);
80 int qcom_scm_pas_shutdown(u32 peripheral);
81 bool qcom_scm_pas_supported(u32 peripheral);
82
83 int qcom_scm_io_readl(phys_addr_t addr, unsigned int *val);
84 int qcom_scm_io_writel(phys_addr_t addr, unsigned int val);
85
86 bool qcom_scm_restore_sec_cfg_available(void);
87 int qcom_scm_restore_sec_cfg(u32 device_id, u32 spare);
88 int qcom_scm_iommu_secure_ptbl_size(u32 spare, size_t *size);
89 int qcom_scm_iommu_secure_ptbl_init(u64 addr, u32 size, u32 spare);
90 int qcom_scm_iommu_set_cp_pool_size(u32 spare, u32 size);
91 int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size,
92 u32 cp_nonpixel_start, u32 cp_nonpixel_size);
93 int qcom_scm_assign_mem(phys_addr_t mem_addr, size_t mem_sz, u64 *src,
94 const struct qcom_scm_vmperm *newvm,
95 unsigned int dest_cnt);
96
97 bool qcom_scm_ocmem_lock_available(void);
98 int qcom_scm_ocmem_lock(enum qcom_scm_ocmem_client id, u32 offset, u32 size,
99 u32 mode);
100 int qcom_scm_ocmem_unlock(enum qcom_scm_ocmem_client id, u32 offset, u32 size);
101
102 bool qcom_scm_ice_available(void);
103 int qcom_scm_ice_invalidate_key(u32 index);
104 int qcom_scm_ice_set_key(u32 index, const u8 *key, u32 key_size,
105 enum qcom_scm_ice_cipher cipher, u32 data_unit_size);
106
107 bool qcom_scm_hdcp_available(void);
108 int qcom_scm_hdcp_req(struct qcom_scm_hdcp_req *req, u32 req_cnt, u32 *resp);
109
110 int qcom_scm_iommu_set_pt_format(u32 sec_id, u32 ctx_num, u32 pt_fmt);
111 int qcom_scm_qsmmu500_wait_safe_toggle(bool en);
112
113 int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val,
114 u64 limit_node, u32 node_id, u64 version);
115 int qcom_scm_lmh_profile_change(u32 profile_id);
116 bool qcom_scm_lmh_dcvsh_available(void);
117
118 /*
119 * Request TZ to program set of access controlled registers necessary
120 * irrespective of any features
121 */
122 #define QCOM_SCM_GPU_ALWAYS_EN_REQ BIT(0)
123 /*
124 * Request TZ to program BCL id to access controlled register when BCL is
125 * enabled
126 */
127 #define QCOM_SCM_GPU_BCL_EN_REQ BIT(1)
128 /*
129 * Request TZ to program set of access controlled register for CLX feature
130 * when enabled
131 */
132 #define QCOM_SCM_GPU_CLX_EN_REQ BIT(2)
133 /*
134 * Request TZ to program tsense ids to access controlled registers for reading
135 * gpu temperature sensors
136 */
137 #define QCOM_SCM_GPU_TSENSE_EN_REQ BIT(3)
138
139 int qcom_scm_gpu_init_regs(u32 gpu_req);
140
141 int qcom_scm_shm_bridge_enable(void);
142 int qcom_scm_shm_bridge_create(struct device *dev, u64 pfn_and_ns_perm_flags,
143 u64 ipfn_and_s_perm_flags, u64 size_and_flags,
144 u64 ns_vmids, u64 *handle);
145 int qcom_scm_shm_bridge_delete(struct device *dev, u64 handle);
146
147 #ifdef CONFIG_QCOM_QSEECOM
148
149 int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id);
150 int qcom_scm_qseecom_app_send(u32 app_id, void *req, size_t req_size,
151 void *rsp, size_t rsp_size);
152
153 #else /* CONFIG_QCOM_QSEECOM */
154
155 static inline int qcom_scm_qseecom_app_get_id(const char *app_name, u32 *app_id)
156 {
157 return -EINVAL;
158 }
159
160 static inline int qcom_scm_qseecom_app_send(u32 app_id,
161 void *req, size_t req_size,
162 void *rsp, size_t rsp_size)
163 {
164 return -EINVAL;
165 }
166
167 #endif /* CONFIG_QCOM_QSEECOM */
168
169 #endif
170
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