1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Common library for ADIS16XXX devices
4 *
5 * Copyright 2012 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
7 */
8
9 #ifndef __IIO_ADIS_H__
10 #define __IIO_ADIS_H__
11
12 #include <linux/cleanup.h>
13 #include <linux/spi/spi.h>
14 #include <linux/interrupt.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/types.h>
17
18 #define ADIS_WRITE_REG(reg) ((0x80 | (reg)))
19 #define ADIS_READ_REG(reg) ((reg) & 0x7f)
20
21 #define ADIS_PAGE_SIZE 0x80
22 #define ADIS_REG_PAGE_ID 0x00
23
24 struct adis;
25 struct iio_dev_attr;
26
27 /**
28 * struct adis_timeouts - ADIS chip variant timeouts
29 * @reset_ms - Wait time after rst pin goes inactive
30 * @sw_reset_ms - Wait time after sw reset command
31 * @self_test_ms - Wait time after self test command
32 */
33 struct adis_timeout {
34 u16 reset_ms;
35 u16 sw_reset_ms;
36 u16 self_test_ms;
37 };
38
39 /**
40 * struct adis_data - ADIS chip variant specific data
41 * @read_delay: SPI delay for read operations in us
42 * @write_delay: SPI delay for write operations in us
43 * @cs_change_delay: SPI delay between CS changes in us
44 * @glob_cmd_reg: Register address of the GLOB_CMD register
45 * @msc_ctrl_reg: Register address of the MSC_CTRL register
46 * @diag_stat_reg: Register address of the DIAG_STAT register
47 * @prod_id_reg: Register address of the PROD_ID register
48 * @prod_id: Product ID code that should be expected when reading @prod_id_reg
49 * @self_test_mask: Bitmask of supported self-test operations
50 * @self_test_reg: Register address to request self test command
51 * @self_test_no_autoclear: True if device's self-test needs clear of ctrl reg
52 * @status_error_msgs: Array of error messages
53 * @status_error_mask: Bitmask of errors supported by the device
54 * @timeouts: Chip specific delays
55 * @enable_irq: Hook for ADIS devices that have a special IRQ enable/disable
56 * @unmasked_drdy: True for devices that cannot mask/unmask the data ready pin
57 * @has_paging: True if ADIS device has paged registers
58 * @burst_reg_cmd: Register command that triggers burst
59 * @burst_len: Burst size in the SPI RX buffer. If @burst_max_len is defined,
60 * this should be the minimum size supported by the device.
61 * @burst_max_len: Holds the maximum burst size when the device supports
62 * more than one burst mode with different sizes
63 * @burst_max_speed_hz: Maximum spi speed that can be used in burst mode
64 */
65 struct adis_data {
66 unsigned int read_delay;
67 unsigned int write_delay;
68 unsigned int cs_change_delay;
69
70 unsigned int glob_cmd_reg;
71 unsigned int msc_ctrl_reg;
72 unsigned int diag_stat_reg;
73 unsigned int prod_id_reg;
74
75 unsigned int prod_id;
76
77 unsigned int self_test_mask;
78 unsigned int self_test_reg;
79 bool self_test_no_autoclear;
80 const struct adis_timeout *timeouts;
81
82 const char * const *status_error_msgs;
83 unsigned int status_error_mask;
84
85 int (*enable_irq)(struct adis *adis, bool enable);
86 bool unmasked_drdy;
87
88 bool has_paging;
89 bool has_fifo;
90
91 unsigned int burst_reg_cmd;
92 unsigned int burst_len;
93 unsigned int burst_max_len;
94 unsigned int burst_max_speed_hz;
95 };
96
97 /**
98 * struct adis - ADIS device instance data
99 * @spi: Reference to SPI device which owns this ADIS IIO device
100 * @trig: IIO trigger object data
101 * @data: ADIS chip variant specific data
102 * @burst: ADIS burst transfer information
103 * @burst_extra_len: Burst extra length. Should only be used by devices that can
104 * dynamically change their burst mode length.
105 * @state_lock: Lock used by the device to protect state
106 * @msg: SPI message object
107 * @xfer: SPI transfer objects to be used for a @msg
108 * @current_page: Some ADIS devices have registers, this selects current page
109 * @irq_flag: IRQ handling flags as passed to request_irq()
110 * @buffer: Data buffer for information read from the device
111 * @tx: DMA safe TX buffer for SPI transfers
112 * @rx: DMA safe RX buffer for SPI transfers
113 */
114 struct adis {
115 struct spi_device *spi;
116 struct iio_trigger *trig;
117
118 const struct adis_data *data;
119 unsigned int burst_extra_len;
120 /**
121 * The state_lock is meant to be used during operations that require
122 * a sequence of SPI R/W in order to protect the SPI transfer
123 * information (fields 'xfer', 'msg' & 'current_page') between
124 * potential concurrent accesses.
125 * This lock is used by all "adis_{functions}" that have to read/write
126 * registers. These functions also have unlocked variants
127 * (see "__adis_{functions}"), which don't hold this lock.
128 * This allows users of the ADIS library to group SPI R/W into
129 * the drivers, but they also must manage this lock themselves.
130 */
131 struct mutex state_lock;
132 struct spi_message msg;
133 struct spi_transfer *xfer;
134 unsigned int current_page;
135 unsigned long irq_flag;
136 void *buffer;
137
138 u8 tx[10] __aligned(IIO_DMA_MINALIGN);
139 u8 rx[4];
140 };
141
142 int adis_init(struct adis *adis, struct iio_dev *indio_dev,
143 struct spi_device *spi, const struct adis_data *data);
144 int __adis_reset(struct adis *adis);
145
146 /**
147 * adis_reset() - Reset the device
148 * @adis: The adis device
149 *
150 * Returns 0 on success, a negative error code otherwise
151 */
152 static inline int adis_reset(struct adis *adis)
153 {
154 guard(mutex)(&adis->state_lock);
155 return __adis_reset(adis);
156 }
157
158 int __adis_write_reg(struct adis *adis, unsigned int reg,
159 unsigned int val, unsigned int size);
160 int __adis_read_reg(struct adis *adis, unsigned int reg,
161 unsigned int *val, unsigned int size);
162
163 /**
164 * __adis_write_reg_8() - Write single byte to a register (unlocked)
165 * @adis: The adis device
166 * @reg: The address of the register to be written
167 * @value: The value to write
168 */
169 static inline int __adis_write_reg_8(struct adis *adis, unsigned int reg,
170 u8 val)
171 {
172 return __adis_write_reg(adis, reg, val, 1);
173 }
174
175 /**
176 * __adis_write_reg_16() - Write 2 bytes to a pair of registers (unlocked)
177 * @adis: The adis device
178 * @reg: The address of the lower of the two registers
179 * @value: Value to be written
180 */
181 static inline int __adis_write_reg_16(struct adis *adis, unsigned int reg,
182 u16 val)
183 {
184 return __adis_write_reg(adis, reg, val, 2);
185 }
186
187 /**
188 * __adis_write_reg_32() - write 4 bytes to four registers (unlocked)
189 * @adis: The adis device
190 * @reg: The address of the lower of the four register
191 * @value: Value to be written
192 */
193 static inline int __adis_write_reg_32(struct adis *adis, unsigned int reg,
194 u32 val)
195 {
196 return __adis_write_reg(adis, reg, val, 4);
197 }
198
199 /**
200 * __adis_read_reg_16() - read 2 bytes from a 16-bit register (unlocked)
201 * @adis: The adis device
202 * @reg: The address of the lower of the two registers
203 * @val: The value read back from the device
204 */
205 static inline int __adis_read_reg_16(struct adis *adis, unsigned int reg,
206 u16 *val)
207 {
208 unsigned int tmp;
209 int ret;
210
211 ret = __adis_read_reg(adis, reg, &tmp, 2);
212 if (ret == 0)
213 *val = tmp;
214
215 return ret;
216 }
217
218 /**
219 * __adis_read_reg_32() - read 4 bytes from a 32-bit register (unlocked)
220 * @adis: The adis device
221 * @reg: The address of the lower of the two registers
222 * @val: The value read back from the device
223 */
224 static inline int __adis_read_reg_32(struct adis *adis, unsigned int reg,
225 u32 *val)
226 {
227 unsigned int tmp;
228 int ret;
229
230 ret = __adis_read_reg(adis, reg, &tmp, 4);
231 if (ret == 0)
232 *val = tmp;
233
234 return ret;
235 }
236
237 /**
238 * adis_write_reg() - write N bytes to register
239 * @adis: The adis device
240 * @reg: The address of the lower of the two registers
241 * @value: The value to write to device (up to 4 bytes)
242 * @size: The size of the @value (in bytes)
243 */
244 static inline int adis_write_reg(struct adis *adis, unsigned int reg,
245 unsigned int val, unsigned int size)
246 {
247 guard(mutex)(&adis->state_lock);
248 return __adis_write_reg(adis, reg, val, size);
249 }
250
251 /**
252 * adis_read_reg() - read N bytes from register
253 * @adis: The adis device
254 * @reg: The address of the lower of the two registers
255 * @val: The value read back from the device
256 * @size: The size of the @val buffer
257 */
258 static int adis_read_reg(struct adis *adis, unsigned int reg,
259 unsigned int *val, unsigned int size)
260 {
261 guard(mutex)(&adis->state_lock);
262 return __adis_read_reg(adis, reg, val, size);
263 }
264
265 /**
266 * adis_write_reg_8() - Write single byte to a register
267 * @adis: The adis device
268 * @reg: The address of the register to be written
269 * @value: The value to write
270 */
271 static inline int adis_write_reg_8(struct adis *adis, unsigned int reg,
272 u8 val)
273 {
274 return adis_write_reg(adis, reg, val, 1);
275 }
276
277 /**
278 * adis_write_reg_16() - Write 2 bytes to a pair of registers
279 * @adis: The adis device
280 * @reg: The address of the lower of the two registers
281 * @value: Value to be written
282 */
283 static inline int adis_write_reg_16(struct adis *adis, unsigned int reg,
284 u16 val)
285 {
286 return adis_write_reg(adis, reg, val, 2);
287 }
288
289 /**
290 * adis_write_reg_32() - write 4 bytes to four registers
291 * @adis: The adis device
292 * @reg: The address of the lower of the four register
293 * @value: Value to be written
294 */
295 static inline int adis_write_reg_32(struct adis *adis, unsigned int reg,
296 u32 val)
297 {
298 return adis_write_reg(adis, reg, val, 4);
299 }
300
301 /**
302 * adis_read_reg_16() - read 2 bytes from a 16-bit register
303 * @adis: The adis device
304 * @reg: The address of the lower of the two registers
305 * @val: The value read back from the device
306 */
307 static inline int adis_read_reg_16(struct adis *adis, unsigned int reg,
308 u16 *val)
309 {
310 unsigned int tmp;
311 int ret;
312
313 ret = adis_read_reg(adis, reg, &tmp, 2);
314 if (ret == 0)
315 *val = tmp;
316
317 return ret;
318 }
319
320 /**
321 * adis_read_reg_32() - read 4 bytes from a 32-bit register
322 * @adis: The adis device
323 * @reg: The address of the lower of the two registers
324 * @val: The value read back from the device
325 */
326 static inline int adis_read_reg_32(struct adis *adis, unsigned int reg,
327 u32 *val)
328 {
329 unsigned int tmp;
330 int ret;
331
332 ret = adis_read_reg(adis, reg, &tmp, 4);
333 if (ret == 0)
334 *val = tmp;
335
336 return ret;
337 }
338
339 int __adis_update_bits_base(struct adis *adis, unsigned int reg, const u32 mask,
340 const u32 val, u8 size);
341 /**
342 * adis_update_bits_base() - ADIS Update bits function - Locked version
343 * @adis: The adis device
344 * @reg: The address of the lower of the two registers
345 * @mask: Bitmask to change
346 * @val: Value to be written
347 * @size: Size of the register to update
348 *
349 * Updates the desired bits of @reg in accordance with @mask and @val.
350 */
351 static inline int adis_update_bits_base(struct adis *adis, unsigned int reg,
352 const u32 mask, const u32 val, u8 size)
353 {
354 guard(mutex)(&adis->state_lock);
355 return __adis_update_bits_base(adis, reg, mask, val, size);
356 }
357
358 /**
359 * adis_update_bits() - Wrapper macro for adis_update_bits_base - Locked version
360 * @adis: The adis device
361 * @reg: The address of the lower of the two registers
362 * @mask: Bitmask to change
363 * @val: Value to be written
364 *
365 * This macro evaluates the sizeof of @val at compile time and calls
366 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
367 * @val can lead to undesired behavior if the register to update is 16bit.
368 */
369 #define adis_update_bits(adis, reg, mask, val) ({ \
370 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
371 adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
372 })
373
374 /**
375 * adis_update_bits() - Wrapper macro for adis_update_bits_base
376 * @adis: The adis device
377 * @reg: The address of the lower of the two registers
378 * @mask: Bitmask to change
379 * @val: Value to be written
380 *
381 * This macro evaluates the sizeof of @val at compile time and calls
382 * adis_update_bits_base() accordingly. Be aware that using MACROS/DEFINES for
383 * @val can lead to undesired behavior if the register to update is 16bit.
384 */
385 #define __adis_update_bits(adis, reg, mask, val) ({ \
386 BUILD_BUG_ON(sizeof(val) != 2 && sizeof(val) != 4); \
387 __adis_update_bits_base(adis, reg, mask, val, sizeof(val)); \
388 })
389
390 int __adis_check_status(struct adis *adis);
391 int __adis_initial_startup(struct adis *adis);
392 int __adis_enable_irq(struct adis *adis, bool enable);
393
394 static inline int adis_enable_irq(struct adis *adis, bool enable)
395 {
396 guard(mutex)(&adis->state_lock);
397 return __adis_enable_irq(adis, enable);
398 }
399
400 static inline int adis_check_status(struct adis *adis)
401 {
402 guard(mutex)(&adis->state_lock);
403 return __adis_check_status(adis);
404 }
405
406 #define adis_dev_auto_lock(adis) guard(mutex)(&(adis)->state_lock)
407 #define adis_dev_auto_scoped_lock(adis) \
408 scoped_guard(mutex, &(adis)->state_lock)
409
410 int adis_single_conversion(struct iio_dev *indio_dev,
411 const struct iio_chan_spec *chan,
412 unsigned int error_mask, int *val);
413
414 #define ADIS_VOLTAGE_CHAN(addr, si, chan, name, info_all, bits) { \
415 .type = IIO_VOLTAGE, \
416 .indexed = 1, \
417 .channel = (chan), \
418 .extend_name = name, \
419 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
420 BIT(IIO_CHAN_INFO_SCALE), \
421 .info_mask_shared_by_all = info_all, \
422 .address = (addr), \
423 .scan_index = (si), \
424 .scan_type = { \
425 .sign = 'u', \
426 .realbits = (bits), \
427 .storagebits = 16, \
428 .endianness = IIO_BE, \
429 }, \
430 }
431
432 #define ADIS_SUPPLY_CHAN(addr, si, info_all, bits) \
433 ADIS_VOLTAGE_CHAN(addr, si, 0, "supply", info_all, bits)
434
435 #define ADIS_AUX_ADC_CHAN(addr, si, info_all, bits) \
436 ADIS_VOLTAGE_CHAN(addr, si, 1, NULL, info_all, bits)
437
438 #define ADIS_TEMP_CHAN(addr, si, info_all, bits) { \
439 .type = IIO_TEMP, \
440 .indexed = 1, \
441 .channel = 0, \
442 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
443 BIT(IIO_CHAN_INFO_SCALE) | \
444 BIT(IIO_CHAN_INFO_OFFSET), \
445 .info_mask_shared_by_all = info_all, \
446 .address = (addr), \
447 .scan_index = (si), \
448 .scan_type = { \
449 .sign = 'u', \
450 .realbits = (bits), \
451 .storagebits = 16, \
452 .endianness = IIO_BE, \
453 }, \
454 }
455
456 #define ADIS_MOD_CHAN(_type, mod, addr, si, info_sep, info_all, bits) { \
457 .type = (_type), \
458 .modified = 1, \
459 .channel2 = IIO_MOD_ ## mod, \
460 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
461 (info_sep), \
462 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
463 .info_mask_shared_by_all = info_all, \
464 .address = (addr), \
465 .scan_index = (si), \
466 .scan_type = { \
467 .sign = 's', \
468 .realbits = (bits), \
469 .storagebits = 16, \
470 .endianness = IIO_BE, \
471 }, \
472 }
473
474 #define ADIS_ACCEL_CHAN(mod, addr, si, info_sep, info_all, bits) \
475 ADIS_MOD_CHAN(IIO_ACCEL, mod, addr, si, info_sep, info_all, bits)
476
477 #define ADIS_GYRO_CHAN(mod, addr, si, info_sep, info_all, bits) \
478 ADIS_MOD_CHAN(IIO_ANGL_VEL, mod, addr, si, info_sep, info_all, bits)
479
480 #define ADIS_INCLI_CHAN(mod, addr, si, info_sep, info_all, bits) \
481 ADIS_MOD_CHAN(IIO_INCLI, mod, addr, si, info_sep, info_all, bits)
482
483 #define ADIS_ROT_CHAN(mod, addr, si, info_sep, info_all, bits) \
484 ADIS_MOD_CHAN(IIO_ROT, mod, addr, si, info_sep, info_all, bits)
485
486 #define devm_adis_setup_buffer_and_trigger(adis, indio_dev, trigger_handler) \
487 devm_adis_setup_buffer_and_trigger_with_attrs((adis), (indio_dev), \
488 (trigger_handler), NULL, \
489 NULL)
490
491 #ifdef CONFIG_IIO_ADIS_LIB_BUFFER
492
493 int
494 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
495 struct iio_dev *indio_dev,
496 irq_handler_t trigger_handler,
497 const struct iio_buffer_setup_ops *ops,
498 const struct iio_dev_attr **buffer_attrs);
499
500 int devm_adis_probe_trigger(struct adis *adis, struct iio_dev *indio_dev);
501
502 int adis_update_scan_mode(struct iio_dev *indio_dev,
503 const unsigned long *scan_mask);
504
505 #else /* CONFIG_IIO_BUFFER */
506
507 static inline int
508 devm_adis_setup_buffer_and_trigger_with_attrs(struct adis *adis,
509 struct iio_dev *indio_dev,
510 irq_handler_t trigger_handler,
511 const struct iio_buffer_setup_ops *ops,
512 const struct iio_dev_attr **buffer_attrs)
513 {
514 return 0;
515 }
516
517 static inline int devm_adis_probe_trigger(struct adis *adis,
518 struct iio_dev *indio_dev)
519 {
520 return 0;
521 }
522
523 #define adis_update_scan_mode NULL
524
525 #endif /* CONFIG_IIO_BUFFER */
526
527 #ifdef CONFIG_DEBUG_FS
528
529 int adis_debugfs_reg_access(struct iio_dev *indio_dev,
530 unsigned int reg, unsigned int writeval,
531 unsigned int *readval);
532
533 #else
534
535 #define adis_debugfs_reg_access NULL
536
537 #endif
538
539 #endif
540
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