1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * DaVinci Voice Codec Core Interface for TI platforms
4 *
5 * Copyright (C) 2010 Texas Instruments, Inc
6 *
7 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
8 */
9
10 #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
11 #define __LINUX_MFD_DAVINCI_VOICECODEC_H_
12
13 #include <linux/kernel.h>
14 #include <linux/platform_device.h>
15 #include <linux/mfd/core.h>
16 #include <linux/platform_data/edma.h>
17
18 struct regmap;
19
20 /*
21 * Register values.
22 */
23 #define DAVINCI_VC_PID 0x00
24 #define DAVINCI_VC_CTRL 0x04
25 #define DAVINCI_VC_INTEN 0x08
26 #define DAVINCI_VC_INTSTATUS 0x0c
27 #define DAVINCI_VC_INTCLR 0x10
28 #define DAVINCI_VC_EMUL_CTRL 0x14
29 #define DAVINCI_VC_RFIFO 0x20
30 #define DAVINCI_VC_WFIFO 0x24
31 #define DAVINCI_VC_FIFOSTAT 0x28
32 #define DAVINCI_VC_TST_CTRL 0x2C
33 #define DAVINCI_VC_REG05 0x94
34 #define DAVINCI_VC_REG09 0xA4
35 #define DAVINCI_VC_REG12 0xB0
36
37 /* DAVINCI_VC_CTRL bit fields */
38 #define DAVINCI_VC_CTRL_MASK 0x5500
39 #define DAVINCI_VC_CTRL_RSTADC BIT(0)
40 #define DAVINCI_VC_CTRL_RSTDAC BIT(1)
41 #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
42 #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
43 #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
44 #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
45 #define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
46 #define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
47 #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
48 #define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
49 #define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
50 #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
51
52 /* DAVINCI_VC_INT bit fields */
53 #define DAVINCI_VC_INT_MASK 0x3F
54 #define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
55 #define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
56 #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
57 #define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
58 #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
59 #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
60
61 /* DAVINCI_VC_REG05 bit fields */
62 #define DAVINCI_VC_REG05_PGA_GAIN 0x07
63
64 /* DAVINCI_VC_REG09 bit fields */
65 #define DAVINCI_VC_REG09_MUTE 0x40
66 #define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
67
68 /* DAVINCI_VC_REG12 bit fields */
69 #define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
70 #define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
71
72 #define DAVINCI_VC_CELLS 2
73
74 enum davinci_vc_cells {
75 DAVINCI_VC_VCIF_CELL,
76 DAVINCI_VC_CQ93VC_CELL,
77 };
78
79 struct davinci_vcif {
80 struct platform_device *pdev;
81 u32 dma_tx_channel;
82 u32 dma_rx_channel;
83 dma_addr_t dma_tx_addr;
84 dma_addr_t dma_rx_addr;
85 };
86
87 struct davinci_vc {
88 /* Device data */
89 struct device *dev;
90 struct platform_device *pdev;
91 struct clk *clk;
92
93 /* Memory resources */
94 void __iomem *base;
95 struct regmap *regmap;
96
97 /* MFD cells */
98 struct mfd_cell cells[DAVINCI_VC_CELLS];
99
100 /* Client devices */
101 struct davinci_vcif davinci_vcif;
102 };
103
104 #endif
105
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