1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Header file for Intel Broxton Whiskey Cove PMIC 4 * 5 * Copyright (C) 2015 Intel Corporation. All rights reserved. 6 */ 7 8 #ifndef __INTEL_BXTWC_H__ 9 #define __INTEL_BXTWC_H__ 10 11 /* BXT WC devices */ 12 #define BXTWC_DEVICE1_ADDR 0x4E 13 #define BXTWC_DEVICE2_ADDR 0x4F 14 #define BXTWC_DEVICE3_ADDR 0x5E 15 16 /* device1 Registers */ 17 #define BXTWC_CHIPID 0x4E00 18 #define BXTWC_CHIPVER 0x4E01 19 20 #define BXTWC_SCHGRIRQ0_ADDR 0x5E1A 21 #define BXTWC_CHGRCTRL0_ADDR 0x5E16 22 #define BXTWC_CHGRCTRL1_ADDR 0x5E17 23 #define BXTWC_CHGRCTRL2_ADDR 0x5E18 24 #define BXTWC_CHGRSTATUS_ADDR 0x5E19 25 #define BXTWC_THRMBATZONE_ADDR 0x4F22 26 27 #define BXTWC_USBPATH_ADDR 0x5E19 28 #define BXTWC_USBPHYCTRL_ADDR 0x5E07 29 #define BXTWC_USBIDCTRL_ADDR 0x5E05 30 #define BXTWC_USBIDEN_MASK 0x01 31 #define BXTWC_USBIDSTAT_ADDR 0x00FF 32 #define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29 33 34 #define BXTWC_DBGUSBBC1_ADDR 0x5FE0 35 #define BXTWC_DBGUSBBC2_ADDR 0x5FE1 36 #define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2 37 38 #define BXTWC_WAKESRC_ADDR 0x4E22 39 #define BXTWC_WAKESRC2_ADDR 0x4EE5 40 #define BXTWC_CHRTTADDR_ADDR 0x5E22 41 #define BXTWC_CHRTTDATA_ADDR 0x5E23 42 43 #define BXTWC_STHRMIRQ0_ADDR 0x4F19 44 #define WC_MTHRMIRQ1_ADDR 0x4E12 45 #define WC_STHRMIRQ1_ADDR 0x4F1A 46 #define WC_STHRMIRQ2_ADDR 0x4F1B 47 48 #define BXTWC_THRMZN0H_ADDR 0x4F44 49 #define BXTWC_THRMZN0L_ADDR 0x4F45 50 #define BXTWC_THRMZN1H_ADDR 0x4F46 51 #define BXTWC_THRMZN1L_ADDR 0x4F47 52 #define BXTWC_THRMZN2H_ADDR 0x4F48 53 #define BXTWC_THRMZN2L_ADDR 0x4F49 54 #define BXTWC_THRMZN3H_ADDR 0x4F4A 55 #define BXTWC_THRMZN3L_ADDR 0x4F4B 56 #define BXTWC_THRMZN4H_ADDR 0x4F4C 57 #define BXTWC_THRMZN4L_ADDR 0x4F4D 58 59 #endif 60
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