1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Functions to access MAX8907 power management chip.
4 *
5 * Copyright (C) 2010 Gyungoh Yoo <jack.yoo@maxim-ic.com>
6 * Copyright (C) 2012, NVIDIA CORPORATION. All rights reserved.
7 */
8
9 #ifndef __LINUX_MFD_MAX8907_H
10 #define __LINUX_MFD_MAX8907_H
11
12 #include <linux/mutex.h>
13 #include <linux/pm.h>
14
15 #define MAX8907_GEN_I2C_ADDR (0x78 >> 1)
16 #define MAX8907_ADC_I2C_ADDR (0x8e >> 1)
17 #define MAX8907_RTC_I2C_ADDR (0xd0 >> 1)
18
19 /* MAX8907 register map */
20 #define MAX8907_REG_SYSENSEL 0x00
21 #define MAX8907_REG_ON_OFF_IRQ1 0x01
22 #define MAX8907_REG_ON_OFF_IRQ1_MASK 0x02
23 #define MAX8907_REG_ON_OFF_STAT 0x03
24 #define MAX8907_REG_SDCTL1 0x04
25 #define MAX8907_REG_SDSEQCNT1 0x05
26 #define MAX8907_REG_SDV1 0x06
27 #define MAX8907_REG_SDCTL2 0x07
28 #define MAX8907_REG_SDSEQCNT2 0x08
29 #define MAX8907_REG_SDV2 0x09
30 #define MAX8907_REG_SDCTL3 0x0A
31 #define MAX8907_REG_SDSEQCNT3 0x0B
32 #define MAX8907_REG_SDV3 0x0C
33 #define MAX8907_REG_ON_OFF_IRQ2 0x0D
34 #define MAX8907_REG_ON_OFF_IRQ2_MASK 0x0E
35 #define MAX8907_REG_RESET_CNFG 0x0F
36 #define MAX8907_REG_LDOCTL16 0x10
37 #define MAX8907_REG_LDOSEQCNT16 0x11
38 #define MAX8907_REG_LDO16VOUT 0x12
39 #define MAX8907_REG_SDBYSEQCNT 0x13
40 #define MAX8907_REG_LDOCTL17 0x14
41 #define MAX8907_REG_LDOSEQCNT17 0x15
42 #define MAX8907_REG_LDO17VOUT 0x16
43 #define MAX8907_REG_LDOCTL1 0x18
44 #define MAX8907_REG_LDOSEQCNT1 0x19
45 #define MAX8907_REG_LDO1VOUT 0x1A
46 #define MAX8907_REG_LDOCTL2 0x1C
47 #define MAX8907_REG_LDOSEQCNT2 0x1D
48 #define MAX8907_REG_LDO2VOUT 0x1E
49 #define MAX8907_REG_LDOCTL3 0x20
50 #define MAX8907_REG_LDOSEQCNT3 0x21
51 #define MAX8907_REG_LDO3VOUT 0x22
52 #define MAX8907_REG_LDOCTL4 0x24
53 #define MAX8907_REG_LDOSEQCNT4 0x25
54 #define MAX8907_REG_LDO4VOUT 0x26
55 #define MAX8907_REG_LDOCTL5 0x28
56 #define MAX8907_REG_LDOSEQCNT5 0x29
57 #define MAX8907_REG_LDO5VOUT 0x2A
58 #define MAX8907_REG_LDOCTL6 0x2C
59 #define MAX8907_REG_LDOSEQCNT6 0x2D
60 #define MAX8907_REG_LDO6VOUT 0x2E
61 #define MAX8907_REG_LDOCTL7 0x30
62 #define MAX8907_REG_LDOSEQCNT7 0x31
63 #define MAX8907_REG_LDO7VOUT 0x32
64 #define MAX8907_REG_LDOCTL8 0x34
65 #define MAX8907_REG_LDOSEQCNT8 0x35
66 #define MAX8907_REG_LDO8VOUT 0x36
67 #define MAX8907_REG_LDOCTL9 0x38
68 #define MAX8907_REG_LDOSEQCNT9 0x39
69 #define MAX8907_REG_LDO9VOUT 0x3A
70 #define MAX8907_REG_LDOCTL10 0x3C
71 #define MAX8907_REG_LDOSEQCNT10 0x3D
72 #define MAX8907_REG_LDO10VOUT 0x3E
73 #define MAX8907_REG_LDOCTL11 0x40
74 #define MAX8907_REG_LDOSEQCNT11 0x41
75 #define MAX8907_REG_LDO11VOUT 0x42
76 #define MAX8907_REG_LDOCTL12 0x44
77 #define MAX8907_REG_LDOSEQCNT12 0x45
78 #define MAX8907_REG_LDO12VOUT 0x46
79 #define MAX8907_REG_LDOCTL13 0x48
80 #define MAX8907_REG_LDOSEQCNT13 0x49
81 #define MAX8907_REG_LDO13VOUT 0x4A
82 #define MAX8907_REG_LDOCTL14 0x4C
83 #define MAX8907_REG_LDOSEQCNT14 0x4D
84 #define MAX8907_REG_LDO14VOUT 0x4E
85 #define MAX8907_REG_LDOCTL15 0x50
86 #define MAX8907_REG_LDOSEQCNT15 0x51
87 #define MAX8907_REG_LDO15VOUT 0x52
88 #define MAX8907_REG_OUT5VEN 0x54
89 #define MAX8907_REG_OUT5VSEQ 0x55
90 #define MAX8907_REG_OUT33VEN 0x58
91 #define MAX8907_REG_OUT33VSEQ 0x59
92 #define MAX8907_REG_LDOCTL19 0x5C
93 #define MAX8907_REG_LDOSEQCNT19 0x5D
94 #define MAX8907_REG_LDO19VOUT 0x5E
95 #define MAX8907_REG_LBCNFG 0x60
96 #define MAX8907_REG_SEQ1CNFG 0x64
97 #define MAX8907_REG_SEQ2CNFG 0x65
98 #define MAX8907_REG_SEQ3CNFG 0x66
99 #define MAX8907_REG_SEQ4CNFG 0x67
100 #define MAX8907_REG_SEQ5CNFG 0x68
101 #define MAX8907_REG_SEQ6CNFG 0x69
102 #define MAX8907_REG_SEQ7CNFG 0x6A
103 #define MAX8907_REG_LDOCTL18 0x72
104 #define MAX8907_REG_LDOSEQCNT18 0x73
105 #define MAX8907_REG_LDO18VOUT 0x74
106 #define MAX8907_REG_BBAT_CNFG 0x78
107 #define MAX8907_REG_CHG_CNTL1 0x7C
108 #define MAX8907_REG_CHG_CNTL2 0x7D
109 #define MAX8907_REG_CHG_IRQ1 0x7E
110 #define MAX8907_REG_CHG_IRQ2 0x7F
111 #define MAX8907_REG_CHG_IRQ1_MASK 0x80
112 #define MAX8907_REG_CHG_IRQ2_MASK 0x81
113 #define MAX8907_REG_CHG_STAT 0x82
114 #define MAX8907_REG_WLED_MODE_CNTL 0x84
115 #define MAX8907_REG_ILED_CNTL 0x84
116 #define MAX8907_REG_II1RR 0x8E
117 #define MAX8907_REG_II2RR 0x8F
118 #define MAX8907_REG_LDOCTL20 0x9C
119 #define MAX8907_REG_LDOSEQCNT20 0x9D
120 #define MAX8907_REG_LDO20VOUT 0x9E
121
122 /* RTC register map */
123 #define MAX8907_REG_RTC_SEC 0x00
124 #define MAX8907_REG_RTC_MIN 0x01
125 #define MAX8907_REG_RTC_HOURS 0x02
126 #define MAX8907_REG_RTC_WEEKDAY 0x03
127 #define MAX8907_REG_RTC_DATE 0x04
128 #define MAX8907_REG_RTC_MONTH 0x05
129 #define MAX8907_REG_RTC_YEAR1 0x06
130 #define MAX8907_REG_RTC_YEAR2 0x07
131 #define MAX8907_REG_ALARM0_SEC 0x08
132 #define MAX8907_REG_ALARM0_MIN 0x09
133 #define MAX8907_REG_ALARM0_HOURS 0x0A
134 #define MAX8907_REG_ALARM0_WEEKDAY 0x0B
135 #define MAX8907_REG_ALARM0_DATE 0x0C
136 #define MAX8907_REG_ALARM0_MONTH 0x0D
137 #define MAX8907_REG_ALARM0_YEAR1 0x0E
138 #define MAX8907_REG_ALARM0_YEAR2 0x0F
139 #define MAX8907_REG_ALARM1_SEC 0x10
140 #define MAX8907_REG_ALARM1_MIN 0x11
141 #define MAX8907_REG_ALARM1_HOURS 0x12
142 #define MAX8907_REG_ALARM1_WEEKDAY 0x13
143 #define MAX8907_REG_ALARM1_DATE 0x14
144 #define MAX8907_REG_ALARM1_MONTH 0x15
145 #define MAX8907_REG_ALARM1_YEAR1 0x16
146 #define MAX8907_REG_ALARM1_YEAR2 0x17
147 #define MAX8907_REG_ALARM0_CNTL 0x18
148 #define MAX8907_REG_ALARM1_CNTL 0x19
149 #define MAX8907_REG_RTC_STATUS 0x1A
150 #define MAX8907_REG_RTC_CNTL 0x1B
151 #define MAX8907_REG_RTC_IRQ 0x1C
152 #define MAX8907_REG_RTC_IRQ_MASK 0x1D
153 #define MAX8907_REG_MPL_CNTL 0x1E
154
155 /* ADC and Touch Screen Controller register map */
156 #define MAX8907_CTL 0
157 #define MAX8907_SEQCNT 1
158 #define MAX8907_VOUT 2
159
160 /* mask bit fields */
161 #define MAX8907_MASK_LDO_SEQ 0x1C
162 #define MAX8907_MASK_LDO_EN 0x01
163 #define MAX8907_MASK_VBBATTCV 0x03
164 #define MAX8907_MASK_OUT5V_VINEN 0x10
165 #define MAX8907_MASK_OUT5V_ENSRC 0x0E
166 #define MAX8907_MASK_OUT5V_EN 0x01
167 #define MAX8907_MASK_POWER_OFF 0x40
168
169 /* Regulator IDs */
170 #define MAX8907_MBATT 0
171 #define MAX8907_SD1 1
172 #define MAX8907_SD2 2
173 #define MAX8907_SD3 3
174 #define MAX8907_LDO1 4
175 #define MAX8907_LDO2 5
176 #define MAX8907_LDO3 6
177 #define MAX8907_LDO4 7
178 #define MAX8907_LDO5 8
179 #define MAX8907_LDO6 9
180 #define MAX8907_LDO7 10
181 #define MAX8907_LDO8 11
182 #define MAX8907_LDO9 12
183 #define MAX8907_LDO10 13
184 #define MAX8907_LDO11 14
185 #define MAX8907_LDO12 15
186 #define MAX8907_LDO13 16
187 #define MAX8907_LDO14 17
188 #define MAX8907_LDO15 18
189 #define MAX8907_LDO16 19
190 #define MAX8907_LDO17 20
191 #define MAX8907_LDO18 21
192 #define MAX8907_LDO19 22
193 #define MAX8907_LDO20 23
194 #define MAX8907_OUT5V 24
195 #define MAX8907_OUT33V 25
196 #define MAX8907_BBAT 26
197 #define MAX8907_SDBY 27
198 #define MAX8907_VRTC 28
199 #define MAX8907_NUM_REGULATORS (MAX8907_VRTC + 1)
200
201 /* IRQ definitions */
202 enum {
203 MAX8907_IRQ_VCHG_DC_OVP = 0,
204 MAX8907_IRQ_VCHG_DC_F,
205 MAX8907_IRQ_VCHG_DC_R,
206 MAX8907_IRQ_VCHG_THM_OK_R,
207 MAX8907_IRQ_VCHG_THM_OK_F,
208 MAX8907_IRQ_VCHG_MBATTLOW_F,
209 MAX8907_IRQ_VCHG_MBATTLOW_R,
210 MAX8907_IRQ_VCHG_RST,
211 MAX8907_IRQ_VCHG_DONE,
212 MAX8907_IRQ_VCHG_TOPOFF,
213 MAX8907_IRQ_VCHG_TMR_FAULT,
214
215 MAX8907_IRQ_GPM_RSTIN = 0,
216 MAX8907_IRQ_GPM_MPL,
217 MAX8907_IRQ_GPM_SW_3SEC,
218 MAX8907_IRQ_GPM_EXTON_F,
219 MAX8907_IRQ_GPM_EXTON_R,
220 MAX8907_IRQ_GPM_SW_1SEC,
221 MAX8907_IRQ_GPM_SW_F,
222 MAX8907_IRQ_GPM_SW_R,
223 MAX8907_IRQ_GPM_SYSCKEN_F,
224 MAX8907_IRQ_GPM_SYSCKEN_R,
225
226 MAX8907_IRQ_RTC_ALARM1 = 0,
227 MAX8907_IRQ_RTC_ALARM0,
228 };
229
230 struct max8907_platform_data {
231 struct regulator_init_data *init_data[MAX8907_NUM_REGULATORS];
232 bool pm_off;
233 };
234
235 struct regmap_irq_chips_data;
236
237 struct max8907 {
238 struct device *dev;
239 struct mutex irq_lock;
240 struct i2c_client *i2c_gen;
241 struct i2c_client *i2c_rtc;
242 struct regmap *regmap_gen;
243 struct regmap *regmap_rtc;
244 struct regmap_irq_chip_data *irqc_chg;
245 struct regmap_irq_chip_data *irqc_on_off;
246 struct regmap_irq_chip_data *irqc_rtc;
247 };
248
249 #endif
250
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