1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (c) 2022 AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
4 */
5
6 #ifndef __MFD_MT6332_CORE_H__
7 #define __MFD_MT6332_CORE_H__
8
9 enum mt6332_irq_status_numbers {
10 MT6332_IRQ_STATUS_CHR_COMPLETE = 0,
11 MT6332_IRQ_STATUS_THERMAL_SD,
12 MT6332_IRQ_STATUS_THERMAL_REG_IN,
13 MT6332_IRQ_STATUS_THERMAL_REG_OUT,
14 MT6332_IRQ_STATUS_OTG_OC,
15 MT6332_IRQ_STATUS_CHR_OC,
16 MT6332_IRQ_STATUS_OTG_THERMAL,
17 MT6332_IRQ_STATUS_CHRIN_SHORT,
18 MT6332_IRQ_STATUS_DRVCDT_SHORT,
19 MT6332_IRQ_STATUS_PLUG_IN_FLASH,
20 MT6332_IRQ_STATUS_CHRWDT_FLAG,
21 MT6332_IRQ_STATUS_FLASH_EN_TIMEOUT,
22 MT6332_IRQ_STATUS_FLASH_VLED1_SHORT,
23 MT6332_IRQ_STATUS_FLASH_VLED1_OPEN = 13,
24 MT6332_IRQ_STATUS_OV = 16,
25 MT6332_IRQ_STATUS_BVALID_DET,
26 MT6332_IRQ_STATUS_VBATON_UNDET,
27 MT6332_IRQ_STATUS_CHR_PLUG_IN,
28 MT6332_IRQ_STATUS_CHR_PLUG_OUT,
29 MT6332_IRQ_STATUS_BC11_TIMEOUT,
30 MT6332_IRQ_STATUS_FLASH_VLED2_SHORT,
31 MT6332_IRQ_STATUS_FLASH_VLED2_OPEN = 23,
32 MT6332_IRQ_STATUS_THR_H = 32,
33 MT6332_IRQ_STATUS_THR_L,
34 MT6332_IRQ_STATUS_BAT_H,
35 MT6332_IRQ_STATUS_BAT_L,
36 MT6332_IRQ_STATUS_M3_H,
37 MT6332_IRQ_STATUS_M3_L,
38 MT6332_IRQ_STATUS_FG_BAT_H,
39 MT6332_IRQ_STATUS_FG_BAT_L,
40 MT6332_IRQ_STATUS_FG_CUR_H,
41 MT6332_IRQ_STATUS_FG_CUR_L,
42 MT6332_IRQ_STATUS_SPKL_D,
43 MT6332_IRQ_STATUS_SPKL_AB,
44 MT6332_IRQ_STATUS_BIF,
45 MT6332_IRQ_STATUS_VWLED_OC = 45,
46 MT6332_IRQ_STATUS_VDRAM_OC = 48,
47 MT6332_IRQ_STATUS_VDVFS2_OC,
48 MT6332_IRQ_STATUS_VRF1_OC,
49 MT6332_IRQ_STATUS_VRF2_OC,
50 MT6332_IRQ_STATUS_VPA_OC,
51 MT6332_IRQ_STATUS_VSBST_OC,
52 MT6332_IRQ_STATUS_LDO_OC,
53 MT6332_IRQ_STATUS_NR,
54 };
55
56 #define MT6332_IRQ_CON0_BASE MT6332_IRQ_STATUS_CHR_COMPLETE
57 #define MT6332_IRQ_CON0_BITS (MT6332_IRQ_STATUS_FLASH_VLED1_OPEN + 1)
58 #define MT6332_IRQ_CON1_BASE MT6332_IRQ_STATUS_OV
59 #define MT6332_IRQ_CON1_BITS (MT6332_IRQ_STATUS_FLASH_VLED2_OPEN - MT6332_IRQ_STATUS_OV + 1)
60 #define MT6332_IRQ_CON2_BASE MT6332_IRQ_STATUS_THR_H
61 #define MT6332_IRQ_CON2_BITS (MT6332_IRQ_STATUS_VWLED_OC - MT6332_IRQ_STATUS_THR_H + 1)
62 #define MT6332_IRQ_CON3_BASE MT6332_IRQ_STATUS_VDRAM_OC
63 #define MT6332_IRQ_CON3_BITS (MT6332_IRQ_STATUS_LDO_OC - MT6332_IRQ_STATUS_VDRAM_OC + 1)
64
65 #endif /* __MFD_MT6332_CORE_H__ */
66
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