1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Copyright (C) 2019 ROHM Semiconductors */
3
4 #ifndef __LINUX_MFD_BD71828_H__
5 #define __LINUX_MFD_BD71828_H__
6
7 #include <linux/bits.h>
8 #include <linux/mfd/rohm-generic.h>
9 #include <linux/mfd/rohm-shared.h>
10
11 /* Regulator IDs */
12 enum {
13 BD71828_BUCK1,
14 BD71828_BUCK2,
15 BD71828_BUCK3,
16 BD71828_BUCK4,
17 BD71828_BUCK5,
18 BD71828_BUCK6,
19 BD71828_BUCK7,
20 BD71828_LDO1,
21 BD71828_LDO2,
22 BD71828_LDO3,
23 BD71828_LDO4,
24 BD71828_LDO5,
25 BD71828_LDO6,
26 BD71828_LDO_SNVS,
27 BD71828_REGULATOR_AMOUNT,
28 };
29
30 #define BD71828_BUCK1267_VOLTS 0x100
31 #define BD71828_BUCK3_VOLTS 0x20
32 #define BD71828_BUCK4_VOLTS 0x40
33 #define BD71828_BUCK5_VOLTS 0x20
34 #define BD71828_LDO_VOLTS 0x40
35 /* LDO6 is fixed 1.8V voltage */
36 #define BD71828_LDO_6_VOLTAGE 1800000
37
38 /* Registers and masks*/
39
40 /* MODE control */
41 #define BD71828_REG_PS_CTRL_1 0x04
42 #define BD71828_REG_PS_CTRL_2 0x05
43 #define BD71828_REG_PS_CTRL_3 0x06
44
45 #define BD71828_MASK_STATE_HBNT BIT(1)
46
47 #define BD71828_MASK_RUN_LVL_CTRL 0x30
48
49 /* Regulator control masks */
50
51 #define BD71828_MASK_RAMP_DELAY 0x6
52
53 #define BD71828_MASK_RUN_EN 0x08
54 #define BD71828_MASK_SUSP_EN 0x04
55 #define BD71828_MASK_IDLE_EN 0x02
56 #define BD71828_MASK_LPSR_EN 0x01
57
58 #define BD71828_MASK_RUN0_EN 0x01
59 #define BD71828_MASK_RUN1_EN 0x02
60 #define BD71828_MASK_RUN2_EN 0x04
61 #define BD71828_MASK_RUN3_EN 0x08
62
63 #define BD71828_MASK_DVS_BUCK1_CTRL 0x10
64 #define BD71828_DVS_BUCK1_CTRL_I2C 0
65 #define BD71828_DVS_BUCK1_USE_RUNLVL 0x10
66
67 #define BD71828_MASK_DVS_BUCK2_CTRL 0x20
68 #define BD71828_DVS_BUCK2_CTRL_I2C 0
69 #define BD71828_DVS_BUCK2_USE_RUNLVL 0x20
70
71 #define BD71828_MASK_DVS_BUCK6_CTRL 0x40
72 #define BD71828_DVS_BUCK6_CTRL_I2C 0
73 #define BD71828_DVS_BUCK6_USE_RUNLVL 0x40
74
75 #define BD71828_MASK_DVS_BUCK7_CTRL 0x80
76 #define BD71828_DVS_BUCK7_CTRL_I2C 0
77 #define BD71828_DVS_BUCK7_USE_RUNLVL 0x80
78
79 #define BD71828_MASK_BUCK1267_VOLT 0xff
80 #define BD71828_MASK_BUCK3_VOLT 0x1f
81 #define BD71828_MASK_BUCK4_VOLT 0x3f
82 #define BD71828_MASK_BUCK5_VOLT 0x1f
83 #define BD71828_MASK_LDO_VOLT 0x3f
84
85 /* Regulator control regs */
86 #define BD71828_REG_BUCK1_EN 0x08
87 #define BD71828_REG_BUCK1_CTRL 0x09
88 #define BD71828_REG_BUCK1_MODE 0x0a
89 #define BD71828_REG_BUCK1_IDLE_VOLT 0x0b
90 #define BD71828_REG_BUCK1_SUSP_VOLT 0x0c
91 #define BD71828_REG_BUCK1_VOLT 0x0d
92
93 #define BD71828_REG_BUCK2_EN 0x12
94 #define BD71828_REG_BUCK2_CTRL 0x13
95 #define BD71828_REG_BUCK2_MODE 0x14
96 #define BD71828_REG_BUCK2_IDLE_VOLT 0x15
97 #define BD71828_REG_BUCK2_SUSP_VOLT 0x16
98 #define BD71828_REG_BUCK2_VOLT 0x17
99
100 #define BD71828_REG_BUCK3_EN 0x1c
101 #define BD71828_REG_BUCK3_MODE 0x1d
102 #define BD71828_REG_BUCK3_VOLT 0x1e
103
104 #define BD71828_REG_BUCK4_EN 0x1f
105 #define BD71828_REG_BUCK4_MODE 0x20
106 #define BD71828_REG_BUCK4_VOLT 0x21
107
108 #define BD71828_REG_BUCK5_EN 0x22
109 #define BD71828_REG_BUCK5_MODE 0x23
110 #define BD71828_REG_BUCK5_VOLT 0x24
111
112 #define BD71828_REG_BUCK6_EN 0x25
113 #define BD71828_REG_BUCK6_CTRL 0x26
114 #define BD71828_REG_BUCK6_MODE 0x27
115 #define BD71828_REG_BUCK6_IDLE_VOLT 0x28
116 #define BD71828_REG_BUCK6_SUSP_VOLT 0x29
117 #define BD71828_REG_BUCK6_VOLT 0x2a
118
119 #define BD71828_REG_BUCK7_EN 0x2f
120 #define BD71828_REG_BUCK7_CTRL 0x30
121 #define BD71828_REG_BUCK7_MODE 0x31
122 #define BD71828_REG_BUCK7_IDLE_VOLT 0x32
123 #define BD71828_REG_BUCK7_SUSP_VOLT 0x33
124 #define BD71828_REG_BUCK7_VOLT 0x34
125
126 #define BD71828_REG_LDO1_EN 0x39
127 #define BD71828_REG_LDO1_VOLT 0x3a
128 #define BD71828_REG_LDO2_EN 0x3b
129 #define BD71828_REG_LDO2_VOLT 0x3c
130 #define BD71828_REG_LDO3_EN 0x3d
131 #define BD71828_REG_LDO3_VOLT 0x3e
132 #define BD71828_REG_LDO4_EN 0x3f
133 #define BD71828_REG_LDO4_VOLT 0x40
134 #define BD71828_REG_LDO5_EN 0x41
135 #define BD71828_REG_LDO5_VOLT 0x43
136 #define BD71828_REG_LDO5_VOLT_OPT 0x42
137 #define BD71828_REG_LDO6_EN 0x44
138 #define BD71828_REG_LDO7_EN 0x45
139 #define BD71828_REG_LDO7_VOLT 0x46
140
141 /* GPIO */
142
143 #define BD71828_GPIO_DRIVE_MASK 0x2
144 #define BD71828_GPIO_OPEN_DRAIN 0x0
145 #define BD71828_GPIO_PUSH_PULL 0x2
146 #define BD71828_GPIO_OUT_HI 0x1
147 #define BD71828_GPIO_OUT_LO 0x0
148 #define BD71828_GPIO_OUT_MASK 0x1
149
150 #define BD71828_REG_GPIO_CTRL1 0x47
151 #define BD71828_REG_GPIO_CTRL2 0x48
152 #define BD71828_REG_GPIO_CTRL3 0x49
153 #define BD71828_REG_IO_STAT 0xed
154
155 /* clk */
156 #define BD71828_REG_OUT32K 0x4b
157
158 /* RTC */
159 #define BD71828_REG_RTC_SEC 0x4c
160 #define BD71828_REG_RTC_MINUTE 0x4d
161 #define BD71828_REG_RTC_HOUR 0x4e
162 #define BD71828_REG_RTC_WEEK 0x4f
163 #define BD71828_REG_RTC_DAY 0x50
164 #define BD71828_REG_RTC_MONTH 0x51
165 #define BD71828_REG_RTC_YEAR 0x52
166
167 #define BD71828_REG_RTC_ALM0_SEC 0x53
168 #define BD71828_REG_RTC_ALM_START BD71828_REG_RTC_ALM0_SEC
169 #define BD71828_REG_RTC_ALM0_MINUTE 0x54
170 #define BD71828_REG_RTC_ALM0_HOUR 0x55
171 #define BD71828_REG_RTC_ALM0_WEEK 0x56
172 #define BD71828_REG_RTC_ALM0_DAY 0x57
173 #define BD71828_REG_RTC_ALM0_MONTH 0x58
174 #define BD71828_REG_RTC_ALM0_YEAR 0x59
175 #define BD71828_REG_RTC_ALM0_MASK 0x61
176
177 #define BD71828_REG_RTC_ALM1_SEC 0x5a
178 #define BD71828_REG_RTC_ALM1_MINUTE 0x5b
179 #define BD71828_REG_RTC_ALM1_HOUR 0x5c
180 #define BD71828_REG_RTC_ALM1_WEEK 0x5d
181 #define BD71828_REG_RTC_ALM1_DAY 0x5e
182 #define BD71828_REG_RTC_ALM1_MONTH 0x5f
183 #define BD71828_REG_RTC_ALM1_YEAR 0x60
184 #define BD71828_REG_RTC_ALM1_MASK 0x62
185
186 #define BD71828_REG_RTC_ALM2 0x63
187 #define BD71828_REG_RTC_START BD71828_REG_RTC_SEC
188
189 /* Charger/Battey */
190 #define BD71828_REG_CHG_STATE 0x65
191 #define BD71828_REG_CHG_FULL 0xd2
192
193 /* LEDs */
194 #define BD71828_REG_LED_CTRL 0x4A
195 #define BD71828_MASK_LED_AMBER 0x80
196 #define BD71828_MASK_LED_GREEN 0x40
197 #define BD71828_LED_ON 0xff
198 #define BD71828_LED_OFF 0x0
199
200 /* IRQ registers */
201 #define BD71828_REG_INT_MASK_BUCK 0xd3
202 #define BD71828_REG_INT_MASK_DCIN1 0xd4
203 #define BD71828_REG_INT_MASK_DCIN2 0xd5
204 #define BD71828_REG_INT_MASK_VSYS 0xd6
205 #define BD71828_REG_INT_MASK_CHG 0xd7
206 #define BD71828_REG_INT_MASK_BAT 0xd8
207 #define BD71828_REG_INT_MASK_BAT_MON1 0xd9
208 #define BD71828_REG_INT_MASK_BAT_MON2 0xda
209 #define BD71828_REG_INT_MASK_BAT_MON3 0xdb
210 #define BD71828_REG_INT_MASK_BAT_MON4 0xdc
211 #define BD71828_REG_INT_MASK_TEMP 0xdd
212 #define BD71828_REG_INT_MASK_RTC 0xde
213
214 #define BD71828_REG_INT_MAIN 0xdf
215 #define BD71828_REG_INT_BUCK 0xe0
216 #define BD71828_REG_INT_DCIN1 0xe1
217 #define BD71828_REG_INT_DCIN2 0xe2
218 #define BD71828_REG_INT_VSYS 0xe3
219 #define BD71828_REG_INT_CHG 0xe4
220 #define BD71828_REG_INT_BAT 0xe5
221 #define BD71828_REG_INT_BAT_MON1 0xe6
222 #define BD71828_REG_INT_BAT_MON2 0xe7
223 #define BD71828_REG_INT_BAT_MON3 0xe8
224 #define BD71828_REG_INT_BAT_MON4 0xe9
225 #define BD71828_REG_INT_TEMP 0xea
226 #define BD71828_REG_INT_RTC 0xeb
227 #define BD71828_REG_INT_UPDATE 0xec
228
229 #define BD71828_MAX_REGISTER BD71828_REG_IO_STAT
230
231 /* Masks for main IRQ register bits */
232 enum {
233 BD71828_INT_BUCK,
234 #define BD71828_INT_BUCK_MASK BIT(BD71828_INT_BUCK)
235 BD71828_INT_DCIN,
236 #define BD71828_INT_DCIN_MASK BIT(BD71828_INT_DCIN)
237 BD71828_INT_VSYS,
238 #define BD71828_INT_VSYS_MASK BIT(BD71828_INT_VSYS)
239 BD71828_INT_CHG,
240 #define BD71828_INT_CHG_MASK BIT(BD71828_INT_CHG)
241 BD71828_INT_BAT,
242 #define BD71828_INT_BAT_MASK BIT(BD71828_INT_BAT)
243 BD71828_INT_BAT_MON,
244 #define BD71828_INT_BAT_MON_MASK BIT(BD71828_INT_BAT_MON)
245 BD71828_INT_TEMP,
246 #define BD71828_INT_TEMP_MASK BIT(BD71828_INT_TEMP)
247 BD71828_INT_RTC,
248 #define BD71828_INT_RTC_MASK BIT(BD71828_INT_RTC)
249 };
250
251 /* Interrupts */
252 enum {
253 /* BUCK reg interrupts */
254 BD71828_INT_BUCK1_OCP,
255 BD71828_INT_BUCK2_OCP,
256 BD71828_INT_BUCK3_OCP,
257 BD71828_INT_BUCK4_OCP,
258 BD71828_INT_BUCK5_OCP,
259 BD71828_INT_BUCK6_OCP,
260 BD71828_INT_BUCK7_OCP,
261 BD71828_INT_PGFAULT,
262 /* DCIN1 interrupts */
263 BD71828_INT_DCIN_DET,
264 BD71828_INT_DCIN_RMV,
265 BD71828_INT_CLPS_OUT,
266 BD71828_INT_CLPS_IN,
267 /* DCIN2 interrupts */
268 BD71828_INT_DCIN_MON_RES,
269 BD71828_INT_DCIN_MON_DET,
270 BD71828_INT_LONGPUSH,
271 BD71828_INT_MIDPUSH,
272 BD71828_INT_SHORTPUSH,
273 BD71828_INT_PUSH,
274 BD71828_INT_WDOG,
275 BD71828_INT_SWRESET,
276 /* Vsys */
277 BD71828_INT_VSYS_UV_RES,
278 BD71828_INT_VSYS_UV_DET,
279 BD71828_INT_VSYS_LOW_RES,
280 BD71828_INT_VSYS_LOW_DET,
281 BD71828_INT_VSYS_HALL_IN,
282 BD71828_INT_VSYS_HALL_TOGGLE,
283 BD71828_INT_VSYS_MON_RES,
284 BD71828_INT_VSYS_MON_DET,
285 /* Charger */
286 BD71828_INT_CHG_DCIN_ILIM,
287 BD71828_INT_CHG_TOPOFF_TO_DONE,
288 BD71828_INT_CHG_WDG_TEMP,
289 BD71828_INT_CHG_WDG_TIME,
290 BD71828_INT_CHG_RECHARGE_RES,
291 BD71828_INT_CHG_RECHARGE_DET,
292 BD71828_INT_CHG_RANGED_TEMP_TRANSITION,
293 BD71828_INT_CHG_STATE_TRANSITION,
294 /* Battery */
295 BD71828_INT_BAT_TEMP_NORMAL,
296 BD71828_INT_BAT_TEMP_ERANGE,
297 BD71828_INT_BAT_TEMP_WARN,
298 BD71828_INT_BAT_REMOVED,
299 BD71828_INT_BAT_DETECTED,
300 BD71828_INT_THERM_REMOVED,
301 BD71828_INT_THERM_DETECTED,
302 /* Battery Mon 1 */
303 BD71828_INT_BAT_DEAD,
304 BD71828_INT_BAT_SHORTC_RES,
305 BD71828_INT_BAT_SHORTC_DET,
306 BD71828_INT_BAT_LOW_VOLT_RES,
307 BD71828_INT_BAT_LOW_VOLT_DET,
308 BD71828_INT_BAT_OVER_VOLT_RES,
309 BD71828_INT_BAT_OVER_VOLT_DET,
310 /* Battery Mon 2 */
311 BD71828_INT_BAT_MON_RES,
312 BD71828_INT_BAT_MON_DET,
313 /* Battery Mon 3 (Coulomb counter) */
314 BD71828_INT_BAT_CC_MON1,
315 BD71828_INT_BAT_CC_MON2,
316 BD71828_INT_BAT_CC_MON3,
317 /* Battery Mon 4 */
318 BD71828_INT_BAT_OVER_CURR_1_RES,
319 BD71828_INT_BAT_OVER_CURR_1_DET,
320 BD71828_INT_BAT_OVER_CURR_2_RES,
321 BD71828_INT_BAT_OVER_CURR_2_DET,
322 BD71828_INT_BAT_OVER_CURR_3_RES,
323 BD71828_INT_BAT_OVER_CURR_3_DET,
324 /* Temperature */
325 BD71828_INT_TEMP_BAT_LOW_RES,
326 BD71828_INT_TEMP_BAT_LOW_DET,
327 BD71828_INT_TEMP_BAT_HI_RES,
328 BD71828_INT_TEMP_BAT_HI_DET,
329 BD71828_INT_TEMP_CHIP_OVER_125_RES,
330 BD71828_INT_TEMP_CHIP_OVER_125_DET,
331 BD71828_INT_TEMP_CHIP_OVER_VF_DET,
332 BD71828_INT_TEMP_CHIP_OVER_VF_RES,
333 /* RTC Alarm */
334 BD71828_INT_RTC0,
335 BD71828_INT_RTC1,
336 BD71828_INT_RTC2,
337 };
338
339 #define BD71828_INT_BUCK1_OCP_MASK 0x1
340 #define BD71828_INT_BUCK2_OCP_MASK 0x2
341 #define BD71828_INT_BUCK3_OCP_MASK 0x4
342 #define BD71828_INT_BUCK4_OCP_MASK 0x8
343 #define BD71828_INT_BUCK5_OCP_MASK 0x10
344 #define BD71828_INT_BUCK6_OCP_MASK 0x20
345 #define BD71828_INT_BUCK7_OCP_MASK 0x40
346 #define BD71828_INT_PGFAULT_MASK 0x80
347
348 #define BD71828_INT_DCIN_DET_MASK 0x1
349 #define BD71828_INT_DCIN_RMV_MASK 0x2
350 #define BD71828_INT_CLPS_OUT_MASK 0x4
351 #define BD71828_INT_CLPS_IN_MASK 0x8
352 /* DCIN2 interrupts */
353 #define BD71828_INT_DCIN_MON_RES_MASK 0x1
354 #define BD71828_INT_DCIN_MON_DET_MASK 0x2
355 #define BD71828_INT_LONGPUSH_MASK 0x4
356 #define BD71828_INT_MIDPUSH_MASK 0x8
357 #define BD71828_INT_SHORTPUSH_MASK 0x10
358 #define BD71828_INT_PUSH_MASK 0x20
359 #define BD71828_INT_WDOG_MASK 0x40
360 #define BD71828_INT_SWRESET_MASK 0x80
361 /* Vsys */
362 #define BD71828_INT_VSYS_UV_RES_MASK 0x1
363 #define BD71828_INT_VSYS_UV_DET_MASK 0x2
364 #define BD71828_INT_VSYS_LOW_RES_MASK 0x4
365 #define BD71828_INT_VSYS_LOW_DET_MASK 0x8
366 #define BD71828_INT_VSYS_HALL_IN_MASK 0x10
367 #define BD71828_INT_VSYS_HALL_TOGGLE_MASK 0x20
368 #define BD71828_INT_VSYS_MON_RES_MASK 0x40
369 #define BD71828_INT_VSYS_MON_DET_MASK 0x80
370 /* Charger */
371 #define BD71828_INT_CHG_DCIN_ILIM_MASK 0x1
372 #define BD71828_INT_CHG_TOPOFF_TO_DONE_MASK 0x2
373 #define BD71828_INT_CHG_WDG_TEMP_MASK 0x4
374 #define BD71828_INT_CHG_WDG_TIME_MASK 0x8
375 #define BD71828_INT_CHG_RECHARGE_RES_MASK 0x10
376 #define BD71828_INT_CHG_RECHARGE_DET_MASK 0x20
377 #define BD71828_INT_CHG_RANGED_TEMP_TRANSITION_MASK 0x40
378 #define BD71828_INT_CHG_STATE_TRANSITION_MASK 0x80
379 /* Battery */
380 #define BD71828_INT_BAT_TEMP_NORMAL_MASK 0x1
381 #define BD71828_INT_BAT_TEMP_ERANGE_MASK 0x2
382 #define BD71828_INT_BAT_TEMP_WARN_MASK 0x4
383 #define BD71828_INT_BAT_REMOVED_MASK 0x10
384 #define BD71828_INT_BAT_DETECTED_MASK 0x20
385 #define BD71828_INT_THERM_REMOVED_MASK 0x40
386 #define BD71828_INT_THERM_DETECTED_MASK 0x80
387 /* Battery Mon 1 */
388 #define BD71828_INT_BAT_DEAD_MASK 0x2
389 #define BD71828_INT_BAT_SHORTC_RES_MASK 0x4
390 #define BD71828_INT_BAT_SHORTC_DET_MASK 0x8
391 #define BD71828_INT_BAT_LOW_VOLT_RES_MASK 0x10
392 #define BD71828_INT_BAT_LOW_VOLT_DET_MASK 0x20
393 #define BD71828_INT_BAT_OVER_VOLT_RES_MASK 0x40
394 #define BD71828_INT_BAT_OVER_VOLT_DET_MASK 0x80
395 /* Battery Mon 2 */
396 #define BD71828_INT_BAT_MON_RES_MASK 0x1
397 #define BD71828_INT_BAT_MON_DET_MASK 0x2
398 /* Battery Mon 3 (Coulomb counter) */
399 #define BD71828_INT_BAT_CC_MON1_MASK 0x1
400 #define BD71828_INT_BAT_CC_MON2_MASK 0x2
401 #define BD71828_INT_BAT_CC_MON3_MASK 0x4
402 /* Battery Mon 4 */
403 #define BD71828_INT_BAT_OVER_CURR_1_RES_MASK 0x1
404 #define BD71828_INT_BAT_OVER_CURR_1_DET_MASK 0x2
405 #define BD71828_INT_BAT_OVER_CURR_2_RES_MASK 0x4
406 #define BD71828_INT_BAT_OVER_CURR_2_DET_MASK 0x8
407 #define BD71828_INT_BAT_OVER_CURR_3_RES_MASK 0x10
408 #define BD71828_INT_BAT_OVER_CURR_3_DET_MASK 0x20
409 /* Temperature */
410 #define BD71828_INT_TEMP_BAT_LOW_RES_MASK 0x1
411 #define BD71828_INT_TEMP_BAT_LOW_DET_MASK 0x2
412 #define BD71828_INT_TEMP_BAT_HI_RES_MASK 0x4
413 #define BD71828_INT_TEMP_BAT_HI_DET_MASK 0x8
414 #define BD71828_INT_TEMP_CHIP_OVER_125_RES_MASK 0x10
415 #define BD71828_INT_TEMP_CHIP_OVER_125_DET_MASK 0x20
416 #define BD71828_INT_TEMP_CHIP_OVER_VF_RES_MASK 0x40
417 #define BD71828_INT_TEMP_CHIP_OVER_VF_DET_MASK 0x80
418 /* RTC Alarm */
419 #define BD71828_INT_RTC0_MASK 0x1
420 #define BD71828_INT_RTC1_MASK 0x2
421 #define BD71828_INT_RTC2_MASK 0x4
422
423 #define BD71828_OUT_TYPE_MASK 0x2
424 #define BD71828_OUT_TYPE_OPEN_DRAIN 0x0
425 #define BD71828_OUT_TYPE_CMOS 0x2
426
427 #endif /* __LINUX_MFD_BD71828_H__ */
428
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