1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3 * Copyright (c) 2012 Samsung Electronics Co., Ltd
4 * http://www.samsung.com
5 */
6
7 #ifndef __LINUX_MFD_S2MPS11_H
8 #define __LINUX_MFD_S2MPS11_H
9
10 /* S2MPS11 registers */
11 enum s2mps11_reg {
12 S2MPS11_REG_ID,
13 S2MPS11_REG_INT1,
14 S2MPS11_REG_INT2,
15 S2MPS11_REG_INT3,
16 S2MPS11_REG_INT1M,
17 S2MPS11_REG_INT2M,
18 S2MPS11_REG_INT3M,
19 S2MPS11_REG_ST1,
20 S2MPS11_REG_ST2,
21 S2MPS11_REG_OFFSRC,
22 S2MPS11_REG_PWRONSRC,
23 S2MPS11_REG_RTC_CTRL,
24 S2MPS11_REG_CTRL1,
25 S2MPS11_REG_ETC_TEST,
26 S2MPS11_REG_RSVD3,
27 S2MPS11_REG_BU_CHG,
28 S2MPS11_REG_RAMP,
29 S2MPS11_REG_RAMP_BUCK,
30 S2MPS11_REG_LDO1_8,
31 S2MPS11_REG_LDO9_16,
32 S2MPS11_REG_LDO17_24,
33 S2MPS11_REG_LDO25_32,
34 S2MPS11_REG_LDO33_38,
35 S2MPS11_REG_LDO1_8_1,
36 S2MPS11_REG_LDO9_16_1,
37 S2MPS11_REG_LDO17_24_1,
38 S2MPS11_REG_LDO25_32_1,
39 S2MPS11_REG_LDO33_38_1,
40 S2MPS11_REG_OTP_ADRL,
41 S2MPS11_REG_OTP_ADRH,
42 S2MPS11_REG_OTP_DATA,
43 S2MPS11_REG_MON1SEL,
44 S2MPS11_REG_MON2SEL,
45 S2MPS11_REG_LEE,
46 S2MPS11_REG_RSVD_NO,
47 S2MPS11_REG_UVLO,
48 S2MPS11_REG_LEE_NO,
49 S2MPS11_REG_B1CTRL1,
50 S2MPS11_REG_B1CTRL2,
51 S2MPS11_REG_B2CTRL1,
52 S2MPS11_REG_B2CTRL2,
53 S2MPS11_REG_B3CTRL1,
54 S2MPS11_REG_B3CTRL2,
55 S2MPS11_REG_B4CTRL1,
56 S2MPS11_REG_B4CTRL2,
57 S2MPS11_REG_B5CTRL1,
58 S2MPS11_REG_BUCK5_SW,
59 S2MPS11_REG_B5CTRL2,
60 S2MPS11_REG_B5CTRL3,
61 S2MPS11_REG_B5CTRL4,
62 S2MPS11_REG_B5CTRL5,
63 S2MPS11_REG_B6CTRL1,
64 S2MPS11_REG_B6CTRL2,
65 S2MPS11_REG_B7CTRL1,
66 S2MPS11_REG_B7CTRL2,
67 S2MPS11_REG_B8CTRL1,
68 S2MPS11_REG_B8CTRL2,
69 S2MPS11_REG_B9CTRL1,
70 S2MPS11_REG_B9CTRL2,
71 S2MPS11_REG_B10CTRL1,
72 S2MPS11_REG_B10CTRL2,
73 S2MPS11_REG_L1CTRL,
74 S2MPS11_REG_L2CTRL,
75 S2MPS11_REG_L3CTRL,
76 S2MPS11_REG_L4CTRL,
77 S2MPS11_REG_L5CTRL,
78 S2MPS11_REG_L6CTRL,
79 S2MPS11_REG_L7CTRL,
80 S2MPS11_REG_L8CTRL,
81 S2MPS11_REG_L9CTRL,
82 S2MPS11_REG_L10CTRL,
83 S2MPS11_REG_L11CTRL,
84 S2MPS11_REG_L12CTRL,
85 S2MPS11_REG_L13CTRL,
86 S2MPS11_REG_L14CTRL,
87 S2MPS11_REG_L15CTRL,
88 S2MPS11_REG_L16CTRL,
89 S2MPS11_REG_L17CTRL,
90 S2MPS11_REG_L18CTRL,
91 S2MPS11_REG_L19CTRL,
92 S2MPS11_REG_L20CTRL,
93 S2MPS11_REG_L21CTRL,
94 S2MPS11_REG_L22CTRL,
95 S2MPS11_REG_L23CTRL,
96 S2MPS11_REG_L24CTRL,
97 S2MPS11_REG_L25CTRL,
98 S2MPS11_REG_L26CTRL,
99 S2MPS11_REG_L27CTRL,
100 S2MPS11_REG_L28CTRL,
101 S2MPS11_REG_L29CTRL,
102 S2MPS11_REG_L30CTRL,
103 S2MPS11_REG_L31CTRL,
104 S2MPS11_REG_L32CTRL,
105 S2MPS11_REG_L33CTRL,
106 S2MPS11_REG_L34CTRL,
107 S2MPS11_REG_L35CTRL,
108 S2MPS11_REG_L36CTRL,
109 S2MPS11_REG_L37CTRL,
110 S2MPS11_REG_L38CTRL,
111 };
112
113 /* S2MPS11 regulator ids */
114 enum s2mps11_regulators {
115 S2MPS11_LDO1,
116 S2MPS11_LDO2,
117 S2MPS11_LDO3,
118 S2MPS11_LDO4,
119 S2MPS11_LDO5,
120 S2MPS11_LDO6,
121 S2MPS11_LDO7,
122 S2MPS11_LDO8,
123 S2MPS11_LDO9,
124 S2MPS11_LDO10,
125 S2MPS11_LDO11,
126 S2MPS11_LDO12,
127 S2MPS11_LDO13,
128 S2MPS11_LDO14,
129 S2MPS11_LDO15,
130 S2MPS11_LDO16,
131 S2MPS11_LDO17,
132 S2MPS11_LDO18,
133 S2MPS11_LDO19,
134 S2MPS11_LDO20,
135 S2MPS11_LDO21,
136 S2MPS11_LDO22,
137 S2MPS11_LDO23,
138 S2MPS11_LDO24,
139 S2MPS11_LDO25,
140 S2MPS11_LDO26,
141 S2MPS11_LDO27,
142 S2MPS11_LDO28,
143 S2MPS11_LDO29,
144 S2MPS11_LDO30,
145 S2MPS11_LDO31,
146 S2MPS11_LDO32,
147 S2MPS11_LDO33,
148 S2MPS11_LDO34,
149 S2MPS11_LDO35,
150 S2MPS11_LDO36,
151 S2MPS11_LDO37,
152 S2MPS11_LDO38,
153 S2MPS11_BUCK1,
154 S2MPS11_BUCK2,
155 S2MPS11_BUCK3,
156 S2MPS11_BUCK4,
157 S2MPS11_BUCK5,
158 S2MPS11_BUCK6,
159 S2MPS11_BUCK7,
160 S2MPS11_BUCK8,
161 S2MPS11_BUCK9,
162 S2MPS11_BUCK10,
163
164 S2MPS11_REGULATOR_MAX,
165 };
166
167 #define S2MPS11_LDO_VSEL_MASK 0x3F
168 #define S2MPS11_BUCK_VSEL_MASK 0xFF
169 #define S2MPS11_BUCK9_VSEL_MASK 0x1F
170 #define S2MPS11_ENABLE_MASK (0x03 << S2MPS11_ENABLE_SHIFT)
171 #define S2MPS11_ENABLE_SHIFT 0x06
172 #define S2MPS11_LDO_N_VOLTAGES (S2MPS11_LDO_VSEL_MASK + 1)
173 #define S2MPS11_BUCK12346_N_VOLTAGES 153
174 #define S2MPS11_BUCK5_N_VOLTAGES 216
175 #define S2MPS11_BUCK7810_N_VOLTAGES 225
176 #define S2MPS11_BUCK9_N_VOLTAGES (S2MPS11_BUCK9_VSEL_MASK + 1)
177 #define S2MPS11_RAMP_DELAY 25000 /* uV/us */
178
179 #define S2MPS11_CTRL1_PWRHOLD_MASK BIT(4)
180
181 #define S2MPS11_BUCK2_RAMP_SHIFT 6
182 #define S2MPS11_BUCK34_RAMP_SHIFT 4
183 #define S2MPS11_BUCK5_RAMP_SHIFT 6
184 #define S2MPS11_BUCK16_RAMP_SHIFT 4
185 #define S2MPS11_BUCK7810_RAMP_SHIFT 2
186 #define S2MPS11_BUCK9_RAMP_SHIFT 0
187 #define S2MPS11_BUCK2_RAMP_EN_SHIFT 3
188 #define S2MPS11_BUCK3_RAMP_EN_SHIFT 2
189 #define S2MPS11_BUCK4_RAMP_EN_SHIFT 1
190 #define S2MPS11_BUCK6_RAMP_EN_SHIFT 0
191 #define S2MPS11_PMIC_EN_SHIFT 6
192
193 /*
194 * Bits for "enable suspend" (On/Off controlled by PWREN)
195 * are the same as in S2MPS14: S2MPS14_ENABLE_SUSPEND
196 */
197
198 #endif /* __LINUX_MFD_S2MPS11_H */
199
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