1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
4 * Author: Philippe Peurichard <philippe.peurichard@st.com>,
5 * Pascal Paillet <p.paillet@st.com> for STMicroelectronics.
6 */
7
8 #ifndef __LINUX_MFD_STPMIC1_H
9 #define __LINUX_MFD_STPMIC1_H
10
11 #define TURN_ON_SR 0x1
12 #define TURN_OFF_SR 0x2
13 #define ICC_LDO_TURN_OFF_SR 0x3
14 #define ICC_BUCK_TURN_OFF_SR 0x4
15 #define RREQ_STATE_SR 0x5
16 #define VERSION_SR 0x6
17
18 #define MAIN_CR 0x10
19 #define PADS_PULL_CR 0x11
20 #define BUCKS_PD_CR 0x12
21 #define LDO14_PD_CR 0x13
22 #define LDO56_VREF_PD_CR 0x14
23 #define VBUS_DET_VIN_CR 0x15
24 #define PKEY_TURNOFF_CR 0x16
25 #define BUCKS_MASK_RANK_CR 0x17
26 #define BUCKS_MASK_RESET_CR 0x18
27 #define LDOS_MASK_RANK_CR 0x19
28 #define LDOS_MASK_RESET_CR 0x1A
29 #define WCHDG_CR 0x1B
30 #define WCHDG_TIMER_CR 0x1C
31 #define BUCKS_ICCTO_CR 0x1D
32 #define LDOS_ICCTO_CR 0x1E
33
34 #define BUCK1_ACTIVE_CR 0x20
35 #define BUCK2_ACTIVE_CR 0x21
36 #define BUCK3_ACTIVE_CR 0x22
37 #define BUCK4_ACTIVE_CR 0x23
38 #define VREF_DDR_ACTIVE_CR 0x24
39 #define LDO1_ACTIVE_CR 0x25
40 #define LDO2_ACTIVE_CR 0x26
41 #define LDO3_ACTIVE_CR 0x27
42 #define LDO4_ACTIVE_CR 0x28
43 #define LDO5_ACTIVE_CR 0x29
44 #define LDO6_ACTIVE_CR 0x2A
45
46 #define BUCK1_STDBY_CR 0x30
47 #define BUCK2_STDBY_CR 0x31
48 #define BUCK3_STDBY_CR 0x32
49 #define BUCK4_STDBY_CR 0x33
50 #define VREF_DDR_STDBY_CR 0x34
51 #define LDO1_STDBY_CR 0x35
52 #define LDO2_STDBY_CR 0x36
53 #define LDO3_STDBY_CR 0x37
54 #define LDO4_STDBY_CR 0x38
55 #define LDO5_STDBY_CR 0x39
56 #define LDO6_STDBY_CR 0x3A
57
58 #define BST_SW_CR 0x40
59
60 #define INT_PENDING_R1 0x50
61 #define INT_PENDING_R2 0x51
62 #define INT_PENDING_R3 0x52
63 #define INT_PENDING_R4 0x53
64
65 #define INT_DBG_LATCH_R1 0x60
66 #define INT_DBG_LATCH_R2 0x61
67 #define INT_DBG_LATCH_R3 0x62
68 #define INT_DBG_LATCH_R4 0x63
69
70 #define INT_CLEAR_R1 0x70
71 #define INT_CLEAR_R2 0x71
72 #define INT_CLEAR_R3 0x72
73 #define INT_CLEAR_R4 0x73
74
75 #define INT_MASK_R1 0x80
76 #define INT_MASK_R2 0x81
77 #define INT_MASK_R3 0x82
78 #define INT_MASK_R4 0x83
79
80 #define INT_SET_MASK_R1 0x90
81 #define INT_SET_MASK_R2 0x91
82 #define INT_SET_MASK_R3 0x92
83 #define INT_SET_MASK_R4 0x93
84
85 #define INT_CLEAR_MASK_R1 0xA0
86 #define INT_CLEAR_MASK_R2 0xA1
87 #define INT_CLEAR_MASK_R3 0xA2
88 #define INT_CLEAR_MASK_R4 0xA3
89
90 #define INT_SRC_R1 0xB0
91 #define INT_SRC_R2 0xB1
92 #define INT_SRC_R3 0xB2
93 #define INT_SRC_R4 0xB3
94
95 #define PMIC_MAX_REGISTER_ADDRESS INT_SRC_R4
96
97 #define STPMIC1_PMIC_NUM_IRQ_REGS 4
98
99 #define TURN_OFF_SR_ICC_EVENT 0x08
100
101 #define LDO_VOLTAGE_MASK GENMASK(6, 2)
102 #define BUCK_VOLTAGE_MASK GENMASK(7, 2)
103 #define LDO_BUCK_VOLTAGE_SHIFT 2
104
105 #define LDO_ENABLE_MASK BIT(0)
106 #define BUCK_ENABLE_MASK BIT(0)
107
108 #define BUCK_HPLP_ENABLE_MASK BIT(1)
109 #define BUCK_HPLP_SHIFT 1
110
111 #define STDBY_ENABLE_MASK BIT(0)
112
113 #define BUCKS_PD_CR_REG_MASK GENMASK(7, 0)
114 #define BUCK_MASK_RANK_REGISTER_MASK GENMASK(3, 0)
115 #define BUCK_MASK_RESET_REGISTER_MASK GENMASK(3, 0)
116 #define LDO1234_PULL_DOWN_REGISTER_MASK GENMASK(7, 0)
117 #define LDO56_VREF_PD_CR_REG_MASK GENMASK(5, 0)
118 #define LDO_MASK_RANK_REGISTER_MASK GENMASK(5, 0)
119 #define LDO_MASK_RESET_REGISTER_MASK GENMASK(5, 0)
120
121 #define BUCK1_PULL_DOWN_REG BUCKS_PD_CR
122 #define BUCK1_PULL_DOWN_MASK BIT(0)
123 #define BUCK2_PULL_DOWN_REG BUCKS_PD_CR
124 #define BUCK2_PULL_DOWN_MASK BIT(2)
125 #define BUCK3_PULL_DOWN_REG BUCKS_PD_CR
126 #define BUCK3_PULL_DOWN_MASK BIT(4)
127 #define BUCK4_PULL_DOWN_REG BUCKS_PD_CR
128 #define BUCK4_PULL_DOWN_MASK BIT(6)
129
130 #define LDO1_PULL_DOWN_REG LDO14_PD_CR
131 #define LDO1_PULL_DOWN_MASK BIT(0)
132 #define LDO2_PULL_DOWN_REG LDO14_PD_CR
133 #define LDO2_PULL_DOWN_MASK BIT(2)
134 #define LDO3_PULL_DOWN_REG LDO14_PD_CR
135 #define LDO3_PULL_DOWN_MASK BIT(4)
136 #define LDO4_PULL_DOWN_REG LDO14_PD_CR
137 #define LDO4_PULL_DOWN_MASK BIT(6)
138 #define LDO5_PULL_DOWN_REG LDO56_VREF_PD_CR
139 #define LDO5_PULL_DOWN_MASK BIT(0)
140 #define LDO6_PULL_DOWN_REG LDO56_VREF_PD_CR
141 #define LDO6_PULL_DOWN_MASK BIT(2)
142 #define VREF_DDR_PULL_DOWN_REG LDO56_VREF_PD_CR
143 #define VREF_DDR_PULL_DOWN_MASK BIT(4)
144
145 #define BUCKS_ICCTO_CR_REG_MASK GENMASK(6, 0)
146 #define LDOS_ICCTO_CR_REG_MASK GENMASK(5, 0)
147
148 #define LDO_BYPASS_MASK BIT(7)
149
150 /* Main PMIC Control Register
151 * MAIN_CR
152 * Address : 0x10
153 */
154 #define OCP_OFF_DBG BIT(4)
155 #define PWRCTRL_POLARITY_HIGH BIT(3)
156 #define PWRCTRL_ENABLE BIT(2)
157 #define RESTART_REQUEST_ENABLE BIT(1)
158 #define SOFTWARE_SWITCH_OFF BIT(0)
159
160 /* Main PMIC PADS Control Register
161 * PADS_PULL_CR
162 * Address : 0x11
163 */
164 #define WAKEUP_DETECTOR_DISABLED BIT(4)
165 #define PWRCTRL_PD_ACTIVE BIT(3)
166 #define PWRCTRL_PU_ACTIVE BIT(2)
167 #define WAKEUP_PD_ACTIVE BIT(1)
168 #define PONKEY_PU_INACTIVE BIT(0)
169
170 /* Main PMIC VINLOW Control Register
171 * VBUS_DET_VIN_CRC DMSC
172 * Address : 0x15
173 */
174 #define SWIN_DETECTOR_ENABLED BIT(7)
175 #define SWOUT_DETECTOR_ENABLED BIT(6)
176 #define VINLOW_ENABLED BIT(0)
177 #define VINLOW_CTRL_REG_MASK GENMASK(7, 0)
178
179 /* USB Control Register
180 * Address : 0x40
181 */
182 #define BOOST_OVP_DISABLED BIT(7)
183 #define VBUS_OTG_DETECTION_DISABLED BIT(6)
184 #define SW_OUT_DISCHARGE BIT(5)
185 #define VBUS_OTG_DISCHARGE BIT(4)
186 #define OCP_LIMIT_HIGH BIT(3)
187 #define SWIN_SWOUT_ENABLED BIT(2)
188 #define USBSW_OTG_SWITCH_ENABLED BIT(1)
189 #define BOOST_ENABLED BIT(0)
190
191 /* PKEY_TURNOFF_CR
192 * Address : 0x16
193 */
194 #define PONKEY_PWR_OFF BIT(7)
195 #define PONKEY_CC_FLAG_CLEAR BIT(6)
196 #define PONKEY_TURNOFF_TIMER_MASK GENMASK(3, 0)
197 #define PONKEY_TURNOFF_MASK GENMASK(7, 0)
198
199 /*
200 * struct stpmic1 - stpmic1 master device for sub-drivers
201 * @dev: master device of the chip (can be used to access platform data)
202 * @irq: main IRQ number
203 * @regmap_irq_chip_data: irq chip data
204 */
205 struct stpmic1 {
206 struct device *dev;
207 struct regmap *regmap;
208 int irq;
209 struct regmap_irq_chip_data *irq_data;
210 };
211
212 #endif /* __LINUX_MFD_STPMIC1_H */
213
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