1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Header of ADC MFD core driver for sunxi platforms
3 *
4 * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
5 */
6
7 #ifndef __SUN4I_GPADC__H__
8 #define __SUN4I_GPADC__H__
9
10 #define SUN4I_GPADC_CTRL0 0x00
11
12 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x) ((GENMASK(7, 0) & (x)) << 24)
13 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE BIT(23)
14 #define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT BIT(22)
15 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x) ((GENMASK(1, 0) & (x)) << 20)
16 #define SUN4I_GPADC_CTRL0_FS_DIV(x) ((GENMASK(3, 0) & (x)) << 16)
17 #define SUN4I_GPADC_CTRL0_T_ACQ(x) (GENMASK(15, 0) & (x))
18
19 #define SUN4I_GPADC_CTRL1 0x04
20
21 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x) ((GENMASK(7, 0) & (x)) << 12)
22 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN BIT(9)
23 #define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(6)
24 #define SUN4I_GPADC_CTRL1_TP_DUAL_EN BIT(5)
25 #define SUN4I_GPADC_CTRL1_TP_MODE_EN BIT(4)
26 #define SUN4I_GPADC_CTRL1_TP_ADC_SELECT BIT(3)
27 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(2, 0) & (x))
28 #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(2, 0)
29
30 /* TP_CTRL1 bits for sun6i SOCs */
31 #define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN BIT(7)
32 #define SUN6I_GPADC_CTRL1_TP_DUAL_EN BIT(6)
33 #define SUN6I_GPADC_CTRL1_TP_MODE_EN BIT(5)
34 #define SUN6I_GPADC_CTRL1_TP_ADC_SELECT BIT(4)
35 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x) (GENMASK(3, 0) & BIT(x))
36 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK GENMASK(3, 0)
37
38 /* TP_CTRL1 bits for sun8i SoCs */
39 #define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN BIT(8)
40 #define SUN8I_GPADC_CTRL1_GPADC_CALI_EN BIT(7)
41
42 #define SUN4I_GPADC_CTRL2 0x08
43
44 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x) ((GENMASK(3, 0) & (x)) << 28)
45 #define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x) ((GENMASK(1, 0) & (x)) << 26)
46 #define SUN4I_GPADC_CTRL2_PRE_MEA_EN BIT(24)
47 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x) (GENMASK(23, 0) & (x))
48
49 #define SUN4I_GPADC_CTRL3 0x0c
50
51 #define SUN4I_GPADC_CTRL3_FILTER_EN BIT(2)
52 #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x) (GENMASK(1, 0) & (x))
53
54 #define SUN4I_GPADC_TPR 0x18
55
56 #define SUN4I_GPADC_TPR_TEMP_ENABLE BIT(16)
57 #define SUN4I_GPADC_TPR_TEMP_PERIOD(x) (GENMASK(15, 0) & (x))
58
59 #define SUN4I_GPADC_INT_FIFOC 0x10
60
61 #define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN BIT(18)
62 #define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN BIT(17)
63 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN BIT(16)
64 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE BIT(13)
65 #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)
66 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN BIT(7)
67 #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH BIT(4)
68 #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN BIT(1)
69 #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN BIT(0)
70
71 #define SUN4I_GPADC_INT_FIFOS 0x14
72
73 #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING BIT(18)
74 #define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING BIT(17)
75 #define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING BIT(16)
76 #define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG BIT(2)
77 #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING BIT(1)
78 #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING BIT(0)
79
80 #define SUN4I_GPADC_CDAT 0x1c
81 #define SUN4I_GPADC_TEMP_DATA 0x20
82 #define SUN4I_GPADC_DATA 0x24
83
84 #define SUN4I_GPADC_IRQ_FIFO_DATA 1
85 #define SUN4I_GPADC_IRQ_TEMP_DATA 2
86
87 /* 10s delay before suspending the IP */
88 #define SUN4I_GPADC_AUTOSUSPEND_DELAY 10000
89
90 struct sun4i_gpadc_dev {
91 struct device *dev;
92 struct regmap *regmap;
93 struct regmap_irq_chip_data *regmap_irqc;
94 void __iomem *base;
95 };
96
97 #endif
98
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