1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * pmic.h -- Power Management Driver for Wolfson WM8350 PMIC
4 *
5 * Copyright 2007 Wolfson Microelectronics PLC
6 */
7
8 #ifndef __LINUX_MFD_WM8350_PMIC_H
9 #define __LINUX_MFD_WM8350_PMIC_H
10
11 #include <linux/platform_device.h>
12 #include <linux/leds.h>
13 #include <linux/regulator/machine.h>
14
15 /*
16 * Register values.
17 */
18
19 #define WM8350_CURRENT_SINK_DRIVER_A 0xAC
20 #define WM8350_CSA_FLASH_CONTROL 0xAD
21 #define WM8350_CURRENT_SINK_DRIVER_B 0xAE
22 #define WM8350_CSB_FLASH_CONTROL 0xAF
23 #define WM8350_DCDC_LDO_REQUESTED 0xB0
24 #define WM8350_DCDC_ACTIVE_OPTIONS 0xB1
25 #define WM8350_DCDC_SLEEP_OPTIONS 0xB2
26 #define WM8350_POWER_CHECK_COMPARATOR 0xB3
27 #define WM8350_DCDC1_CONTROL 0xB4
28 #define WM8350_DCDC1_TIMEOUTS 0xB5
29 #define WM8350_DCDC1_LOW_POWER 0xB6
30 #define WM8350_DCDC2_CONTROL 0xB7
31 #define WM8350_DCDC2_TIMEOUTS 0xB8
32 #define WM8350_DCDC3_CONTROL 0xBA
33 #define WM8350_DCDC3_TIMEOUTS 0xBB
34 #define WM8350_DCDC3_LOW_POWER 0xBC
35 #define WM8350_DCDC4_CONTROL 0xBD
36 #define WM8350_DCDC4_TIMEOUTS 0xBE
37 #define WM8350_DCDC4_LOW_POWER 0xBF
38 #define WM8350_DCDC5_CONTROL 0xC0
39 #define WM8350_DCDC5_TIMEOUTS 0xC1
40 #define WM8350_DCDC6_CONTROL 0xC3
41 #define WM8350_DCDC6_TIMEOUTS 0xC4
42 #define WM8350_DCDC6_LOW_POWER 0xC5
43 #define WM8350_LIMIT_SWITCH_CONTROL 0xC7
44 #define WM8350_LDO1_CONTROL 0xC8
45 #define WM8350_LDO1_TIMEOUTS 0xC9
46 #define WM8350_LDO1_LOW_POWER 0xCA
47 #define WM8350_LDO2_CONTROL 0xCB
48 #define WM8350_LDO2_TIMEOUTS 0xCC
49 #define WM8350_LDO2_LOW_POWER 0xCD
50 #define WM8350_LDO3_CONTROL 0xCE
51 #define WM8350_LDO3_TIMEOUTS 0xCF
52 #define WM8350_LDO3_LOW_POWER 0xD0
53 #define WM8350_LDO4_CONTROL 0xD1
54 #define WM8350_LDO4_TIMEOUTS 0xD2
55 #define WM8350_LDO4_LOW_POWER 0xD3
56 #define WM8350_VCC_FAULT_MASKS 0xD7
57 #define WM8350_MAIN_BANDGAP_CONTROL 0xD8
58 #define WM8350_OSC_CONTROL 0xD9
59 #define WM8350_RTC_TICK_CONTROL 0xDA
60 #define WM8350_SECURITY 0xDB
61 #define WM8350_RAM_BIST_1 0xDC
62 #define WM8350_DCDC_LDO_STATUS 0xE1
63 #define WM8350_GPIO_PIN_STATUS 0xE6
64
65 #define WM8350_DCDC1_FORCE_PWM 0xF8
66 #define WM8350_DCDC3_FORCE_PWM 0xFA
67 #define WM8350_DCDC4_FORCE_PWM 0xFB
68 #define WM8350_DCDC6_FORCE_PWM 0xFD
69
70 /*
71 * R172 (0xAC) - Current Sink Driver A
72 */
73 #define WM8350_CS1_HIB_MODE 0x1000
74 #define WM8350_CS1_HIB_MODE_MASK 0x1000
75 #define WM8350_CS1_HIB_MODE_SHIFT 12
76 #define WM8350_CS1_ISEL_MASK 0x003F
77 #define WM8350_CS1_ISEL_SHIFT 0
78
79 /* Bit values for R172 (0xAC) */
80 #define WM8350_CS1_HIB_MODE_DISABLE 0
81 #define WM8350_CS1_HIB_MODE_LEAVE 1
82
83 #define WM8350_CS1_ISEL_220M 0x3F
84
85 /*
86 * R173 (0xAD) - CSA Flash control
87 */
88 #define WM8350_CS1_FLASH_MODE 0x8000
89 #define WM8350_CS1_TRIGSRC 0x4000
90 #define WM8350_CS1_DRIVE 0x2000
91 #define WM8350_CS1_FLASH_DUR_MASK 0x0300
92 #define WM8350_CS1_OFF_RAMP_MASK 0x0030
93 #define WM8350_CS1_ON_RAMP_MASK 0x0003
94
95 /*
96 * R174 (0xAE) - Current Sink Driver B
97 */
98 #define WM8350_CS2_HIB_MODE 0x1000
99 #define WM8350_CS2_ISEL_MASK 0x003F
100
101 /*
102 * R175 (0xAF) - CSB Flash control
103 */
104 #define WM8350_CS2_FLASH_MODE 0x8000
105 #define WM8350_CS2_TRIGSRC 0x4000
106 #define WM8350_CS2_DRIVE 0x2000
107 #define WM8350_CS2_FLASH_DUR_MASK 0x0300
108 #define WM8350_CS2_OFF_RAMP_MASK 0x0030
109 #define WM8350_CS2_ON_RAMP_MASK 0x0003
110
111 /*
112 * R176 (0xB0) - DCDC/LDO requested
113 */
114 #define WM8350_LS_ENA 0x8000
115 #define WM8350_LDO4_ENA 0x0800
116 #define WM8350_LDO3_ENA 0x0400
117 #define WM8350_LDO2_ENA 0x0200
118 #define WM8350_LDO1_ENA 0x0100
119 #define WM8350_DC6_ENA 0x0020
120 #define WM8350_DC5_ENA 0x0010
121 #define WM8350_DC4_ENA 0x0008
122 #define WM8350_DC3_ENA 0x0004
123 #define WM8350_DC2_ENA 0x0002
124 #define WM8350_DC1_ENA 0x0001
125
126 /*
127 * R177 (0xB1) - DCDC Active options
128 */
129 #define WM8350_PUTO_MASK 0x3000
130 #define WM8350_PWRUP_DELAY_MASK 0x0300
131 #define WM8350_DC6_ACTIVE 0x0020
132 #define WM8350_DC4_ACTIVE 0x0008
133 #define WM8350_DC3_ACTIVE 0x0004
134 #define WM8350_DC1_ACTIVE 0x0001
135
136 /*
137 * R178 (0xB2) - DCDC Sleep options
138 */
139 #define WM8350_DC6_SLEEP 0x0020
140 #define WM8350_DC4_SLEEP 0x0008
141 #define WM8350_DC3_SLEEP 0x0004
142 #define WM8350_DC1_SLEEP 0x0001
143
144 /*
145 * R179 (0xB3) - Power-check comparator
146 */
147 #define WM8350_PCCMP_ERRACT 0x4000
148 #define WM8350_PCCMP_RAIL 0x0100
149 #define WM8350_PCCMP_OFF_THR_MASK 0x0070
150 #define WM8350_PCCMP_ON_THR_MASK 0x0007
151
152 /*
153 * R180 (0xB4) - DCDC1 Control
154 */
155 #define WM8350_DC1_OPFLT 0x0400
156 #define WM8350_DC1_VSEL_MASK 0x007F
157 #define WM8350_DC1_VSEL_SHIFT 0
158
159 /*
160 * R181 (0xB5) - DCDC1 Timeouts
161 */
162 #define WM8350_DC1_ERRACT_MASK 0xC000
163 #define WM8350_DC1_ERRACT_SHIFT 14
164 #define WM8350_DC1_ENSLOT_MASK 0x3C00
165 #define WM8350_DC1_ENSLOT_SHIFT 10
166 #define WM8350_DC1_SDSLOT_MASK 0x03C0
167 #define WM8350_DC1_UVTO_MASK 0x0030
168 #define WM8350_DC1_SDSLOT_SHIFT 6
169
170 /* Bit values for R181 (0xB5) */
171 #define WM8350_DC1_ERRACT_NONE 0
172 #define WM8350_DC1_ERRACT_SHUTDOWN_CONV 1
173 #define WM8350_DC1_ERRACT_SHUTDOWN_SYS 2
174
175 /*
176 * R182 (0xB6) - DCDC1 Low Power
177 */
178 #define WM8350_DC1_HIB_MODE_MASK 0x7000
179 #define WM8350_DC1_HIB_TRIG_MASK 0x0300
180 #define WM8350_DC1_VIMG_MASK 0x007F
181
182 /*
183 * R183 (0xB7) - DCDC2 Control
184 */
185 #define WM8350_DC2_MODE 0x4000
186 #define WM8350_DC2_MODE_MASK 0x4000
187 #define WM8350_DC2_MODE_SHIFT 14
188 #define WM8350_DC2_HIB_MODE 0x1000
189 #define WM8350_DC2_HIB_MODE_MASK 0x1000
190 #define WM8350_DC2_HIB_MODE_SHIFT 12
191 #define WM8350_DC2_HIB_TRIG_MASK 0x0300
192 #define WM8350_DC2_HIB_TRIG_SHIFT 8
193 #define WM8350_DC2_ILIM 0x0040
194 #define WM8350_DC2_ILIM_MASK 0x0040
195 #define WM8350_DC2_ILIM_SHIFT 6
196 #define WM8350_DC2_RMP_MASK 0x0018
197 #define WM8350_DC2_RMP_SHIFT 3
198 #define WM8350_DC2_FBSRC_MASK 0x0003
199 #define WM8350_DC2_FBSRC_SHIFT 0
200
201 /* Bit values for R183 (0xB7) */
202 #define WM8350_DC2_MODE_BOOST 0
203 #define WM8350_DC2_MODE_SWITCH 1
204
205 #define WM8350_DC2_HIB_MODE_ACTIVE 1
206 #define WM8350_DC2_HIB_MODE_DISABLE 0
207
208 #define WM8350_DC2_HIB_TRIG_NONE 0
209 #define WM8350_DC2_HIB_TRIG_LPWR1 1
210 #define WM8350_DC2_HIB_TRIG_LPWR2 2
211 #define WM8350_DC2_HIB_TRIG_LPWR3 3
212
213 #define WM8350_DC2_ILIM_HIGH 0
214 #define WM8350_DC2_ILIM_LOW 1
215
216 #define WM8350_DC2_RMP_30V 0
217 #define WM8350_DC2_RMP_20V 1
218 #define WM8350_DC2_RMP_10V 2
219 #define WM8350_DC2_RMP_5V 3
220
221 #define WM8350_DC2_FBSRC_FB2 0
222 #define WM8350_DC2_FBSRC_ISINKA 1
223 #define WM8350_DC2_FBSRC_ISINKB 2
224 #define WM8350_DC2_FBSRC_USB 3
225
226 /*
227 * R184 (0xB8) - DCDC2 Timeouts
228 */
229 #define WM8350_DC2_ERRACT_MASK 0xC000
230 #define WM8350_DC2_ERRACT_SHIFT 14
231 #define WM8350_DC2_ENSLOT_MASK 0x3C00
232 #define WM8350_DC2_ENSLOT_SHIFT 10
233 #define WM8350_DC2_SDSLOT_MASK 0x03C0
234 #define WM8350_DC2_UVTO_MASK 0x0030
235
236 /* Bit values for R184 (0xB8) */
237 #define WM8350_DC2_ERRACT_NONE 0
238 #define WM8350_DC2_ERRACT_SHUTDOWN_CONV 1
239 #define WM8350_DC2_ERRACT_SHUTDOWN_SYS 2
240
241 /*
242 * R186 (0xBA) - DCDC3 Control
243 */
244 #define WM8350_DC3_OPFLT 0x0400
245 #define WM8350_DC3_VSEL_MASK 0x007F
246 #define WM8350_DC3_VSEL_SHIFT 0
247
248 /*
249 * R187 (0xBB) - DCDC3 Timeouts
250 */
251 #define WM8350_DC3_ERRACT_MASK 0xC000
252 #define WM8350_DC3_ERRACT_SHIFT 14
253 #define WM8350_DC3_ENSLOT_MASK 0x3C00
254 #define WM8350_DC3_ENSLOT_SHIFT 10
255 #define WM8350_DC3_SDSLOT_MASK 0x03C0
256 #define WM8350_DC3_UVTO_MASK 0x0030
257 #define WM8350_DC3_SDSLOT_SHIFT 6
258
259 /* Bit values for R187 (0xBB) */
260 #define WM8350_DC3_ERRACT_NONE 0
261 #define WM8350_DC3_ERRACT_SHUTDOWN_CONV 1
262 #define WM8350_DC3_ERRACT_SHUTDOWN_SYS 2
263 /*
264 * R188 (0xBC) - DCDC3 Low Power
265 */
266 #define WM8350_DC3_HIB_MODE_MASK 0x7000
267 #define WM8350_DC3_HIB_TRIG_MASK 0x0300
268 #define WM8350_DC3_VIMG_MASK 0x007F
269
270 /*
271 * R189 (0xBD) - DCDC4 Control
272 */
273 #define WM8350_DC4_OPFLT 0x0400
274 #define WM8350_DC4_VSEL_MASK 0x007F
275 #define WM8350_DC4_VSEL_SHIFT 0
276
277 /*
278 * R190 (0xBE) - DCDC4 Timeouts
279 */
280 #define WM8350_DC4_ERRACT_MASK 0xC000
281 #define WM8350_DC4_ERRACT_SHIFT 14
282 #define WM8350_DC4_ENSLOT_MASK 0x3C00
283 #define WM8350_DC4_ENSLOT_SHIFT 10
284 #define WM8350_DC4_SDSLOT_MASK 0x03C0
285 #define WM8350_DC4_UVTO_MASK 0x0030
286 #define WM8350_DC4_SDSLOT_SHIFT 6
287
288 /* Bit values for R190 (0xBE) */
289 #define WM8350_DC4_ERRACT_NONE 0
290 #define WM8350_DC4_ERRACT_SHUTDOWN_CONV 1
291 #define WM8350_DC4_ERRACT_SHUTDOWN_SYS 2
292
293 /*
294 * R191 (0xBF) - DCDC4 Low Power
295 */
296 #define WM8350_DC4_HIB_MODE_MASK 0x7000
297 #define WM8350_DC4_HIB_TRIG_MASK 0x0300
298 #define WM8350_DC4_VIMG_MASK 0x007F
299
300 /*
301 * R192 (0xC0) - DCDC5 Control
302 */
303 #define WM8350_DC5_MODE 0x4000
304 #define WM8350_DC5_MODE_MASK 0x4000
305 #define WM8350_DC5_MODE_SHIFT 14
306 #define WM8350_DC5_HIB_MODE 0x1000
307 #define WM8350_DC5_HIB_MODE_MASK 0x1000
308 #define WM8350_DC5_HIB_MODE_SHIFT 12
309 #define WM8350_DC5_HIB_TRIG_MASK 0x0300
310 #define WM8350_DC5_HIB_TRIG_SHIFT 8
311 #define WM8350_DC5_ILIM 0x0040
312 #define WM8350_DC5_ILIM_MASK 0x0040
313 #define WM8350_DC5_ILIM_SHIFT 6
314 #define WM8350_DC5_RMP_MASK 0x0018
315 #define WM8350_DC5_RMP_SHIFT 3
316 #define WM8350_DC5_FBSRC_MASK 0x0003
317 #define WM8350_DC5_FBSRC_SHIFT 0
318
319 /* Bit values for R192 (0xC0) */
320 #define WM8350_DC5_MODE_BOOST 0
321 #define WM8350_DC5_MODE_SWITCH 1
322
323 #define WM8350_DC5_HIB_MODE_ACTIVE 1
324 #define WM8350_DC5_HIB_MODE_DISABLE 0
325
326 #define WM8350_DC5_HIB_TRIG_NONE 0
327 #define WM8350_DC5_HIB_TRIG_LPWR1 1
328 #define WM8350_DC5_HIB_TRIG_LPWR2 2
329 #define WM8350_DC5_HIB_TRIG_LPWR3 3
330
331 #define WM8350_DC5_ILIM_HIGH 0
332 #define WM8350_DC5_ILIM_LOW 1
333
334 #define WM8350_DC5_RMP_30V 0
335 #define WM8350_DC5_RMP_20V 1
336 #define WM8350_DC5_RMP_10V 2
337 #define WM8350_DC5_RMP_5V 3
338
339 #define WM8350_DC5_FBSRC_FB2 0
340 #define WM8350_DC5_FBSRC_ISINKA 1
341 #define WM8350_DC5_FBSRC_ISINKB 2
342 #define WM8350_DC5_FBSRC_USB 3
343
344 /*
345 * R193 (0xC1) - DCDC5 Timeouts
346 */
347 #define WM8350_DC5_ERRACT_MASK 0xC000
348 #define WM8350_DC5_ERRACT_SHIFT 14
349 #define WM8350_DC5_ENSLOT_MASK 0x3C00
350 #define WM8350_DC5_ENSLOT_SHIFT 10
351 #define WM8350_DC5_SDSLOT_MASK 0x03C0
352 #define WM8350_DC5_UVTO_MASK 0x0030
353 #define WM8350_DC5_SDSLOT_SHIFT 6
354
355 /* Bit values for R193 (0xC1) */
356 #define WM8350_DC5_ERRACT_NONE 0
357 #define WM8350_DC5_ERRACT_SHUTDOWN_CONV 1
358 #define WM8350_DC5_ERRACT_SHUTDOWN_SYS 2
359
360 /*
361 * R195 (0xC3) - DCDC6 Control
362 */
363 #define WM8350_DC6_OPFLT 0x0400
364 #define WM8350_DC6_VSEL_MASK 0x007F
365 #define WM8350_DC6_VSEL_SHIFT 0
366
367 /*
368 * R196 (0xC4) - DCDC6 Timeouts
369 */
370 #define WM8350_DC6_ERRACT_MASK 0xC000
371 #define WM8350_DC6_ERRACT_SHIFT 14
372 #define WM8350_DC6_ENSLOT_MASK 0x3C00
373 #define WM8350_DC6_ENSLOT_SHIFT 10
374 #define WM8350_DC6_SDSLOT_MASK 0x03C0
375 #define WM8350_DC6_UVTO_MASK 0x0030
376 #define WM8350_DC6_SDSLOT_SHIFT 6
377
378 /* Bit values for R196 (0xC4) */
379 #define WM8350_DC6_ERRACT_NONE 0
380 #define WM8350_DC6_ERRACT_SHUTDOWN_CONV 1
381 #define WM8350_DC6_ERRACT_SHUTDOWN_SYS 2
382
383 /*
384 * R197 (0xC5) - DCDC6 Low Power
385 */
386 #define WM8350_DC6_HIB_MODE_MASK 0x7000
387 #define WM8350_DC6_HIB_TRIG_MASK 0x0300
388 #define WM8350_DC6_VIMG_MASK 0x007F
389
390 /*
391 * R199 (0xC7) - Limit Switch Control
392 */
393 #define WM8350_LS_ERRACT_MASK 0xC000
394 #define WM8350_LS_ERRACT_SHIFT 14
395 #define WM8350_LS_ENSLOT_MASK 0x3C00
396 #define WM8350_LS_ENSLOT_SHIFT 10
397 #define WM8350_LS_SDSLOT_MASK 0x03C0
398 #define WM8350_LS_SDSLOT_SHIFT 6
399 #define WM8350_LS_HIB_MODE 0x0010
400 #define WM8350_LS_HIB_MODE_MASK 0x0010
401 #define WM8350_LS_HIB_MODE_SHIFT 4
402 #define WM8350_LS_HIB_PROT 0x0002
403 #define WM8350_LS_HIB_PROT_MASK 0x0002
404 #define WM8350_LS_HIB_PROT_SHIFT 1
405 #define WM8350_LS_PROT 0x0001
406 #define WM8350_LS_PROT_MASK 0x0001
407 #define WM8350_LS_PROT_SHIFT 0
408
409 /* Bit values for R199 (0xC7) */
410 #define WM8350_LS_ERRACT_NONE 0
411 #define WM8350_LS_ERRACT_SHUTDOWN_CONV 1
412 #define WM8350_LS_ERRACT_SHUTDOWN_SYS 2
413
414 /*
415 * R200 (0xC8) - LDO1 Control
416 */
417 #define WM8350_LDO1_SWI 0x4000
418 #define WM8350_LDO1_OPFLT 0x0400
419 #define WM8350_LDO1_VSEL_MASK 0x001F
420 #define WM8350_LDO1_VSEL_SHIFT 0
421
422 /*
423 * R201 (0xC9) - LDO1 Timeouts
424 */
425 #define WM8350_LDO1_ERRACT_MASK 0xC000
426 #define WM8350_LDO1_ERRACT_SHIFT 14
427 #define WM8350_LDO1_ENSLOT_MASK 0x3C00
428 #define WM8350_LDO1_ENSLOT_SHIFT 10
429 #define WM8350_LDO1_SDSLOT_MASK 0x03C0
430 #define WM8350_LDO1_UVTO_MASK 0x0030
431 #define WM8350_LDO1_SDSLOT_SHIFT 6
432
433 /* Bit values for R201 (0xC9) */
434 #define WM8350_LDO1_ERRACT_NONE 0
435 #define WM8350_LDO1_ERRACT_SHUTDOWN_CONV 1
436 #define WM8350_LDO1_ERRACT_SHUTDOWN_SYS 2
437
438 /*
439 * R202 (0xCA) - LDO1 Low Power
440 */
441 #define WM8350_LDO1_HIB_MODE_MASK 0x3000
442 #define WM8350_LDO1_HIB_TRIG_MASK 0x0300
443 #define WM8350_LDO1_VIMG_MASK 0x001F
444 #define WM8350_LDO1_HIB_MODE_DIS (0x1 << 12)
445
446
447 /*
448 * R203 (0xCB) - LDO2 Control
449 */
450 #define WM8350_LDO2_SWI 0x4000
451 #define WM8350_LDO2_OPFLT 0x0400
452 #define WM8350_LDO2_VSEL_MASK 0x001F
453 #define WM8350_LDO2_VSEL_SHIFT 0
454
455 /*
456 * R204 (0xCC) - LDO2 Timeouts
457 */
458 #define WM8350_LDO2_ERRACT_MASK 0xC000
459 #define WM8350_LDO2_ERRACT_SHIFT 14
460 #define WM8350_LDO2_ENSLOT_MASK 0x3C00
461 #define WM8350_LDO2_ENSLOT_SHIFT 10
462 #define WM8350_LDO2_SDSLOT_MASK 0x03C0
463 #define WM8350_LDO2_SDSLOT_SHIFT 6
464
465 /* Bit values for R204 (0xCC) */
466 #define WM8350_LDO2_ERRACT_NONE 0
467 #define WM8350_LDO2_ERRACT_SHUTDOWN_CONV 1
468 #define WM8350_LDO2_ERRACT_SHUTDOWN_SYS 2
469
470 /*
471 * R205 (0xCD) - LDO2 Low Power
472 */
473 #define WM8350_LDO2_HIB_MODE_MASK 0x3000
474 #define WM8350_LDO2_HIB_TRIG_MASK 0x0300
475 #define WM8350_LDO2_VIMG_MASK 0x001F
476
477 /*
478 * R206 (0xCE) - LDO3 Control
479 */
480 #define WM8350_LDO3_SWI 0x4000
481 #define WM8350_LDO3_OPFLT 0x0400
482 #define WM8350_LDO3_VSEL_MASK 0x001F
483 #define WM8350_LDO3_VSEL_SHIFT 0
484
485 /*
486 * R207 (0xCF) - LDO3 Timeouts
487 */
488 #define WM8350_LDO3_ERRACT_MASK 0xC000
489 #define WM8350_LDO3_ERRACT_SHIFT 14
490 #define WM8350_LDO3_ENSLOT_MASK 0x3C00
491 #define WM8350_LDO3_ENSLOT_SHIFT 10
492 #define WM8350_LDO3_SDSLOT_MASK 0x03C0
493 #define WM8350_LDO3_UVTO_MASK 0x0030
494 #define WM8350_LDO3_SDSLOT_SHIFT 6
495
496 /* Bit values for R207 (0xCF) */
497 #define WM8350_LDO3_ERRACT_NONE 0
498 #define WM8350_LDO3_ERRACT_SHUTDOWN_CONV 1
499 #define WM8350_LDO3_ERRACT_SHUTDOWN_SYS 2
500
501 /*
502 * R208 (0xD0) - LDO3 Low Power
503 */
504 #define WM8350_LDO3_HIB_MODE_MASK 0x3000
505 #define WM8350_LDO3_HIB_TRIG_MASK 0x0300
506 #define WM8350_LDO3_VIMG_MASK 0x001F
507
508 /*
509 * R209 (0xD1) - LDO4 Control
510 */
511 #define WM8350_LDO4_SWI 0x4000
512 #define WM8350_LDO4_OPFLT 0x0400
513 #define WM8350_LDO4_VSEL_MASK 0x001F
514 #define WM8350_LDO4_VSEL_SHIFT 0
515
516 /*
517 * R210 (0xD2) - LDO4 Timeouts
518 */
519 #define WM8350_LDO4_ERRACT_MASK 0xC000
520 #define WM8350_LDO4_ERRACT_SHIFT 14
521 #define WM8350_LDO4_ENSLOT_MASK 0x3C00
522 #define WM8350_LDO4_ENSLOT_SHIFT 10
523 #define WM8350_LDO4_SDSLOT_MASK 0x03C0
524 #define WM8350_LDO4_UVTO_MASK 0x0030
525 #define WM8350_LDO4_SDSLOT_SHIFT 6
526
527 /* Bit values for R210 (0xD2) */
528 #define WM8350_LDO4_ERRACT_NONE 0
529 #define WM8350_LDO4_ERRACT_SHUTDOWN_CONV 1
530 #define WM8350_LDO4_ERRACT_SHUTDOWN_SYS 2
531
532 /*
533 * R211 (0xD3) - LDO4 Low Power
534 */
535 #define WM8350_LDO4_HIB_MODE_MASK 0x3000
536 #define WM8350_LDO4_HIB_TRIG_MASK 0x0300
537 #define WM8350_LDO4_VIMG_MASK 0x001F
538
539 /*
540 * R215 (0xD7) - VCC_FAULT Masks
541 */
542 #define WM8350_LS_FAULT 0x8000
543 #define WM8350_LDO4_FAULT 0x0800
544 #define WM8350_LDO3_FAULT 0x0400
545 #define WM8350_LDO2_FAULT 0x0200
546 #define WM8350_LDO1_FAULT 0x0100
547 #define WM8350_DC6_FAULT 0x0020
548 #define WM8350_DC5_FAULT 0x0010
549 #define WM8350_DC4_FAULT 0x0008
550 #define WM8350_DC3_FAULT 0x0004
551 #define WM8350_DC2_FAULT 0x0002
552 #define WM8350_DC1_FAULT 0x0001
553
554 /*
555 * R216 (0xD8) - Main Bandgap Control
556 */
557 #define WM8350_MBG_LOAD_FUSES 0x8000
558 #define WM8350_MBG_FUSE_WPREP 0x4000
559 #define WM8350_MBG_FUSE_WRITE 0x2000
560 #define WM8350_MBG_FUSE_TRIM_MASK 0x1F00
561 #define WM8350_MBG_TRIM_SRC 0x0020
562 #define WM8350_MBG_USER_TRIM_MASK 0x001F
563
564 /*
565 * R217 (0xD9) - OSC Control
566 */
567 #define WM8350_OSC_LOAD_FUSES 0x8000
568 #define WM8350_OSC_FUSE_WPREP 0x4000
569 #define WM8350_OSC_FUSE_WRITE 0x2000
570 #define WM8350_OSC_FUSE_TRIM_MASK 0x0F00
571 #define WM8350_OSC_TRIM_SRC 0x0020
572 #define WM8350_OSC_USER_TRIM_MASK 0x000F
573
574 /*
575 * R248 (0xF8) - DCDC1 Force PWM
576 */
577 #define WM8350_DCDC1_FORCE_PWM_ENA 0x0010
578
579 /*
580 * R250 (0xFA) - DCDC3 Force PWM
581 */
582 #define WM8350_DCDC3_FORCE_PWM_ENA 0x0010
583
584 /*
585 * R251 (0xFB) - DCDC4 Force PWM
586 */
587 #define WM8350_DCDC4_FORCE_PWM_ENA 0x0010
588
589 /*
590 * R253 (0xFD) - DCDC1 Force PWM
591 */
592 #define WM8350_DCDC6_FORCE_PWM_ENA 0x0010
593
594 /*
595 * DCDC's
596 */
597 #define WM8350_DCDC_1 0
598 #define WM8350_DCDC_2 1
599 #define WM8350_DCDC_3 2
600 #define WM8350_DCDC_4 3
601 #define WM8350_DCDC_5 4
602 #define WM8350_DCDC_6 5
603
604 /* DCDC modes */
605 #define WM8350_DCDC_ACTIVE_STANDBY 0
606 #define WM8350_DCDC_ACTIVE_PULSE 1
607 #define WM8350_DCDC_SLEEP_NORMAL 0
608 #define WM8350_DCDC_SLEEP_LOW 1
609
610 /* DCDC Low power (Hibernate) mode */
611 #define WM8350_DCDC_HIB_MODE_CUR (0 << 12)
612 #define WM8350_DCDC_HIB_MODE_IMAGE (1 << 12)
613 #define WM8350_DCDC_HIB_MODE_STANDBY (2 << 12)
614 #define WM8350_DCDC_HIB_MODE_LDO (4 << 12)
615 #define WM8350_DCDC_HIB_MODE_LDO_IM (5 << 12)
616 #define WM8350_DCDC_HIB_MODE_DIS (7 << 12)
617 #define WM8350_DCDC_HIB_MODE_MASK (7 << 12)
618
619 /* DCDC Low Power (Hibernate) signal */
620 #define WM8350_DCDC_HIB_SIG_REG (0 << 8)
621 #define WM8350_DCDC_HIB_SIG_LPWR1 (1 << 8)
622 #define WM8350_DCDC_HIB_SIG_LPWR2 (2 << 8)
623 #define WM8350_DCDC_HIB_SIG_LPWR3 (3 << 8)
624
625 /* LDO Low power (Hibernate) mode */
626 #define WM8350_LDO_HIB_MODE_IMAGE (0 << 0)
627 #define WM8350_LDO_HIB_MODE_DIS (1 << 0)
628
629 /* LDO Low Power (Hibernate) signal */
630 #define WM8350_LDO_HIB_SIG_REG (0 << 8)
631 #define WM8350_LDO_HIB_SIG_LPWR1 (1 << 8)
632 #define WM8350_LDO_HIB_SIG_LPWR2 (2 << 8)
633 #define WM8350_LDO_HIB_SIG_LPWR3 (3 << 8)
634
635 /*
636 * LDOs
637 */
638 #define WM8350_LDO_1 6
639 #define WM8350_LDO_2 7
640 #define WM8350_LDO_3 8
641 #define WM8350_LDO_4 9
642
643 /*
644 * ISINKs
645 */
646 #define WM8350_ISINK_A 10
647 #define WM8350_ISINK_B 11
648
649 #define WM8350_ISINK_MODE_BOOST 0
650 #define WM8350_ISINK_MODE_SWITCH 1
651 #define WM8350_ISINK_ILIM_NORMAL 0
652 #define WM8350_ISINK_ILIM_LOW 1
653
654 #define WM8350_ISINK_FLASH_DISABLE 0
655 #define WM8350_ISINK_FLASH_ENABLE 1
656 #define WM8350_ISINK_FLASH_TRIG_BIT 0
657 #define WM8350_ISINK_FLASH_TRIG_GPIO 1
658 #define WM8350_ISINK_FLASH_MODE_EN (1 << 13)
659 #define WM8350_ISINK_FLASH_MODE_DIS (0 << 13)
660 #define WM8350_ISINK_FLASH_DUR_32MS (0 << 8)
661 #define WM8350_ISINK_FLASH_DUR_64MS (1 << 8)
662 #define WM8350_ISINK_FLASH_DUR_96MS (2 << 8)
663 #define WM8350_ISINK_FLASH_DUR_1024MS (3 << 8)
664 #define WM8350_ISINK_FLASH_ON_INSTANT (0 << 0)
665 #define WM8350_ISINK_FLASH_ON_0_25S (1 << 0)
666 #define WM8350_ISINK_FLASH_ON_0_50S (2 << 0)
667 #define WM8350_ISINK_FLASH_ON_1_00S (3 << 0)
668 #define WM8350_ISINK_FLASH_ON_1_95S (1 << 0)
669 #define WM8350_ISINK_FLASH_ON_3_91S (2 << 0)
670 #define WM8350_ISINK_FLASH_ON_7_80S (3 << 0)
671 #define WM8350_ISINK_FLASH_OFF_INSTANT (0 << 4)
672 #define WM8350_ISINK_FLASH_OFF_0_25S (1 << 4)
673 #define WM8350_ISINK_FLASH_OFF_0_50S (2 << 4)
674 #define WM8350_ISINK_FLASH_OFF_1_00S (3 << 4)
675 #define WM8350_ISINK_FLASH_OFF_1_95S (1 << 4)
676 #define WM8350_ISINK_FLASH_OFF_3_91S (2 << 4)
677 #define WM8350_ISINK_FLASH_OFF_7_80S (3 << 4)
678
679 /*
680 * Regulator Interrupts.
681 */
682 #define WM8350_IRQ_CS1 13
683 #define WM8350_IRQ_CS2 14
684 #define WM8350_IRQ_UV_LDO4 25
685 #define WM8350_IRQ_UV_LDO3 26
686 #define WM8350_IRQ_UV_LDO2 27
687 #define WM8350_IRQ_UV_LDO1 28
688 #define WM8350_IRQ_UV_DC6 29
689 #define WM8350_IRQ_UV_DC5 30
690 #define WM8350_IRQ_UV_DC4 31
691 #define WM8350_IRQ_UV_DC3 32
692 #define WM8350_IRQ_UV_DC2 33
693 #define WM8350_IRQ_UV_DC1 34
694 #define WM8350_IRQ_OC_LS 35
695
696 #define NUM_WM8350_REGULATORS 12
697
698 struct wm8350;
699 struct platform_device;
700 struct regulator_init_data;
701
702 /*
703 * WM8350 LED platform data
704 */
705 struct wm8350_led_platform_data {
706 const char *name;
707 const char *default_trigger;
708 int max_uA;
709 };
710
711 struct wm8350_led {
712 struct platform_device *pdev;
713 struct work_struct work;
714 spinlock_t value_lock;
715 enum led_brightness value;
716 struct led_classdev cdev;
717 int max_uA_index;
718 int enabled;
719
720 struct regulator *isink;
721 struct regulator_consumer_supply isink_consumer;
722 struct regulator_init_data isink_init;
723 struct regulator *dcdc;
724 struct regulator_consumer_supply dcdc_consumer;
725 struct regulator_init_data dcdc_init;
726 };
727
728 struct wm8350_pmic {
729 /* Number of regulators of each type on this device */
730 int max_dcdc;
731 int max_isink;
732
733 /* ISINK to DCDC mapping */
734 int isink_A_dcdc;
735 int isink_B_dcdc;
736
737 /* hibernate configs */
738 u16 dcdc1_hib_mode;
739 u16 dcdc3_hib_mode;
740 u16 dcdc4_hib_mode;
741 u16 dcdc6_hib_mode;
742
743 /* regulator devices */
744 struct platform_device *pdev[NUM_WM8350_REGULATORS];
745
746 /* LED devices */
747 struct wm8350_led led[2];
748 };
749
750 int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
751 struct regulator_init_data *initdata);
752 int wm8350_register_led(struct wm8350 *wm8350, int lednum, int dcdc, int isink,
753 struct wm8350_led_platform_data *pdata);
754
755 /*
756 * Additional DCDC control not supported via regulator API
757 */
758 int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
759 u16 stop, u16 fault);
760 int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
761 u16 ilim, u16 ramp, u16 feedback);
762
763 /*
764 * Additional LDO control not supported via regulator API
765 */
766 int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
767
768 /*
769 * Additional ISINK control not supported via regulator API
770 */
771 int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
772 u16 trigger, u16 duration, u16 on_ramp,
773 u16 off_ramp, u16 drive);
774
775 #endif
776
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